CN103105514A - Oscilloscope with full-digital frequency counting function - Google Patents
Oscilloscope with full-digital frequency counting function Download PDFInfo
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- CN103105514A CN103105514A CN2011103599567A CN201110359956A CN103105514A CN 103105514 A CN103105514 A CN 103105514A CN 2011103599567 A CN2011103599567 A CN 2011103599567A CN 201110359956 A CN201110359956 A CN 201110359956A CN 103105514 A CN103105514 A CN 103105514A
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Abstract
The invention provides an oscilloscope with a full-digital frequency counting function. The oscilloscope comprises a data sampling unit, a numeric comparison unit, a trigger control unit, a sampling storage unit and a frequency counting unit. The frequency counting unit is used for generating gate time signals provided with gate time according to a system clock, and generates a frequency counting result according to the gate time, the total frequency of data changes of comparison data in the gate time, a first time difference between the starting moment and the first data change of the comparison data in the gate time, and a second time difference between the finishing moment of the gate time and the last data change of comparison data in the gate time. The frequency counting of the oscilloscope takes the first time difference and the second time difference into account. Therefore, a frequency measuring error can be reduced to zero, and the frequency counting accuracy of the oscilloscope is improved. Moreover, due to the fact that an analog comparator and a peripheral analog trigger circuit are not adopted, hardware cost is reduced.
Description
Technical field
The present invention relates to test, field of measuring technique, particularly relate to a kind of digital meter oscillograph of function frequently that has.
Background technology
Oscillograph is a kind of purposes electronic measuring instrument very widely, and present oscillograph mainly comprises two kinds: analog oscilloscope and digital oscilloscope.With reference to Fig. 1, show the structural representation of a kind of analog oscilloscope in prior art.Data sampling 101 pairs of the unit measured signal a of oscillograph 100 carries out data sampling, obtains digitized sampled data b; 102 couples of measured signal a of analog comparator compare processing, and measured signal a is converted to the comparison signal c that height changes, and are a square-wave signal; Trigger control unit 103 produces a Trig control signal d according to this comparison signal c, and samples storage unit 104 is stored sampled data b according to Trig control signal d, produces to be used for the waveform that waveform shows and to show data e.
With reference to Fig. 2, show the structural representation of a kind of digital oscilloscope in prior art.Data sampling 201 pairs of the unit measured signal a of oscillograph 200 carries out data sampling, obtains digitized sampled data b; 202 couples of sampled data b of digital comparator carry out the level comparison process, obtain digitized comparing data f, trigger control unit 203 produces a Trig control signal d according to this comparing data f, samples storage unit 204 is stored sampled data b according to Trig control signal d, produces waveform and shows data e.
Along with technical progress, oscillographic function is more and more perfect, and some oscillograph also can possess meter function frequently, and its Main Function is to facilitate the user in observation signal, can obtain accurately the frequency of measured signal.With reference to Fig. 3, show a kind of oscillographic structural representation with meter frequency function in prior art.Oscillograph 300 comprises data sampling unit 301, analog comparator 302, trigger control unit 303, samples storage unit 304 and frequency counting unit 305, and frequency counting unit 305 has T gate time for generation of one
0Time gate signal, and according to time gate signal, the comparison signal c that analog comparator 302 produces is carried out frequency counting, wherein, at T gate time
0Initial time, the beginning frequency counting; At T gate time
0The finish time, stop frequency counting, the final meter that produces frequently as a result g be the frequency values of measured signal a.With reference to Fig. 4, be the principle schematic of the frequency counting of prior art.
In conjunction with Fig. 3, frequency counting unit 305 generally makes the method frequently of using tricks carry out frequency counting.As shown in Fig. 4 (a), carry out the principle schematic of frequency counting for adopting the meter frequency method.The method usage comparison signal c is as meter clock frequently, calculates to have had in certain gate time what meters clocks frequently, and reference clock is for generation of time gate signal, when calculated rate according to formula: meter frequently as a result g=count the number of frequency clock/gate time T
0Can find out from Fig. 4 (a), because time gate signal is asynchronous with comparison signal c, the synchronous time is T, therefore can cause T gate time
0It not the integral multiple of comparison signal c.Because the method is not considered these two periods mistimings of T1, T2, the final meter frequency that produces g as a result has 0～1 frequency error.Wherein, T1 is T gate time
0In, first rising edge of comparison signal c is to T gate time
0Initial time between mistiming; T2 is T gate time
0In, last negative edge of comparison signal c is to T gate time
0The finish time between mistiming.
In addition, also has a kind of frequency counting method of counting all modes.As shown in Fig. 4 (b), carry out the principle schematic of frequency counting for adopting all modes of meter.The one-period of the method usage comparison signal c is as T gate time
0, utilize reference clock to remove to calculate the one-period of comparison signal c, the meter frequency final according to this cycle acquisition be g as a result.Can find out from Fig. 4 (b), because comparison signal c is asynchronous with reference clock, therefore can cause the cycle of comparison signal c is not the integral multiple of reference clock, and the cycle of the comparison signal c of actual measurement is T.Owing to not considering these two periods mistimings of T3, T4, same, also can therefore bring 0～1 frequency error.Wherein, T3 is T gate time
0In, first rising edge of reference clock is to T gate time
0Initial time between mistiming; T4 is T gate time
0In, last negative edge of reference clock is to T gate time
0The finish time between mistiming.
In addition, the frequency counting method that also has the precision mode such as a kind of.As shown in Fig. 4 (c), carry out the principle schematic of frequency counting for precision modes such as employings.The method with comparison signal c as clock, produce one that synchronize with comparison signal c, have a sync gate time T ' the sync gate time signal, then ', according to the sync gate time T ' converses the frequency of comparison signal to go to calculate sync gate time T in the sync gate time signal with reference clock.Can find out from Fig. 2 (c), due to the sync gate time T ' asynchronous with reference clock, the synchronous time is T, therefore can cause the sync gate time T ' not the integral multiple of reference clock.Owing to not considering these two periods mistimings of T5, T6, same, also can therefore bring 0～1 frequency error.Wherein, T5 is the sync gate time T ' in, first rising edge of reference clock is to the sync gate time T ' initial time between mistiming, the mistiming between the finish time that T6 is the sync gate time T ' in, last negative edge of reference clock is to the sync gate time T '.
Can find out, all there is the trueness error of frequency computation part in above-mentioned three kinds of methods.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of digital meter oscillograph of function frequently that has, and can improve oscillographic meter precision frequently.
In order to address the above problem, the invention discloses a kind of digital meter oscillograph of function frequently that has, comprising:
The data sampling unit is used for according to a sampling clock, digital sample being carried out in measured signal, obtains sampled data;
The numeral comparing unit is used for described sampled data is carried out the level comparison process, produces comparing data;
Trigger control unit is used for producing a Trig control signal according to described comparing data;
The samples storage unit is used for according to described Trig control signal, described sampled data being stored, and produces the waveform that is used for the waveform demonstration and shows data;
The frequency counting unit is used for producing the time gate signal with gate time according to a system clock; And according to the second mistiming between last data variation of data relatively in the finish time of poor, described gate time very first time between first data variation of data and described gate time relatively in total degree, the initial time of described gate time and the described gate time of the data variation of data relatively in described gate time, described gate time, the frequency result is counted in generation.
Compared with prior art, the present invention has the following advantages: the signal that the present invention is used for frequency counting is the comparing data of digital comparing unit output, and it is not counted as clock, but comes count frequency by the data variation of judgement comparing data; Simultaneously, the second mistiming between the finish time of having considered in the initial time of gate time and gate time poor and gate time very first time between first data variation of data relatively and last data variation of interior comparison gate time data, the measuring error of frequency is reduced to zero, has improved oscillographic meter precision frequently.
Illustrate as a kind of, frequency counting of the present invention unit is made of a programmable logic device (PLD).The present invention has saved the complete machine cost, fully without analog comparator, peripheral analog trigger circuitry, on the basis of existing digital oscilloscope, only depend on existing logical block, as FPGA, just can realize high-precision digital frequency meter, reduce hardware cost, reduced the hardware fault risk.
Illustrate as a kind of, data sampling of the present invention unit is used for respectively digital sample being carried out in the measured signal of a plurality of passages, obtains corresponding multi-channel sampling data; Described digital comparing unit is used for respectively described multi-channel sampling data being carried out the level comparison process, produce corresponding multichannel comparative result, and select wherein one road comparative result as the comparing data of described data comparing unit output from described multichannel comparative result.
As a kind of example, in originally illustrating, described data sampling unit also is used for an outside signal of introducing is carried out the signal comparison process, and in response to N the over-sampling clock that phase place is different, result after described signal comparison process is carried out digital sample, produce the over-sampling result; Described digital comparing unit also is used for selecting described over-sampling result as described comparing data.
As a kind of modification, in this example, described system clock and described sampling clock, over-sampling clock synchronous; The frequency of described sampling clock is the integral multiple of the frequency of described system clock; The frequency of described over-sampling clock is the integral multiple of the frequency of described system clock.
Illustrate as a kind of, frequency counting of the present invention unit comprises:
Data variation is searched module, is used for obtaining successively the monocycle data variation number of times of described comparing data according to described comparing data and described system clock;
The first phase inverter is used for described time gate signal is carried out anti-phase processing, produces a reset signal;
The number of times totalizer is used for according to described time gate signal and reset signal, to the operation that add up of the monocycle data variation number of times of described comparing data, obtains the total degree of the data variation of described gate time of interior comparison data.
As a kind of example, in originally illustrating, described data variation is searched module and also is used for one group of first initialize data of record, and described the first initialize data comprises: dissimilar comparing data and corresponding monocycle data variation number of times thereof; Described data variation is searched module and is used for obtaining described monocycle data variation number of times according to described comparing data and described system clock from described the first initialize data.
As a kind of example, in originally illustrating, described number of times totalizer is when described time gate signal is high level, to the operation that adds up of described monocycle data variation number of times; When described time gate signal is converted into low level by high level, the result of the cumulative operation of described monocycle data variation number of times is exported as the total degree of data variation; When described reset signal was high level, the cumulative zero clearing as a result that operates resetted to described monocycle data variation number of times.
Illustrate as a kind of, frequency counting of the present invention unit comprises:
First side is along searching module, be used for according to described comparing data, in a system clock cycle, produce the first edge position information of distance between expression first data variation of comparing data and described system clock cycle initial time, and produce simultaneously the id signal whether an expression has data variation;
Pretreatment module is used for carrying out level conversion according to described id signal and described time gate signal and processes, and produces an enable signal;
The second phase inverter is used for described time gate signal is carried out anti-phase processing, produces a reset signal;
The first totalizer is used for according to described enable signal and reset signal, to the operation that add up of described the first edge position information, and poor according to the result described very first time of acquisition that should cumulatively operate.
As a kind of example, in originally illustrating, described first side also is used for one group of second initialize data of record along searching module, and described the second initialize data comprises: dissimilar comparing data and corresponding the first edge position information thereof, whether the sign of data variation is arranged; Described first side is used for according to described comparing data and described system clock along searching module, produces described the first edge position information and described id signal from described the second initialize data.
As a kind of example, in originally illustrating, described pretreatment module comprises:
Latch, being used for initial value of output is low level latch signal, and when described id signal has been expressed as data variation for the first time within described gate time, described latch signal is converted to high level output;
Latch phase inverter, be used for described latch signal is carried out anti-phase processing, produce an inversion signal;
The logical and module is used for described time gate signal and inversion signal are carried out the logic and operation operation, produces described enable signal.
As a kind of example, in originally illustrating, described the first totalizer comprises:
The primary importance submodule that adds up is used for according to described enable signal and reset signal, to the operation that add up of described the first edge position information, and acquisition first position of adding up;
The very first time is obtained submodule, is used for according to one of the frequency of described sampling clock and frequency of over-sampling clock, the described first cumulative position is converted to the described very first time poor.
As a kind of modification, in example, the cumulative submodule of described primary importance is when described enable signal is high level, to the operation that adds up of described the first edge position information; When described enable signal is converted into low level by high level, the result of the cumulative operation of the first edge position information is exported as the first cumulative position; When reset signal was high level, the cumulative zero clearing as a result that operates resetted to the first edge position information.
Illustrate as a kind of, described frequency counting of the present invention unit comprises:
Second Edge is along searching module, be used for according to described comparing data, in a system clock cycle, produce last data variation of an expression comparing data and the second edge position information of described system clock cycle distance between the finish time, and when comparing data has data variation, produce simultaneously an override signal;
The 3rd phase inverter is used for described time gate signal is carried out anti-phase processing, produces a reset signal;
The second totalizer for according to described time gate signal, reset signal and override signal, adds up operation and result described the second mistiming of acquisition that operates according to adding up to described the second edge position information.
As a kind of example, in originally illustrating, described Second Edge also is used for one group of the 3rd initialize data of record along searching module, and described the 3rd initialize data comprises: dissimilar comparing data and corresponding the second edge position information thereof, whether the sign of data variation is arranged; Described second searches module is used for according to described comparing data and described system clock, produces described the second edge position information and described override signal from described the 3rd initialize data.
As a kind of example, in originally illustrating, described the second totalizer comprises:
The second place submodule that adds up is used for according to described time gate signal, reset signal and override signal, to described Second Edge along the positional value operation that add up, acquisition second position of adding up;
The second time was obtained submodule, was used for according to one of the frequency of described sampling clock and frequency of over-sampling clock, and the described second cumulative position is converted to described the second mistiming.
As a kind of modification, in example, the cumulative submodule of the described second place is when time gate signal is high level, to the operation that adds up of described the second edge position information; When getting described override signal, the cumulative result that operates of the second edge position information is updated to and produced simultaneously the second edge position information of described override signal; When described time gate signal is converted into low level by high level, the result of the cumulative operation of the second edge position information is exported as the second cumulative position; When reset signal was high level, the cumulative zero clearing as a result that operates resetted to the second edge position information.
Illustrate as a kind of, frequency counting of the present invention unit produces described meter frequency result according to the second mistiming between interior last data variation " 10 " that compares data of the finish time of poor, described gate time very first time between first data variation " 10 " of data and described gate time relatively in total degree, the initial time of described gate time and the described gate time of data variation " 10 " in data relatively in described gate time, described gate time.
Illustrate as a kind of, frequency counting of the present invention unit produces described meter frequency result according to the second mistiming between interior last data variation " 01 " that compares data of the finish time of poor, described gate time very first time between first data variation " 01 " of data and described gate time relatively in total degree, the initial time of described gate time and the described gate time of data variation " 01 " in data relatively in described gate time, described gate time.
Description of drawings
Fig. 1 is the structural representation of a kind of analog oscilloscope in prior art;
Fig. 2 is the structural representation of a kind of digital oscilloscope in prior art;
Fig. 3 is a kind of oscillographic structural representation with meter frequency function in prior art;
Fig. 4 is the principle schematic of the frequency counting of prior art;
Fig. 5 is a kind of structural representation with oscillograph embodiment of digital meter frequency function of the present invention;
Fig. 6 is a kind of illustrational structural representation of oscillograph embodiment of the present invention.
Fig. 7 is the schematic diagram of frequency counting of the present invention.
Fig. 8 is the structural representation of the described frequency counting of embodiment of the present invention unit;
Fig. 9 is the structural representation of the described data variation counter of the embodiment of the present invention;
Figure 10 is the structural representation of the described very first time counter of the embodiment of the present invention;
Figure 11 is the structural representation of described the second time counter of the embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
With reference to Fig. 5, show that the present invention is a kind of has the digital meter structural representation of the oscillograph embodiment of function frequently, the oscillograph 500 that the present embodiment proposes comprises: data sampling unit 501, digital comparing unit 502, trigger control unit 503, samples storage unit 504 and frequency counting unit 505.
Data sampling unit 501, it carries out digital sample according to a sampling clock h to measured signal a, obtains sampled data b;
Numeral comparing unit 502, it carries out the level comparison process to sampled data b, produces comparing data f;
In conjunction with Fig. 7, system clock i of frequency counting unit 505 foundations produces one and has T gate time
0Time gate signal j; And according to T gate time
0, gate time T
0The total degree m of the data variation of interior relatively data f, gate time T
0Initial time and gate time T
0Poor t1 of the very first time between first data variation of interior relatively data f, gate time T
0The finish time and gate time T
0The second mistiming t2 between last data variation of interior relatively data f produces meter frequency g as a result.
The described measured signal a of the present embodiment is inputed in data sampling unit 501 by oscillographic passage, and data sampling unit 501 is equivalent to analog to digital converter ADC, and it to the conversion that measured signal a carries out analog to digital, realizes data sampling according to sampling clock h; Afterwards, data sampling unit 501 is sent to the sampled data b that obtains respectively in digital comparing unit 502 and samples storage unit 504.General, also had an analog front circuit before data sampling unit 501, be used for realizing a series of operational processes of buffering, decay, limit bandwidth etc. to measured signal a.The specific implementation of analog front circuit can adopt multiple design proposal, is not giving unnecessary details herein.
Numeral comparing unit 502 is made of a series of viscous comparers usually, and each viscous comparer can be relatively precision of 8bit, and comparative level and viscous scope all can arrange.Can obtain two physics comparative levels after comparative level and the combination of viscous scope, be called the gentle lower level that powers on.If the sampled data b (8bit) of viscous comparer input is greater than upper level, viscous comparer output logic " 1 " (1bit); If the sampled data b of input is less than lower level, viscous comparer output logic " 0 " (1bit).
Frequency counting unit 505 produces according to system clock i has T gate time
0Time gate signal j, that is to say, desynchronize the zero hour and the finish time of gate time with system clock, can be that the rising edge of system clock is synchronous or negative edge is synchronous.The user can arrange T gate time as required
0Length, for example, can be set to: 100ms, 500ms, 1s etc.If gate time T
0Shorter, the meter of frequency counting unit 505 speed frequently; If gate time T
0Longer, g can be more accurate as a result frequently for the meter that obtains of frequency counting unit 505, this be because one gate time T
0In, frequency change often,, the frequency error that brings by average measured signal a (actual measurement for comparing data f) self shake, the error of g is less as a result frequently for the meter that records after average, it doesn't matter for the measuring error of frequency error and frequency, and frequency error is the error that test signal self is brought, and it does not belong to the error that produces in measuring process.In frequency measurement, frequency counting unit 505 is according to T gate time
0, gate time T
0Interior total degree m, the very first time poor t1, the second mistiming t2 that compares the data variation of data f produces meter frequency g as a result, and concrete frequency computation part method is:
1) when the total degree m of data variation is less than or equal to 1, the meter frequency is g=0 as a result;
2) as the total degree m of data variation greater than 1 the time, meter is g=(the total degree m-1 of data variation)/(gate time T as a result frequently
0Poor t1-the second mistiming t2 of-very first time).
One of difference with the prior art of the present invention is, prior art with the comparison signal c of analog comparator output as clock, comparison signal c and gate time T
0Be asynchronous relationship, therefore can't calculate T1, T2, and the present invention is used for the comparing data that the signal of frequency counting is digital comparing unit output, it is not counted as clock, but comes count frequency by the data variation of judgement comparing data; In addition, the present invention has considered T gate time
0Initial time and gate time T
0Poor t1 of the very first time between first data variation of interior relatively data f and gate time T
0The finish time and gate time T
0The second mistiming t2 between last data variation of interior relatively data f, with the measuring error of frequency, namely meter frequency error is reduced to zero, has improved oscillographic meter precision frequently.
Be understandable that, 505 actual measurements of frequency counting unit be the frequency of comparing data f, still, due to comparing data f by measured signal a sample, level ratio obtains, therefore, the frequency of the comparing data f that measures is equivalent to the frequency of measured signal a.
Need to prove, described oscillograph 500 can also comprise a central control unit, be used for data sampling unit 501, digital comparing unit 502, trigger control unit 503, samples storage unit 504 and frequency counting unit 505 are controlled and the parameter setting, for example, comparative level and the viscous scope of digital comparing unit 502 are set, the generation of control gate time signal j, the meter frequency that reading frequency counting unit 505 produces is g as a result, the demonstration of control waveform data, meter frequency result etc.
Illustrate as one, the described frequency counting of the present embodiment unit 505 can be made of a programmable logic device (PLD).As, can be consisted of by devices such as FPGA or CPLD.In addition, this programmable logic device (PLD) can also the integrated digital sampling, level ratio, trigger control, samples storage and to data sampling, level ratio, the control function of the operations such as samples storage, waveform demonstration, various functions are integrated in one, both reduce the volume of digital oscilloscope, saved again cost.
The meter frequency method of prior art all need to be converted to the measured signal of input by analog comparator the comparison signal of height variation, adopt the meter frequency method of simulation, before its analog comparator, peripheral circuit must be arranged, analog trigger circuitry for example, it has brought extra hardware cost, also increases the risk of hardware fault simultaneously.The present invention has saved the complete machine cost, fully without analog comparator, peripheral analog trigger circuitry, on the basis of existing digital oscilloscope, only depend on existing logical block, as FPGA, just can realize high-precision digital frequency meter, reduce hardware cost, reduced the hardware fault risk.
Illustrate as one, the described data sampling of the present embodiment unit 501 can be respectively carries out digital sample to the measured signal a of a plurality of passages, obtains corresponding multi-channel sampling data b; Numeral comparing unit 502 carries out the level comparison process to the multi-channel sampling data b respectively, produces corresponding multichannel comparative result k, and the comparing data f that selects one road comparative result wherein to export as data comparing unit 501 from multichannel comparative result k.
With reference to Fig. 6, be a kind of illustrational structural representation of oscillograph embodiment of the present invention.Data sampling unit 501 comprises ADC1 and ADC2, and ADC1 carries out digital sample to the measured signal a1 of passage 1, obtains one tunnel sampled data b1, and ADC2 carries out digital sample to the measured signal a2 of passage 2, obtains another road sampled data b2.Numeral comparing unit 502 comprises relatively subelement 5021 and 5022 of two numerals, respectively sampled data b1 and sampled data b2 is carried out the level comparison process, produces corresponding two-way comparative result k1 and k2; Numeral comparing unit 502 also comprises a channel to channel adapter 5023, be used for selecting frequency counting and trigger the data source of controlling, that is, select wherein one road comparative result from two-way comparative result k1 and k2, with its comparing data f as 502 outputs of data comparing unit.
Illustrate as another, the described data sampling of the present embodiment unit 501 also is used for an outside signal p that introduces is carried out the signal comparison process, and in response to N the over-sampling clock q that phase place is different, result after the signal comparison process is carried out digital sample, produce over-sampling r as a result, digital comparing unit 502 is selected over-samplings r data f as a comparison as a result.
With reference to Fig. 6, data sampling unit 501 can also comprise an external trigger comparer 5011 and an over-sampling subelement 5012, external trigger comparer 5011 is by the signal comparison process, signal p is introduced in the outside change the precipitous external trigger signal s in edge into, the signal that outside introducing signal p can be external clock, circuit under test etc.Over-sampling subelement 5012 is in response to N the over-sampling clock q that phase place is different, and externally trigger pip s carries out the Parallel Digital sampling, obtains N and passes by sampled data, afterwards, according to the time sequencing of Parallel Digital sampling, N is passed by sampled data carry out the cross arrangement combination, produce over-sampling r as a result; Channel to channel adapter 5023 can be selected over-sampling, and r is as the comparing data f of data comparing unit 502 output as a result, and trigger control unit 503 can produce Trig control signal d according to by the over-sampling comparing data f that obtains of r as a result, realizes the external trigger function.Frequency counting unit 505 carries out frequency counting according to this comparing data f.Same, carry out processings such as over-sampling and obtain because this comparing data f introduces signal p by the outside, therefore, in this situation, the frequency of the comparing data f that measures is equivalent to the frequency of outside introducing signal p.
Can find out from originally illustrating, frequency counting unit 505 both can have been counted the frequency of measured signal a, also can count the frequency that signal p is introduced in the outside that is used for realizing external trigger.
As a kind of example, originally illustrate described system clock i and synchronize with sampling clock h, over-sampling clock q; The frequency of sampling clock h can be the integral multiple of the frequency of system clock i; The frequency of over-sampling clock q can be the integral multiple of the frequency of system clock i.
As a kind of example, originally illustrate total clock (being also the processing clock of programmable logic device (PLD)) that described system clock i can refer to system of Oscillograph inside, can produce sampling clock h and over-sampling clock q according to system clock i.Illustrate as another kind, system clock i of the present invention can not be total clock of system of Oscillograph inside, system clock i is only for generation of time gate signal j, and system clock i, sampling clock h, over-sampling clock q all can produce according to total clock of internal system.
Illustrate as one, with reference to Fig. 7 (a) and in conjunction with Fig. 5, the described frequency counting of the present embodiment unit 505 can be according to T gate time
0, in gate time relatively the total degree m of data variation " 01 " in data f, gate time T
0Initial time and gate time T
0Poor t1 of the very first time between first data variation " 01 " of interior relatively data f, gate time T
0The finish time and gate time T
0The second mistiming t2 between last data variation " 01 " of interior relatively data f produces meter frequency g as a result., the mode shown in Fig. 7 (a) is equivalent to carry out frequency counting according to the rising edge of comparing data.
Illustrate as another, with reference to Fig. 7 (b) and in conjunction with Fig. 5, the described frequency counting of the present embodiment unit 505 can be according to T gate time
0, in gate time relatively the total degree m of data variation " 10 " in data f, gate time T
0Initial time and gate time T
0Poor t1 of the very first time between first data variation " 10 " of interior relatively data f, gate time T
0The finish time and gate time T
0The second mistiming t2 between last data variation " 10 " of interior relatively data f produces meter frequency g as a result., the mode shown in Fig. 7 (b) is equivalent to carry out frequency counting according to the negative edge of comparing data.
Illustrate as one, as shown in Figure 8, the described frequency counting of the present embodiment unit 505 can comprise: gate time, generator 81, and it produces according to system clock i has T gate time
0Time gate signal j; Data variation counter 82, it obtains T gate time according to comparing data f, system clock i and time gate signal j
0The interior relatively total degree m of the data variation of data f; Very first time counter 83, it obtains T gate time according to comparing data f, system clock i and time gate signal j
0Initial time and gate time T
0Poor t1 of the very first time between first data variation of interior relatively data f; The second time counter 84, it obtains T gate time according to comparing data f, system clock i and time gate signal j
0The finish time and gate time T
0The second mistiming t2 between last data variation of interior relatively data f; Frequency counter 85, its total degree m according to data variation, poor t1 of the very first time and the second mistiming t2 produce meter frequency g as a result.
In originally illustrating, as shown in Figure 9, data variation counter 82 specifically can comprise:
Data variation is searched module 821, and it obtains the monocycle data variation frequency n of comparing data f successively according to comparing data f and system clock i;
The first phase inverter 822, it carries out anti-phase processing to time gate signal j, produces a reset signal y;
Number of times totalizer 823, it is according to time gate signal j and reset signal y, to the operation that add up of the monocycle data variation frequency n of data f relatively, acquisition T gate time
0The interior relatively total degree m of the data variation of data f.
As a kind of example, in illustrating, data variation is searched module 821 and also is used for one group of first initialize data of record, and described the first initialize data comprises: dissimilar comparing data and corresponding monocycle data variation number of times thereof; Data variation is searched module 821 according to comparing data f and system clock i, obtains monocycle data variation frequency n from described the first initialize data.Described the first initialize data can exist with the form of tables of data.
Take a system clock cycle 8bit comparing data as example, as shown in table 1, be one group of first initialize data that frequently records according to data variation " 01 " (rising edge) meter, last classifying as: the data that the comparing data of last data of previous system clock cycle (last bit) and current system clock period forms, it is from left to right arranged according to the time order and function order, and rear one classifies as and data variation number of times of corresponding monocycle of dissimilar comparing data.As example, table 1 has only provided the wherein part of the first initialize data, and remaining data is omitted herein.
Table 1
In this example, when opening meter frequency function, data variation is searched module 821 successively in each system clock cycle, last Bit data and the comparing data of current system clock period according to last system clock cycle, search in the first initialize data, obtain the monocycle data variation frequency n corresponding with it, and input in number of times totalizer 823.Time gate signal j controls beginning and the end of the 823 cumulative operations of number of times totalizer as the enable signal of number of times totalizer 823, according to reset signal y, the zero clearing as a result of cumulative operation is resetted simultaneously.
As a kind of example, in originally illustrating, number of times totalizer 823 (is equivalent to T gate time when being high level at time gate signal j
0Time period), to the operation that adds up of monocycle data variation frequency n; When being converted into low level by high level, time gate signal j (is equivalent to T gate time
0The finish time), preserve the result of the cumulative operation of monocycle data variation frequency n, with its total degree m output as data variation; When reset signal y was high level, the cumulative zero clearing as a result that operates resetted to monocycle data variation frequency n.As another kind of example, number of times totalizer 823 can also be when time gate signal j be low level, to the operation that adds up of monocycle data variation frequency n; When time gate signal j is converted into high level by low level, with the total degree m output of this cumulative result that operates as data variation; When reset signal y is low level, this cumulative zero clearing as a result that operates is resetted.
In originally illustrating, as shown in figure 10, very first time counter 83 specifically can comprise:
First side is along searching module 831, be used for according to comparing data f, in a system clock cycle, produce the first edge position information x1 of distance between first data variation of an expression comparing data f and this system clock cycle initial time, and produce simultaneously the id signal u whether an expression has data variation;
Pretreatment module 832 is used for carrying out level conversion according to id signal u and time gate signal j and processes, and produces an enable signal v;
The second phase inverter 833 is used for time gate signal j is carried out anti-phase processing, produces a reset signal y;
The first totalizer 834 is used for according to enable signal v and reset signal y, to the first edge position information x1 operation that add up, and according to result acquisition very first time difference t1 that should cumulative operation.
As a kind of example, in illustrating, first side also is used for one group of second initialize data of record along searching module 831, and described the second initialize data comprises: dissimilar comparing data and corresponding the first edge position information thereof, whether the sign of data variation is arranged; First side produces the first edge position information x1 and id signal u along searching module 831 according to comparing data f and system clock i from described the second initialize data.Described the second initialize data can exist with the form of tables of data.
take a system clock cycle 8bit comparing data as example, as shown in table 2, be one group of second initialize data that frequently records according to data variation " 01 " (rising edge) meter, first classifies as: the data that the comparing data of last data of previous system clock cycle (last bit) and current system clock period forms, it is from left to right arranged according to the time order and function order, second classifies as and corresponding the first edge position information of dissimilar comparing data, the 3rd classifies the sign whether data variation is arranged as, in this example, there is no data variation with sign " 0 " expression, with sign " 1 " expression, data variation is arranged.As example, table 2 has only provided the wherein part of the second initialize data, and remaining data is omitted herein.
Table 2
In this example, with reference to Figure 10, when opening meter frequency function, first side is along searching module 831 successively in each system clock cycle, last Bit data and the comparing data of current system clock period according to last system clock cycle, search in the second initialize data, obtain the first edge position information x1 corresponding with it, and input in the first totalizer 834; In addition, by searching in the second initialize data, when producing the first edge position information x1, also can produce the id signal u whether an expression has data variation, and id signal u is inputed in pretreatment module 832.Pretreatment module 832 is carried out the level conversion processing according to id signal u and time gate signal j, produces an enable signal v that beginning and the result of the cumulative operation of the first totalizer are controlled.
As a kind of example, as shown in figure 10, in originally illustrating, pretreatment module 832 comprises:
Latch phase inverter 1002, it carries out anti-phase processing to latch signal w, produces an inversion signal z;
Logical and module 1003, it carries out the logic and operation operation to time gate signal j and inversion signal z, produces enable signal v.
As a kind of example, the first totalizer 814 can comprise:
The primary importance submodule that adds up, it is according to enable signal v and reset signal y, to the first edge position information x1 operation that adds up, obtains the first cumulative position;
The very first time is obtained submodule, and it is converted to poor t1 of the very first time according to one of the frequency of sampling clock and frequency of over-sampling clock with the first cumulative position.
In this example, the effect of the cumulative submodule of primary importance is exactly that first side is always cumulative along the first edge position information x1 that searches module 831 outputs, until till first data variation, stop adding up, the first cumulative position that draws at last is T gate time
0Begin to T gate time
0Position between first data variation of interior relatively data f.As a kind of modification, in this example, the cumulative submodule of primary importance is when enable signal v is high level, to the first edge position information x1 operation that adds up; When enable signal v is converted into low level by high level, the result of the cumulative operation of the first edge position information x1 is exported as the first cumulative position; When reset signal y was high level, the cumulative zero clearing as a result that operates resetted to the first edge position information x1.
The very first time obtains submodule and carries out the position to the conversion of time, is about to the first cumulative position and is converted to poor t1 of the very first time.Concrete, if comparing data f is obtained by measured signal a, the frequency according to sampling clock h transforms, i.e. the cumulative position * (frequency of 1/ sampling clock h) of poor t1=first of the very first time; If comparing data f introduces signal p by the outside and obtains, the frequency according to over-sampling clock q transforms, i.e. the cumulative position * (frequency of 1/ over-sampling clock q) of poor t1=first of the very first time.
In originally illustrating, as shown in figure 11, the second time counter 84 specifically can comprise:
Second Edge is along searching module 841, it is according to comparing data f, in a system clock cycle, produce last data variation of an expression comparing data f and the second edge position information x2 of this system clock cycle distance between the finish time, and when comparing data f has data variation, produce simultaneously an override signal L;
The 3rd phase inverter 842, it carries out anti-phase processing to time gate signal j, produces a reset signal y;
The second totalizer 843, it is according to time gate signal j, reset signal y and override signal L, to the second edge position information x2 operation that adds up, and obtains the second mistiming t2 according to the result of cumulative operation.
As a kind of example, in illustrating, Second Edge also is used for one group of the 3rd initialize data of record along searching module 841, and described the 3rd initialize data comprises: dissimilar comparing data and corresponding the second edge position information thereof, whether the sign of data variation is arranged; Second searches module according to comparing data f and system clock i, produces the second edge position information x2 and override signal L from the 3rd initialize data.Described the 3rd initialize data can exist with the form of tables of data.
take a system clock cycle 8bit comparing data as example, as shown in table 3, be one group of the 3rd initialize data that frequently records according to data variation " 01 " (rising edge) meter, first classifies as: the data that the comparing data of last data of previous system clock cycle (last bit) and current system clock period forms, it is from left to right arranged according to the time order and function order, second classifies as and corresponding the second edge position information of dissimilar comparing data, the 3rd classifies the sign whether data variation is arranged as, in this example, there is no data variation with sign " 0 " expression, with sign " 1 " expression, data variation is arranged.As example, table 3 has only provided the wherein part of the 3rd initialize data, and remaining data is omitted herein.
Table 3
In this example, with reference to Figure 11, when opening meter frequency function, Second Edge is along searching module 841 successively in each system clock cycle, according to the comparing data of current system clock period and last Bit data of last system clock cycle, search in the 3rd initialize data, obtain the second edge position information x2 corresponding with it, and input in the second totalizer 843; In addition, by searching in the second initialize data, if at current system under the clock period, when judgement comparing data f has data variation, when producing the second edge position information x2, also can produce an override signal L, the second edge position information x2 and id signal u can input in the second totalizer 843 simultaneously.The second totalizer 843 is according to time gate signal j, reset signal y and override signal L, to the second edge position information x2 operation that adds up, and obtains the second mistiming t2 according to result that should cumulative operation.
As a kind of example, the second totalizer 843 can comprise:
The second place submodule that adds up, it is according to time gate signal j, reset signal y and override signal L, and Second Edge along the positional value x2 operation that adds up, is obtained the second cumulative position;
The second time was obtained submodule, and it is converted to the second mistiming t2 according to one of the frequency of sampling clock h and frequency of over-sampling clock q with the second cumulative position.
In this example, the effect of the cumulative submodule of the second place be exactly by to Second Edge along the second edge position information x2 that the searches module 841 outputs operation that add up, acquisition T gate time
0End and gate time T
0Position between last data variation of interior relatively data f, i.e. the second cumulative position.Wherein, if comparing data f does not have data variation, the cumulative submodule of the second place operation that always adds up; If comparing data f has data variation, the cumulative submodule of the second place also can be according to override signal L, the result of the cumulative operation of heavy duty.As a kind of modification, in this example, the cumulative submodule of the second place (is equivalent to T gate time when time gate signal j is high level
0Time period), to the second edge position information x2 operation that adds up; When getting override signal, the cumulative result that operates of the second edge position information x2 is updated to and produced simultaneously the second edge position information x2 of override signal; When being converted into low level by high level, time gate signal j (is equivalent to T gate time
0The finish time), preserve the result of the cumulative operation of the second edge position information x2, with it as the second cumulative position output; When reset signal was high level, the cumulative zero clearing as a result that operates resetted to the second edge position information x2.
The second time obtained submodule and carries out the position to the conversion of time, was about to the second cumulative position and was converted to the second mistiming t2.Concrete, if comparing data f is obtained by measured signal a, the frequency according to sampling clock h transforms, i.e. the second cumulative position * (frequency of 1/ sampling clock h) of mistiming t2=second; If comparing data f introduces signal p by the outside and obtains, the frequency according to over-sampling clock q transforms, i.e. the second cumulative position * (frequency of 1/ over-sampling clock q) of mistiming t2=second.
Need to prove, in originally illustrating, the dissimilar comparing data that records in described the first initialize data, the second initialize data and the 3rd initialize data is: the data that the comparing data of last data of previous system clock cycle (last bit) and current system clock period forms.This kind recording mode is in order in the comparing data that can accurately judge the current system clock period, whether data variation to be arranged.The example that is judged as with data variation " 01 ", in some cases, such as, the comparing data of current system clock period is 11110000, if the comparing data of previous system clock cycle is 00000000, the comparing data of current system clock period has data variation " 01 ", has a rising edge; If previous cycle data is 11111111, the comparing data of current system clock period does not just have data variation " 01 " so, there is no rising edge.Therefore, judge whether that data variation also needs last data according to previous system clock cycle.
As a kind of example, in originally illustrating, the first phase inverter 822, the second phase inverter 833 and the 3rd phase inverter 842 can share same public phase inverter, thereby have reached the purpose that economizes on resources.
Below, lift a concrete example, the specific embodiment of the present invention is introduced.In this example, measured signal a is carried out frequency counting.Wherein, sampling clock h is 1GHz, and over-sampling clock q is 1GHz, and system clock i is 125MHz, and the also line width of comparing data f is 8.Take the rising edge frequency counting method shown in Fig. 7 (a) as example, in conjunction with Fig. 9, in the clock period, comparing data f is 01100110 at first systematic, and data variation is searched mould 821 by look-up table 1, and can obtain corresponding monocycle data variation number of times is 2; In second system clock cycle, comparing data f is 01100110, search module 821 by data variation, can obtain corresponding monocycle data variation number of times and be similarly 2, by that analogy, the cumulative operation of number of pass times totalizer 823,5 system clock cycles cycle data change frequency that places an order is cumulative, obtain whole gate time of T
0The interior relatively total degree m of the data variation of data f, m=2+2+2+2+2=10.
In conjunction with Figure 10, first side along search module 831 according to first systematic the comparing data 01100110 in the clock period, by look-up table 2, the first edge position information of generation is 1, and produces simultaneously the id signal u that expression has data variation.The first totalizer 834 is according to enable signal v and reset signal y, and to the operation that adds up of the first edge position information, final the first cumulative position that obtains is 1; Further, according to the frequency of sampling clock h, the first cumulative position is converted to poor t1 of the very first time:
t1＝1*(1/1GHz)＝1ns。
In conjunction with Figure 11, Second Edge is along searching module 841 according to the comparing data 01100110 in last system clock cycle, and by look-up table 3, the second edge position information of generation is 3, because this comparing data has data variation, produce simultaneously an override signal L; The second totalizer according to override signal L will before the accumulation result of 4 system clock cycles again be updated to 3, final the first cumulative position that obtains is 3; Further, according to the frequency of sampling clock h, the second cumulative position is converted to the second mistiming t2:
t2＝3*(1/1GHz)＝3ns。
The meter frequency that obtains at last is g as a result
=(the total degree m-1 of data variation)/(gate time T
0Poor t1-the second mistiming t2 of-very first time)
＝(10-1)/(40ns-1ns-3ns)
＝250MHz。
Described meter frequently as a result g be the frequency values of measured signal a, can find out, by the present invention, can obtain very accurately the frequency of measured signal a.
Mainly be introduced in measured signal a frequency counting mode in the specific embodiment of the invention, the frequency counting of outside introducing signal p is cross-reference accordingly.
In the specific embodiment of the invention mainly the frequency counting mode with data variation " 01 " (being rising edge) be introduced, the frequency counting of data variation " 10 " (being negative edge) is cross-reference accordingly.
Above to a kind of digital meter oscillograph of function frequently that has provided by the present invention, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (19)
1. one kind has the digital meter oscillograph of function frequently, comprising:
The data sampling unit is used for according to a sampling clock, digital sample being carried out in measured signal, obtains sampled data;
The numeral comparing unit is used for described sampled data is carried out the level comparison process, produces comparing data;
Trigger control unit is used for producing a Trig control signal according to described comparing data;
The samples storage unit is used for according to described Trig control signal, described sampled data being stored, and produces the waveform that is used for the waveform demonstration and shows data;
It is characterized in that, also comprise:
The frequency counting unit is used for producing the time gate signal with gate time according to a system clock; And according to the second mistiming between last data variation of data relatively in the finish time of poor, described gate time very first time between first data variation of data and described gate time relatively in total degree, the initial time of described gate time and the described gate time of the data variation of data relatively in described gate time, described gate time, the frequency result is counted in generation.
2. oscillograph as claimed in claim 1, is characterized in that,
Described frequency counting unit is made of a programmable logic device (PLD).
3. oscillograph as claimed in claim 1, is characterized in that,
Described data sampling unit is used for respectively digital sample being carried out in the measured signal of a plurality of passages, obtains corresponding multi-channel sampling data;
Described digital comparing unit is used for respectively described multi-channel sampling data being carried out the level comparison process, produce corresponding multichannel comparative result, and select wherein one road comparative result as the comparing data of described data comparing unit output from described multichannel comparative result.
4. oscillograph as claimed in claim 3, is characterized in that, also comprises:
Described data sampling unit also is used for an outside signal of introducing is carried out the signal comparison process, and in response to N the over-sampling clock that phase place is different, the result after described signal comparison process is carried out digital sample, produces the over-sampling result;
Described digital comparing unit also is used for selecting described over-sampling result as described comparing data.
5. oscillograph as described in claim 1 to 4 any one, is characterized in that,
Described frequency counting unit comprises:
Data variation is searched module, is used for obtaining successively the monocycle data variation number of times of described comparing data according to described comparing data and described system clock;
The first phase inverter is used for described time gate signal is carried out anti-phase processing, produces a reset signal;
The number of times totalizer is used for according to described time gate signal and reset signal, to the operation that add up of the monocycle data variation number of times of described comparing data, obtains the total degree of the data variation of described gate time of interior comparison data.
6. oscillograph as claimed in claim 5, is characterized in that,
Described data variation is searched module and also is used for one group of first initialize data of record, and described the first initialize data comprises: dissimilar comparing data and corresponding monocycle data variation number of times thereof;
Described data variation is searched module and is used for obtaining described monocycle data variation number of times according to described comparing data and described system clock from described the first initialize data.
7. oscillograph as claimed in claim 5, is characterized in that,
Described number of times totalizer is when described time gate signal is high level, to the operation that adds up of described monocycle data variation number of times; When described time gate signal is converted into low level by high level, the result of the cumulative operation of described monocycle data variation number of times is exported as the total degree of data variation; When described reset signal was high level, the cumulative zero clearing as a result that operates resetted to described monocycle data variation number of times.
8. oscillograph as described in claim 1 to 4 any one, is characterized in that,
Described frequency counting unit comprises:
First side is along searching module, be used for according to described comparing data, in a system clock cycle, produce the first edge position information of distance between expression first data variation of comparing data and described system clock cycle initial time, and produce simultaneously the id signal whether an expression has data variation;
Pretreatment module is used for carrying out level conversion according to described id signal and described time gate signal and processes, and produces an enable signal;
The second phase inverter is used for described time gate signal is carried out anti-phase processing, produces a reset signal;
The first totalizer is used for according to described enable signal and reset signal, to the operation that add up of described the first edge position information, and poor according to the result described very first time of acquisition that should cumulatively operate.
9. oscillograph as claimed in claim 8, is characterized in that,
Described first side also is used for one group of second initialize data of record along searching module, and described the second initialize data comprises: dissimilar comparing data and corresponding the first edge position information thereof, whether the sign of data variation is arranged;
Described first side is used for according to described comparing data and described system clock along searching module, produces described the first edge position information and described id signal from described the second initialize data.
10. oscillograph as claimed in claim 8, is characterized in that,
Described pretreatment module comprises:
Latch, being used for initial value of output is low level latch signal, and when described id signal has been expressed as data variation for the first time within described gate time, described latch signal is converted to high level output;
Latch phase inverter, be used for described latch signal is carried out anti-phase processing, produce an inversion signal;
The logical and module is used for described time gate signal and inversion signal are carried out the logic and operation operation, produces described enable signal.
11. oscillograph as claimed in claim 8 is characterized in that,
Described the first totalizer comprises:
The primary importance submodule that adds up is used for according to described enable signal and reset signal, to the operation that add up of described the first edge position information, and acquisition first position of adding up;
The very first time is obtained submodule, is used for according to one of the frequency of described sampling clock and frequency of over-sampling clock, the described first cumulative position is converted to the described very first time poor.
12. oscillograph as claimed in claim 9 is characterized in that,
The cumulative submodule of described primary importance is when described enable signal is high level, to the operation that adds up of described the first edge position information; When described enable signal is converted into low level by high level, the result of the cumulative operation of the first edge position information is exported as the first cumulative position; When reset signal was high level, the cumulative zero clearing as a result that operates resetted to the first edge position information.
13. oscillograph as described in claim 1 to 4 any one is characterized in that,
Described frequency counting unit comprises:
Second Edge is along searching module, be used for according to described comparing data, in a system clock cycle, produce last data variation of an expression comparing data and the second edge position information of described system clock cycle distance between the finish time, and when comparing data has data variation, produce simultaneously an override signal;
The 3rd phase inverter is used for described time gate signal is carried out anti-phase processing, produces a reset signal;
The second totalizer for according to described time gate signal, reset signal and override signal, adds up operation and result described the second mistiming of acquisition that operates according to adding up to described the second edge position information.
14. oscillograph as claimed in claim 13 is characterized in that,
Described Second Edge also is used for one group of the 3rd initialize data of record along searching module, and described the 3rd initialize data comprises: dissimilar comparing data and corresponding the second edge position information thereof, whether the sign of data variation is arranged;
Described second searches module is used for according to described comparing data and described system clock, produces described the second edge position information and described override signal from described the 3rd initialize data.
15. oscillograph as claimed in claim 13 is characterized in that,
Described the second totalizer comprises:
The second place submodule that adds up is used for according to described time gate signal, reset signal and override signal, to described Second Edge along the positional value operation that add up, acquisition second position of adding up;
The second time was obtained submodule, was used for according to one of the frequency of described sampling clock and frequency of over-sampling clock, and the described second cumulative position is converted to described the second mistiming.
16. oscillograph as claimed in claim 15 is characterized in that,
The cumulative submodule of the described second place is when time gate signal is high level, to the operation that adds up of described the second edge position information; When getting described override signal, the cumulative result that operates of the second edge position information is updated to and produced simultaneously the second edge position information of described override signal; When described time gate signal is converted into low level by high level, the result of the cumulative operation of the second edge position information is exported as the second cumulative position; When reset signal was high level, the cumulative zero clearing as a result that operates resetted to the second edge position information.
17. oscillograph as claimed in claim 4 is characterized in that,
Described system clock and described sampling clock, over-sampling clock synchronous;
The frequency of described sampling clock is the integral multiple of the frequency of described system clock;
The frequency of described over-sampling clock is the integral multiple of the frequency of described system clock.
18. oscillograph as claimed in claim 1 is characterized in that,
Described frequency counting unit produces described meter frequency result according to the second mistiming between interior last data variation " 10 " that compares data of the finish time of poor, described gate time very first time between first data variation " 10 " of data and described gate time relatively in total degree, the initial time of described gate time and the described gate time of data variation " 10 " in data relatively in described gate time, described gate time.
19. oscillograph as claimed in claim 1 is characterized in that,
Described frequency counting unit produces described meter frequency result according to the second mistiming between interior last data variation " 01 " that compares data of the finish time of poor, described gate time very first time between first data variation " 01 " of data and described gate time relatively in total degree, the initial time of described gate time and the described gate time of data variation " 01 " in data relatively in described gate time, described gate time.
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