JPH0854481A - Time interval measuring apparatus - Google Patents

Abstract

PURPOSE:To measure the time interval with a resolution of less than one several-th of a reference clock by connecting a plurality of unit delay elements in series, setting the entire delay time several times or more as large as the reference clock, providing a latch circuit for every element, and measuring the time interval from the transient position information of the data. CONSTITUTION:A reference clock 71 is so set as to allow the relationships among a period time Tt, the delay time Td of a unit delay element 22n to satisfy Tt=K X Td+DELTAT (K: integer number), and supplies the reference clock. A unit delay detector 20n latches the delay times of n pieces of elements 22a-22n. Accordingly, the entire delay time becomes Tdly=n X Td. An encoder 30 inputs latch signals 24Qa-24Qn from FF 24a-FF 24n, detects the rise and fall transient positions of the signals, converts it into a binary signal, and supplies it to a data recorder 40. An arithmetic processing part 44 determines Tdly>Tt X (Td/DELTAT)=TtX Q (Q: resolution magnification) from the data, and measures the time interval with the DELTAT as the measuring resolution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field in which a highly accurate pulse signal is required, and for measuring the pulse width of the pulse signal,
Pulse generation period measurement, time interval measurement between two pulses,
It relates to an apparatus for measuring these average values with high resolution.

[0002]

2. Description of the Related Art As an example of the prior art, there is a case of measuring various time intervals of a pulse signal using a high frequency reference clock. This will be described with reference to FIGS. 5 and 6. As shown in FIG. 5, the configuration of this circuit has a reference clock 70

The reference clock 70 is a high-frequency clock that can be realized by a circuit, determines the resolution of each time measurement, and uses, for example, a 1 GHz clock. In this case, the reference time has a minimum resolution of 1 ns. This reference clock is supplied to the gate controller 50 and the counter 60.

The counting section 60 is a counter that counts the number of clocks of the reference clock 70 while the enable signal 64 is being input, and is, for example, a 24-bit length counter and is composed of a high-speed ECL device or the like. The counting unit 60 receives the RST signal 66 and initializes and clears the count value. The counting unit 60 receives the enable signal 64 input and starts / stops counting. The data 62 of the counting result is read from the outside if desired.

The gate controller 50 receives the measurement condition selection signal 59 from the outside and measures the measured input pulse signals 51, 54 and 55 in various measurement modes. That is, the measurement condition selection signal 59 is used to measure the pulse width of the pulse signal,
Measurement of pulse generation period, measurement of time interval between two pulses,
Switching to the measurement mode of measuring the average pulse width of the repetitive input pulse signal, measuring the average pulse generation period, and measuring the average time interval between two pulses. In the case of the first pulse width measurement, the high level (or low level) of the input signal 51
To measure the time. As in the example of the input signal 51b shown in FIG. 6, the counting unit 60 outputs the enable signal 64 at the high level during the period when the input signal is in the high level. The pulses 61 in this period are counted. These operations are operated in synchronization with the reference clock 70. In the case of the second pulse generation period measurement, the time of two rising (or falling) of the input signal 51 is measured. As in the example of the input signal 51a shown in FIG. 6, the enable signal 64 output is set to a high level at the first rising edge of the input signal, and the enable signal 64 output is cleared at the first rising edge of the next input signal. The pulse generation cycle is measured by counting the high level period of the enable signal 64. In the case of measuring the time interval between the third two pulses, the pulse interval between the two input signals is measured. As in the example of the input signals 54a and 55a shown in FIG. 6, the enable signal 64 output is set to a high level at the rising (or falling) edge of one input signal 54a and enabled at the rising edge of the other input signal 55a. Clear the signal 64 output. The high level period of the enable signal 64 is counted. In the case of the average pulse width measurement of the fourth repetitive input pulse signal, it is a measurement mode in which the first measurement is continuously performed N times. In this case, a down counter 48 for counting the number of repetitions is provided in the gate control unit 50, and an N value is preset in this down counter 48 as an initial state before starting the measurement. Since the output of the enable signal 64 repeatedly repeats the high / low state during the measurement, the count is counted by the down counter 48, and the measurement is terminated when zero is detected. As a result, the count value of the counting unit 60 is N times the count value,
From this, the average value of the pulse width of the input pulse signal can be obtained. In the case of the fifth average pulse generation period measurement,
This is a measurement mode in which the second measurement is continuously performed N times, and the measurement is performed in the same manner as in the fourth case. In the case of the average time interval measurement between the sixth two pulses, the third measurement is
This is a measurement mode in which measurement is performed continuously, and the measurement is performed in the same manner as in the fourth case.

[0006]

Since the configuration is as described above, there is a drawback that the time below the resolution of the reference clock 70 cannot be measured. Further, if the frequency of the reference clock 70 is increased to increase the resolution, it is necessary to use a device having an ultrahigh speed. Further, there is a limitation on the mounting distance between circuit components, and due to the propagation delay of the wiring pattern, there is a limit to operating the ultra-high frequency clocks in synchronization, which is practically difficult.

Therefore, an object of the present invention is to realize a time interval measuring device capable of measuring a time interval having a resolution of 70 hours or less of a reference clock.

[0008]

In order to solve the above-mentioned problems, the first solution is to provide a reference clock 71 source capable of arbitrarily varying the cycle time Tt, and to provide an input signal 5 to be measured 5.
The input shaping control unit 10 which receives 1, 54, 55 and outputs the level signal 56 from the start to the stop of the measured time interval is provided, and a plurality of unit delays composed of the unit delay element 22 and the flip-flop 24 are provided. Detectors 20a-20
n are connected in series, and a plurality of unit delay detectors 20a to 20n for detecting and latching the level signal at the output terminal of the unit delay element 22 through which the level signal 56 passes are provided, and the unit delay detectors 20a to 20n are provided. Latch signal from 24Qa
An encoder unit 30 that encodes and outputs a transition position of data from permuted data of ˜24Qn is provided, a clock time counting unit 42 that counts the number of times of a reference clock Tclk unit is provided, and the arrangement of the encoded data 33a and 37a is arranged. Calculate the time less than the cycle time Tt from the data,
The arithmetic processing unit 44 for adding the data from the clock time counting unit 42 and outputting the entire time interval is provided. In this case, the means for receiving the period from the start to the stop of the measured time interval and measuring with the level signal of the period Tmeas from the start to the stop is used.

Further, as a constitution of the second solving means, a reference clock 71 source capable of arbitrarily varying the cycle time Tt is provided, and when the measured input signals 51, 54 and 55 are received, the start pulse Pstt and the stop pulse Pstt are received. The input shaping control unit 10 for generating Pstp is provided, and the unit delay element 22 and the flip
A plurality of unit delay detection units 20a configured with the flop 24
.About.20n are connected in series, and a plurality of unit delay detectors 20a to 20n for detecting and latching the level signal at the output terminal of the unit delay element 22 through which the start pulse Pstt or the stop pulse Pstp passes are provided to detect the unit delay. Part 2
An encoder unit 30 that encodes and outputs a transition position of data out of the permutation data of the latch signals 24Qa to 24Qn from 0a to 20n is provided, and a clock time counting unit 42 that counts the number of hours of a reference clock Tclk unit is provided. From the data of the arrangement of the encoded data 33a and 37a, the time less than the cycle time Tt is calculated, the data from the clock time counting unit 42 is added, and the arithmetic processing unit 44 for outputting the entire time interval is provided. . In this case, a means for measuring the time interval from the start to the stop of the measured time interval by two pulses of a start pulse / stop pulse is used.

In addition to the above configuration means, a reference clock T
In synchronization with clk, the encoder unit 30 stores the encoded data 33a and 37a, and the clock time counting unit 42
Data recording unit 4 for storing count value Tcount data from
There is a configuration means for providing 0. In this case, the arithmetic processing unit 44 may be a unit that reads out the stored data and performs an arithmetic operation after the measurement of the time interval is completed.

Further, the encoder unit 30 includes a first transition encoder unit 31 and a second transition encoder unit 35.
Unit delay detectors 20a-20 having a pair of encoders
There is a configuration means for providing an encoder unit 30 that simultaneously detects, encodes and outputs two transition positions from the permutation data of the latch signals 24Qa to 24Qn from n.
In this case, the encoder unit 30 can realize a means for detecting both rising and falling edge positions at the same time.

[0012]

The reference clock 71, whose cycle time Tt can be changed arbitrarily, acts to set the resolution of ΔT time by setting so that the relationship of Tt = k × Td + ΔT is established.
The unit delay detection units 20a to 20n and the encoder unit 30 are
It has a function of detecting a fractional time less than the reference clock Tclk as a plurality of permutation data. The encoder unit 30 also has an effect of reducing the data length to the data recording unit 40 by converting a multi-bit input signal into a binary signal. The data recording unit 40 uses the reference clock Tclk.
In synchronization with the above, there is an action of storing the continuous encoded data 33a / 37a from the encoder unit 30. Also,
It has a function of storing the count value Tcount data from the clock time counting unit 42. The clock time counting unit 42 has a function of counting a number of times in units of the reference clock Tclk so that a long time interval can be measured.

For the time Tstt / Tstp which is less than the reference clock, the arithmetic processing unit 44 receives the data of the arrangement of the encoded data 33a / 37a, and Tx = the first encoded value DL
It has a function of obtaining as Y0 + (position of data change point Dpos-1) / resolution magnification Q. Further, from now on, as shown in FIG. 4, from the measured values divided into three sections, Tto
The total time interval is obtained by calculating tal = Tstt + (Tt−Tstp) + Tcount × Tt. Encoder part 3
When two independent circuits of the first transition encoder unit 31 and the second transition encoder unit 35 are provided at 0, it is possible to measure a time interval shorter than the total delay time Tdly. That is, there is an effect of detecting both rising and falling edge positions at the same time. With this configuration, it is possible to obtain the function of measuring the time interval of the signal under measurement at a high resolution time interval of ΔT time smaller than the cycle time Tt of the reference clock 71. Further, a time interval measuring function from the time interval measurement of the minimum ΔT time to the arbitrary time interval exceeding the total delay time Tdly can be obtained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiment of the present invention, a large number of unit delay elements are connected in series to provide a total delay time of N times or more of a reference clock, and a latch circuit is provided for each unit delay element. Is a case where the time interval is measured with a resolution of 1 / N of the reference clock. About this,
Will be described with reference to FIG. As shown in FIG. 1, the configuration includes a reference clock (Tclk) 71 and an input shaping controller 1.
0, M unit delay detection units 20a to 20n, an encoder unit 30, a clock time counting unit 42, a data recording unit 40, and an arithmetic processing unit 44.

The reference clock 71 is a reference clock source capable of arbitrarily changing the cycle time Tt, and generates a desired cycle time Tt according to a cycle time setting parameter from the outside. This is an oscillation source by a synthesizer, for example.
The cycle time Tt of the reference clock and the unit delay element 22
The relationship with the delay time of n will be described later with Tt = k × Td + ΔT
This is to allow setting so that the relationship of is established.

The unit delay detectors 20a to 20n are composed of minute unit delay elements 22a to 22n using gates and D-type FFs (flip-flops) 24a to 24n. Since the unit delay elements 22a to 22n are minute delay elements for obtaining the minimum delay time, a high speed buffer gate or the like having a propagation delay as small as possible is used. When this delay element is formed in the gate array, a buffer / OR / AND gate cell with a small propagation delay is used. The reference clock 7 is provided at the clock ends of the D-type FFs 24a to 24n.
1 is being supplied. The output states of the D-type FFs 24a to 24n are in the initialization clear state by the reset signal 58 before the start of measurement. Then, it receives the high-level signal at the output end of the unit delay element 22n, latches it at the reference clock, and outputs it. The latch signals 24Qa to 24Qn are supplied to the encoder unit 30. This unit delay detector 20
n is for latching the unit time information of the unit delay time Td, and the unit delay detector 20a at the first stage receives the signal under measurement 56 from the input shaping controller 10 and receives the unit delay time of the unit delay element 22a. After passing Td, D-type FF24
It is supplied to the data input terminal of a and the unit delay element 22b of the next stage. Since the unit delay elements 22a to 22n are connected in series, the total delay time is Tdly = M × Td. Here, each unit delay element 22a-2
The delay times of 2n are assumed to be substantially the same unit delay time Td.

The encoder section 30, as shown in FIG.
First transition encoder unit 31 and second transition encoder unit 3
5 has two sets of encoders, and the first transition encoder unit 31 detects the rising position from the permutation data of the input latch signals 24Qa to 24Qn, encodes it, and outputs it. The encoder unit 35 is
The falling position is detected from the permutation data of the input latch signals 24Qa to 24Qn, encoded, and output. When there is no position detection signal, a 0 value is output. The first transition encoder unit 31 includes a first encoder 32.
And the first FF 33. First encoder 3
2 receives the permutation data of the latch signals 24Qa to 24Qn from the unit delay detectors 20a to 20n, detects the rising transition position from the permutation data, encodes and converts this position information into binary data, and then FF33.
Supply to. The FF 33 latches this binary signal in synchronization with the reference clock 71 and encodes the encoded data 33.
a is supplied to the data recording unit 40. For example, when the number of unit delay detectors is M = 255, the number of outputs is converted into an 8-bit binary signal. The second transition encoder unit 35 includes a second encoder 36 and a second FF 37. In the same manner as described above, the second encoder 36
Detects the falling transition position from the permutation data,
This position information is encoded and converted into binary data and then supplied to the FF 37. The FF 37 supplies the encoded data 37 a obtained by latching this binary signal in synchronization with the reference clock 71 to the data recording unit 40. In this way, by providing the two circuits of the first transition encoder unit 31 and the second transition encoder unit 35 independent from each other,
It is also possible to measure a time interval shorter than the total delay time Tdly. That is, it becomes possible by detecting both the rising and falling edge positions at the same time and supplying them to the data recording section 40.

As shown in FIG. 1, the input shaping control section 10 selectively receives the measured input pulse signals 51, 54, 55 according to the measurement mode of the measurement condition selection signal 59,
Period Tme from start to stop of the measured time interval
The measured level signal 56 is supplied to the delay element 22a as a high level signal of as. The generation of the start / stop is performed corresponding to the measurement mode, that is, the pulse width measurement, the pulse generation period measurement, and the time interval measurement between two pulses, as in the conventional description.

The clock time counting section 42 receives the count enable signal 25a from the input shaping control section 10, and
In the start / stop period, as shown in FIG. 4, the counter measures only a time section Tcount × Tt that is an integral multiple of the reference clock unit. The input shaping controller 10 is provided with an enable FF 25 for this purpose. The enable FF 25 is a count enable signal 25 shown in FIG.
Like a, it is set in synchronization with the reference clock at the start timing and then immediately cleared at the stop timing. This count value Tcount is supplied to and recorded in the data recording unit 40.

The data recording unit 40 receives the encoded data 33a from the encoder unit 30, the encoded data 37a, and the data of the count value Tcount from the clock time counting unit 42 described above, and synchronizes with the reference clock Tclk. Write and save.

After the measurement of the time interval is completed, the arithmetic processing unit 44 reads the data stored in the data recording unit 40 and calculates the total time interval Ttotal. In the sequence of the encoded data 33a and 37a, the time Tstt / Tstp, which will be described later, is less than the reference clock, and Tx = the initial encoded value DLY0 + (the position of the data change point Dpos-1).
/ Resolution magnification Q. From this, as shown in FIG. 4, Ttotal = Tstt + (Tt−Tstp) + Tcoun
Calculated by calculating t × Tt. As described above, the time interval measuring means is realized by means of dividing the measurement into three intervals and measuring and then adding them. The measurement of the first section Tstt measures the time difference between the start signal and the reference clock Tclk, the measurement of the second section Tcount measures the number of hours that is an integral multiple of the reference clock time, and the measurement of the third section Tend. The measurement measures the time difference Tstp between the stop signal and the reference clock Tclk,
It is calculated later by Tend = Tclk-Tstp.

The principle of time interval measurement by the unit delay detectors 20a to 20n will be described below with reference to FIG. It is assumed that the cycle time Tt is set in advance so that the relationship between the cycle time Tt of the reference clock and the unit delay element 22n is Tt = k × Td + ΔT. The total delay time Tdly of all unit delay elements 22n is set to Tdly> Tt * (Td / [Delta] T) = Tt * Q. Here, (Td / ΔT) is the resolution magnification Q.
Thereby, the measurement resolution can be measured as ΔT. Here, k is an integer value. Here, a numerical example is given to facilitate the following description. Tt = 10 ns, Td =
When 1.0 ns, k = 10, and resolution magnification Q = 10, Tdly> Tt × (Td / ΔT) = 100 ns
To provide. This gives a resolution ΔT = 0.1 ns.

This total delay time Tdly is 10 times the cycle time Tt.
An example in which the measurement resolution can be obtained at ΔT = 0.1 ns by providing the double times will be described below. As a first example of the interval between the signal under measurement Tstt and the reference clock, FIG.
A case where the measured time interval Tx from the reference clock position is at a position of 5.9 ns, as indicated by the encoded value 110 in FIG. In this case, there is an integer multiple of 5 of the unit delay time Td and a fractional time of 0.9 ns. The encoded data 33a is stored in the data recording unit 40 as an array of encoded data 33a for each reference clock Tclk. When the encoded values from the first reference clock to the tenth encoded value are sequentially described, as shown by the encoded value 110 in FIG. 3, 5, 16, 26, 36, 46, 56, 66, 76,
The data are stored in the data recording unit 40 in the order of 86 and 96.
Here, the first encoded value 5 is DLY0. In the case of this encoded value, the original value of the second value is 15 and the original value is 16. This is the data change point Dpos. This is because the unit delay element 22n has a fractional time of 0.
Since it has 9 ns, if one ΔT time is added to this, it becomes 0.9 ns + ΔT × 1 = 1 ns, which is the unit delay time Td. Therefore, the unit delay value of +1 step ahead is 15 + 1 = 16. Has been detected as. From this, it is easily obtained that the fractional time is 0.9 ns.

Next, as a second example of the interval between the measured signal Tstt and the reference clock, the measured time interval T from the reference clock position as shown by the encoded value 120 in FIG.
The case where x is located at 5.7 ns will be described. In this case, an integer multiple of 5 of the unit delay time Td and a fractional time 0.7n
when there is s. In this case as well, if the encoded values are similarly described in order, 5, 15, 25, 36, 46, 56, 6
6,76,86,96. In the case of this encoded value, the original value of the fourth value is 35, but the original value is 36. This is the data change point Dpos. This is because the unit delay element 22n has a fractional time of 0.7 ns.
ns + ΔT × 3 = 1 ns, which is the unit delay time T
Since it is d, it is detected as a unit delay value of +1 step ahead 35 + 1 = 36. From now on, the fractional time is 0.7n
It is easily required to be s.

As described in the above two examples, in this numerical example, the data stored in the data recording section 40 is read by providing the total delay time Tdly which is 10 times or more the reference clock cycle time Tt. From the position of the data change point Dpos, it can be seen that the measurement result can be obtained with the resolution of ΔT = 0.1 ns. From now on, the measured signal T
The time Tx between stt and the reference clock is calculated as Tx = initial encode value DLY0 + (position of data change point Dpos-1) / resolution magnification Q. Thus, the resolution ΔT
By setting the time to a desired time value that is smaller than the cycle time Tt that is the reference clock 71, it is possible to easily perform high-resolution time interval measurement.

In the above description of the embodiment, the measured level signal 56 is described as a high level signal in the period Tmeas from the start to the stop of the measured time interval, but instead of this high level signal, the start / start signal is used. In response to the stop signal, two pulses of a start pulse / stop pulse having a unit pulse width are generated, and the pulses of these two are supplied to the delay element 22a of the unit delay detection unit 20a, and the passage position of these two is detected. Then, the encoded data is recorded in the data recording section 40.
It may be stored in the same manner, and can be carried out in the same manner.

In the above description of the embodiment, the encoder section 30 is provided with the two-transition circuits of the first transition encoder section 31 and the second transition encoder section 35. However, the total delay time Tdly In the case of only the measurement of a long time interval exceeding 0, it is possible to apply the configuration means provided with one transition encoder part and to detect both the rising edge and the falling edge, and it is possible to carry out in the same manner.

In the above description of the embodiment, the data recording section 40 is provided, and once stored in this memory, it is read out and the arithmetic processing section 44 calculates and calculates the total time interval Ttotal. However, this data recording unit 40
Is deleted, and the entire time interval Tto is directly calculated by the arithmetic processing unit 44.
It may be a constituent means for calculating and realizing tal, and can be implemented in the same manner.

[0029]

Since the present invention is configured as described above, it has the following effects. With this configuration, the time interval of the signal under measurement is set to the reference clock 7
It is possible to obtain the effect that measurement can be performed at time intervals of resolution ΔT time smaller than the cycle time Tt of 1. Further, there is an effect that the time interval from the time interval measurement of the minimum ΔT time to the arbitrary time interval exceeding the total delay time Tdly can be measured. Reference clock 71 whose cycle time Tt can be changed arbitrarily
Has an effect of setting so that the relationship of Tt = k × Td + ΔT is established. The unit delay detection units 20a to 20n and the encoder unit 30 have an effect of detecting a fractional time less than the reference clock Tclk as a plurality of permutation data.
The data recording unit 40 includes the data of the count value Tcount from the clock time counting unit 42 and the encoder unit 3 described above.
There is an effect that the encoded data 33a / 37a from 0 is received, and the encoded data 33a / 37a is synchronized with the reference clock Tclk and continuously stored. The clock time counting unit 42 has the effect of measuring a long time interval by counting the number of times in units of the reference clock Tclk. The arithmetic processing unit 44 calculates Ttotal = Tstt + (Tt-Tstp) from the measured values divided into three sections.
The time interval of the signal under measurement can be obtained by adding the total time interval Ttotal by calculating + Tcount × Tt.

[0030]

[Brief description of drawings]

FIG. 1 is an example of a configuration block diagram of time interval measurement according to the present invention.

FIG. 2 is an example of a configuration block diagram when the encoder unit 30 according to the present invention has two systems of a first / second transition encoder unit.

FIG. 3 is a timing diagram illustrating the principle of time interval measurement by the unit delay detection units 20a to 20n according to the present invention.

FIG. 4 is a timing diagram illustrating the measurement of time intervals in three divisions of the present invention.

FIG. 5 is a configuration diagram of a conventional time interval measurement.

FIG. 6 is a timing diagram illustrating conventional time interval measurement in various measurement modes.

[Explanation of symbols]

 10 Input shaping control section 20a, 20n Unit delay detection section 22, 22n, 22b Unit delay element 22a Delay element 24, 24a Flip flop 24Qa, 24Qn Latch signal 24a, 24n D type FF 25a Count enable signal 25 Enable FF 30 Encoder section 31 1st transition encoder part 32 1st encoder 33a, 37a Encoded data 33, 37 FF 35 2nd transition encoder part 36 2nd encoder 40 Data recording part 42 Clock time counting part 44 Arithmetic processing part 48 Down counter 50 Gate control part 51 , 54, 55 input pulse signal to be measured 51b, 51a, 54a, 55a, 56 input signal 58 reset signal 59 measurement condition selection signal 60 counting section 61 pulse 62 data 64 enable signal 66 RST signal 0,71 reference clock (Tclk) 110, 120 encoded value Tt cycle time Pstt start pulse Pstp stop pulse Pref origin pulse Ttotal entire time interval Tcount count Tstt, Tstp, Tend interval Tmeas period ΔT resolution

Claims (4)

[Claims] 1. A cycle time (T) of a reference clock (71).
With a resolution smaller than t), the input signal under measurement (51, 5,
In the measurement of the time interval of (4, 55), the reference clock (7
1) Provide a source and receive the input signal (51, 54, 55) to be measured, and receive the level signal (5
An input shaping control unit (10) for outputting 6) is provided, and a plurality of unit delay detection units (20a to 20n) each including a unit delay element (22) and a flip-flop (24) are connected in series, A plurality of unit delay detection units (20a to 20n) for detecting and latching the level signal at the output end of the unit delay element (22) through which the level signal (56) passes, and unit delay detection units (20a to 20n) are provided. From the permutation data of the latch signals (24Qa to 24Qn) from the encoder section (3
0) is provided, and a clock time counting unit (42) that counts the number of times in units of a reference clock (Tclk) is provided, and a time less than the cycle time (Tt) is calculated from the data of the array of encoded data (33a, 37a). An arithmetic processing unit (44) for adding the data from the clock time counting unit (42) and outputting the total time interval is provided, and the time interval measuring device is provided with the above. 2. A cycle time (T) of the reference clock (71).
With a resolution smaller than t), the input signal under measurement (51, 5,
In the measurement of the time interval of (4, 55), the reference clock (7
1) A source is provided, an input shaping control unit (10) that receives a measured input signal (51, 54, 55) and generates a start pulse (Pstt) and a stop pulse (Pstp) is provided, and a unit delay element ( 22) and a plurality of unit delay detectors (20a to 20n) composed of a flip-flop (24) are connected in series, and a unit delay element (22) through which a start pulse (Pstt) or a stop pulse (Pstp) passes.
In the permutation data of the latch signals (24Qa to 24Qn) from the unit delay detection units (20a to 20n), a plurality of unit delay detection units (20a to 20n) for detecting and latching the level signal at the output terminal of From the encoder part (3 that encodes and outputs the transition position of the data from
0) is provided, and a clock time counting unit (42) that counts the number of times in units of a reference clock (Tclk) is provided, and a time less than the cycle time (Tt) is calculated from the data of the array of encoded data (33a, 37a). An arithmetic processing unit (44) for adding the data from the clock time counting unit (42) and outputting the total time interval is provided, and the time interval measuring device is provided with the above. 3. The encoder unit (3) in addition to the constituent means according to claim 1 or 2, in synchronization with a reference clock (Tclk).
0) from the encoded data (33a, 37a) and the count value (Tcoun from the clock time counter (42).
t) A time interval measuring device comprising a data recording unit (40) for storing data and comprising the above. 4. The encoder unit (30) according to claim 1 or 2, comprising two sets of encoders, a first transition encoder unit (31) and a second transition encoder unit (35), Latch signals (24Qa to 2Q) from the delay detection units (20a to 20n)
4Qn) permutation data, two transition positions are simultaneously detected, encoded, and output by an encoder unit (3
0) is provided and the above is provided, The time interval measuring device characterized by the above-mentioned.