JPS60201279A - Time interval measuring device - Google Patents

Abstract

PURPOSE:To reduce + or -1 counting errors of a basic clock and obtain high resolution at a lower clock frequency than conventional one by delaying the basic clock by the value of necessary resolution successively, and detecting counting errors of a signal to be measured. CONSTITUTION:A delay line 2 generates 10-phase clocks 103-1-103-10 which are delayed by the resolution value TR successively and the signal 101 to be measured is inputted in this state to store the 10-phase clocks in a register 4 at the leading edge of the signal. A counter 3 counts the high-level time of the signal 101 with the basis clock 102. When the signal 101 is ceased, a register 5 stores the 10-phase clocks 103-1-103-10 at the leading edge. A microprocessor 6 recognizes the completion of measurement at the trailing edge of the signal 101 and performs arithmetic on the basis of outputs of the register 4, counter 3, and register 5 to calculate the high-level time of the signal 101.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a time interval measuring device.

In particular, the present invention relates to a time interval measuring device that obtains a resolution higher than a clock frequency.

(Prior Art) Conventionally, time intervals have been measured by counting the clock pulses of the clock frequency that exist within the time of the signal under test. This method has an error of ±1 count value, and in order to reduce the error value, the resolution must be increased. Since resolution is proportional to clock frequency, the clock frequency must be increased to obtain high resolution. However, it is not easy to stably obtain a high clock frequency. This is because component circuit components that operate with a high frequency clock must operate at a frequency higher than the clock frequency, and the clock frequency t
- This is because all the component circuitry that generates the clock frequency must be stable in order to provide a constant supply. This meant the use of very specialized circuit components and circuit and measurement techniques, which had the disadvantage of resulting in complex and expensive measurement equipment.

(Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks by using a multi-phase a.c. An object of the present invention is to provide a time interval measuring device that can obtain the desired time intervals.

(Structure of the Invention) According to the present invention, there is provided a basic clock generating section that generates a clock of a certain frequency, a counting section that counts a signal under test at a clock frequency from the basic clock generating section, and an integer multiple of the clock frequency. a multiphase clock generating section that generates a multiphase clock; first and second storage sections that store the start time and end time of the signal under test, respectively, in the order of the multiphase clock; A time interval measuring device is obtained, which is characterized by comprising a calculation section that calculates a time interval of a signal.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the time interval measuring device of the present invention, and FIG. 2 is a time chart showing an example of each signal in FIG. The figure shows a 10-phase clock frequency in which the period of the clock frequency is divided into 10 equal parts in order to obtain a resolution of 10 times the clock frequency, that is, from one multi-phase clock frequency to the next multi-phase clock frequency. A block diagram and a time chart are shown in the case of using a lO-phase 072 frequency in which the delay (resolution value) is 1/10 of the period of the clock frequency.

Next, the operation of this embodiment will be explained. A basic clock 102 output from the oscillation circuit 1 is input to the delay line 2. The delay 2-in-2 is a 10-phase Kurozuku 103-1. 103-2
．． ~103-10 is generated. When the signal under test 101 is input in this state, the register 4
is a 10-phase clock 103-1.103-2. ~103
-10 (in Figure 2, the 10-phase clock 10
3-1, it is stored as 1100000111'' in positive logic).

The counter 3 basically counts the high level time of the 1111J constant signal 101 using the a clock 102 (2 counts in FIG. 2). At the end of the signal under test 101, the falling edge is 9, and the register 5 receives the 10-phase clock 1.
03-1.103-2. ~103-10 is recorded (in FIG. 2, it is stored as 0111110000 with positive logic from the 1O phase converting clock 103-1). Recognize the end.

The output 105 of the register 4 which is the state 1 of the 10-phase clock that stores the start time, the output 104 of the counter 3 that is the count value based on the basic clock 102, and the 10-phase clock that stores the end time. The state value of the register 50 output 106 is input, and calculation is performed according to the following equation (1) to calculate the high level time of the signal under test 101.

Ty=n・1/fc+(Kp KT)'TR−-[1)
Here, TM: Time interval measurement value of the signal under test, n: Count value by the basic clock 102.

fc...Clock frequency TR...HjLh of the required resolution KT...1o that remembers the start time
Phase 1 rank determined by the status value of phase black dwarf.

K, . . . is the 1o phase conversion order determined by the state value of the 1o phase conversion clock that stores the end time.

Further, the 10-phase conversion order KT and KT are determined as follows. A 10-phase clock 103-1, 103-2. ．． 103-10, each status value a1. a2. Assuming that ~alo is written, these are arranged in order starting from the state value a1 and the state (ia =
(axt a2+ ~alG).

Adding the state value a11="0" to it, the total state value a'
”(a1+a2.~alO, axt), the state value al (however, Th' ~1.2.~10.11
) has either 1" or 0" in positive logic, so if the state [a] is shifted from 1 to the left and output, the output changes from "1" to "0°". value al
exists. Since the number of shifts at this time is 1, i-1 becomes the 10-phase conversion order. From the definition of 10-phase Kurozuku in CC, the state value a / = (o.

It is clear that C does not become O1~0,0).

Generally, when the number of polyphases is ft and m, the state value is a''
It is expressed as (al, a2.~am, 8m+1) and is shifted to obtain the polyphase rank i-1 (however, 1≦i
≦ill +l, 'B, n+t="0").

Now, when calculating the high level time of the signal under test 101 shown in FIG. 2, the counter 3. The count is directly calculated from the output 104 of n=2. The state value of the start time of the register 40 output 105 is "1100000111", so it is in the 10-phase order! = 2% Since the end time state value of register 50 output 106 is “0111110000”, 10-phase conversion order KP =
6, and the above formula (1) is 1"M = 2 ・1/fc+
(6-2) s'l'F, = 2 ・1/fc+4・T
R and Naru.

In the first embodiment, the time measurement of the signal under test 1010 is set to high level, but the register 5 is used as a storage circuit for the state value of the 10-phase clock for the start time, and the register 4 is used as a storage circuit for the state value of the 10-phase clock for the end time. Similarly, time can be measured on the low level side as well. 19 According to the first embodiment, the signal under test 10
Time intervals can be measured with a pulse width of 1.

Next, FIG. 3 is a partial block diagram showing a second embodiment of the time interval measuring device of the present invention, and FIG. 4 is a time chart showing an example of each signal in FIG. 3. The second embodiment is constructed by adding a flip-flop 7 to the front stage of the signal under test 101 in the first embodiment (shown in FIG. 1).

In the second embodiment, the starting signal 1 for the signal under test 101 is
Both signals 107 and 108 using 07 and end signal 108.
The time difference between the gold can be measured.

Above 1st. In the second embodiment, the number of multiphase clocks is shown as 10 phases, but the number of multiphase clocks is not limited to this, and the number of multiphase clocks can be changed arbitrarily depending on the required resolution and basic clock frequency. It goes without saying that you may decide to do so.

(Effects of the Invention) As explained above, the time interval measuring device of the present invention measures ±1 count of the basic clock by sequentially delaying the basic clock by as much as the required resolution and detecting the counting error of the signal under test. Since the error t is substantially small and high resolution can be obtained with a clock frequency lower than that of the conventional method, there is an effect that the configuration of the measuring device is simplified and the measurement device is inexpensive.

[Brief explanation of the drawing]

FIGS. 1 and 3 respectively show the first time interval measuring device of the present invention. Brine showing the second example, 3...
...Counter, 4.5...Register. 6...Microprocessor, 7...Flip 70 knob, 101...Measurement signal % 1
02...Basic 107...Start signal,
108...End signal. Early 3rd peak 2'd-4m

Claims (1)

[Claims] A basic clock generating section that generates a clock of a certain frequency, a counting section that counts the signal under measurement at the clock frequency from the basic clock generating section, and a multiphase clock generating section that is an integral multiple of the clock frequency. a multiphase clock generating section that generates a multiphase clock, and first and second clocks that record the start time and end time of the signal under test, respectively, in the order of the multiphase clock.
A time interval measuring device comprising: a zero-column section; and a calculation section that calculates the time interval of the measurement target No. 18.