JPS6295487A - Time width measuring instrument - Google Patents

Abstract

PURPOSE:To measure time width fast on a real-time basis by converting the output of a phase detector directly from analog to digital and then performing arithmetic by a microcomputer, etc. CONSTITUTION:The output of the phase detector 23 is converted fast by an AD converter 26 into a digital signal, which is processed by the microprocessor 11. A flip-flop 27 is set and reset with a signal s8 applied to a terminal p5. The quantity delta1 of phase shifting is the output value of the phase detector 23 and converted by the AD converter 26 fast into the digital signal, which is sent as a signal s9 to the microprocessor 11. The microprocessor 11 performs arithmetic to calculate the 1st and the 2nd fraction times DELTAT1 and DELTAT2 because the pulse width tau0 of a strobe signal and the period T0 of a clock signal are already known and the value delta1 is found from the signal s9.

Description

[Detailed description of the invention] B. “Purpose of the invention” [Industrial application field] The present invention relates to a time width measuring device.

More specifically, the present invention relates to a time width measuring device that can accurately measure even so-called fractional time that is less than the period of the reference clock signal.

(Prior Art) Universal counters are widely used as devices for measuring the frequency, period, etc. of a signal.

In addition to such counters, devices such as LSI testers, for example, use devices that measure the time width from a point in time to a point in time when a signal to be measured is formed.

BACKGROUND OF THE INVENTION With the development of the telecommunications field, the frequencies of signals handled have increased in recent years, and it has become necessary to measure the time width of signals with high precision (high resolution).

Generally, the following principle is used to measure time width with high accuracy. A clock signal with a period To is passed through the gates 1 to 1 which are open in the measured time width Tx, and the number N of the clocks passing through is counted. And NTo
is the time width. Although this method improves resolution as the clock frequency increases, there is actually a limit to the speed of the circuit elements. That is, this means cannot measure with a resolution higher than the clock cycle.

In the above method, in m-density, Tx=NT.

TX=8NTo. This is usually T
This is because x is not divisible by TO and there are small fractional times. This is shown in FIG. In Figure 4, ΔT1
is the fractional time from the rising edge of Tx to the clock CO generated immediately thereafter, and ΔT2 is the fractional time from the falling edge of TX to the clock Cn generated immediately thereafter. Then, the gate is opened for a period between clock signals C0 and Cn (see (d) in FIG. 4), and the number of clocks passing through is counted. If the number of clocks in that period is N, then [(e) in Figure 4] time width T
x is expressed by equation (1).

Tx=NTo + ΔT+ −ΔT 2
(1) Therefore, the fractional time Δ
By measuring T+ and ΔT2, it is possible to measure the time width Tx with a resolution of 10 or more clock cycles (1)
It can be seen from the formula.

There is a time VerniQr method as a known means that can measure this fractional time. This time vernier method is an application of the caliper principle to the time axis, and will be explained using FIG. 5. In this method, in addition to the main clock with period To, the period To = (To −
>To ) vernier clock is required. By counting the number of clocks N until the phases of both clocks match, ΔT can be found as ΔT=N (To −To). The resolution is the period difference between both clocks (To ′
To).

(Problems to be Solved by the Invention) However, with the above means, as shown in FIG. 5, it takes time for the main clock and the vernier clock to match.
There is a problem that high-speed repeated measurements and real-time measurements cannot be performed.

The purpose of the present invention is to provide a time width measuring device that can perform high-speed repetitive measurements, real-time measurements, and high-resolution measurements. i!
It is to provide.

``Structure of the Invention'' (Means for Solving the Problems) In order to solve the above problems, the eleventh invention provides a start pulse and a stop pulse corresponding to the start and end points of the time width to be measured, and a game. A control circuit that can output a gating clock signal, and a control circuit that can output a gating clock signal.
In a device that is equipped with a counter that measures t and measures a measured time width from the output of the counter and a so-called fractional time,
means for outputting a strobe signal having a constant pulse width in synchronization with a start pulse and a stop pulse; oscillation is stopped during the pulse width period of the strobe signal;
After the strobe signal pulse disappears, a fractional time measuring circuit consisting of an oscillation means that performs oscillation operation at the period of the clock signal, and a phase detector that detects the phase difference between the output signal of the oscillation means and the clock signal is activated. The phase difference signal from the fractional time measuring circuit is calculated based on the fractional time, and the time width to be measured is measured.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an example of the configuration of a fractional time measuring circuit, which is a main part of the present invention. Moreover, FIG. 2 shows a mouth according to the present invention,
1 is a block diagram of a width measuring device, and FIG. 3 is a time chart.

First, the entire time width measuring device according to the present invention will be explained using FIG. In the figure, reference numeral 1 denotes an input horn amplifier, which shapes the waveform of a signal having a time width to be measured introduced from an input terminal p1 into a rectangular wave as shown in FIG. 3(A). 3 is a control circuit which introduces the signal from the input amplifier 1 having the time width Tx to be measured and the clock signal;
It is possible to output a start pulse S1, a stop pulse S2, and a gating clock signal S4 corresponding to the start point and end point of the measured time width Tx. A counter 5 measures the number of times the gating clock signal S4 introduced from the control circuit 3 crosses this level.

7 is a clock generator, which generates a clock signal serving as a time reference with a period To. Reference numerals 8 and 9 denote fractional time measuring circuits, which have a mechanism for introducing a start pulse s1, a stop pulse S2, and a clock signal, and outputting a phase difference signal that is the basis for calculating fractional time. 8.9
Both have the same configuration, and the fractional time measuring circuit 8 measures the first fractional time ΔT, which occurs at the time of the start pulse S1,
The fractional time measuring circuit 9 outputs a phase difference signal that is the basis for calculating the second fractional time Δd2 that occurs at the time of the stop pulse S2. . The configuration of the fractional time measuring circuits 8, 9 is illustrated in detail in FIG. A microprocessor 11 receives signals from the counter 5 and the fractional time measurement circuits 8 and 9, and performs calculations to determine the time width.

In FIG. 1, 21 is a rising edge detection circuit, which detects the rising edge of the start pulse s1 or stop pulse S2 applied to the input terminal p3, and generates a strobe signal with a constant pulse width τQ shown in FIG. 3(d). This outputs st.

22 is VCO (voltage control)
d oscillator), and the inverter a and the delay device form a loop as shown in FIG. For example, a variable capacitance diode C2 is provided, and this container is changed by a voltage signal S6 applied from the outside, so that it oscillates at a frequency corresponding to this voltage. This V CO22 operates so that it oscillates when the strobe signal st is ``low'' and stops oscillating when it is high.Then, oscillation is started when the strobe signal st changes from ``high'' to ``low''. Operate.

23 is a phase detector, which outputs the output signal s5 of V CO22.
and clock signal sr are introduced, and a signal corresponding to the phase difference between these two signals is output. The output of this phase detector 23 is guided to a selection circuit 24.

The selection circuit 24 receives the signal S7 from the flip-flop 27.
controlled by If this signal s7 is, for example, "low"
If this is the case, the signal from the phase detector 23 is output as is to the next stage, and if the signal s7 is applied, the output state of the phase detector 23 when this signal s7 is applied is held and output to the next stage.Selection The output of the circuit 24 is introduced into a loop filter 25, and the output signal s6 of this loop filter 25 is V
Controls the variable capacitance diode C2 of CO22. This loop filter 25 is combined with the VCO 22 to form a PLL circuit, and has an appropriate time constant for this Pl-[- circuit. The output of the phase detector 23 is converted into a digital signal at high speed by the AD converter 2G, and the microprocessor 11 in FIG. 2 performs calculations to be described later. The flip-flop 27 is set and reset by a signal s8 applied to the terminal p5.

The operation of the circuits of FIGS. 1 and 2 configured as described above will be explained.

A signal having the time width to be measured, which is applied to the input terminal p1, is waveform-shaped by the input amplifier 1, becomes a signal as shown in (a) in FIG. 3, and is introduced into the control circuit 3. The control circuit 3 outputs a start pulse S1 and a stop pulse S2 as shown in FIGS. 3(b) and 3(c) at the rising edge and falling edge of the signal in FIG. 3(a), respectively. Further, in the restriction 0 circuit 3, a clock signal is introduced from the clock generator 7, and a start pulse s1. The gate circuit (not shown) is open during the period of clock signals C9 and Cn generated after the stop pulse S2 is generated, and the gating clock signal S4 passing through this gate circuit is as shown in FIG. H).

This gating clock signal S4 is counted by the counter 5 (count number N), and the gating clock signal S4 is counted by the counter 5 (count number N)
1, the calculation of N T o shown in equation (1) is performed.

On the other hand, the fractional time measuring circuit 8 introduces the start pulse S1 and outputs a phase difference signal, which is the basis for calculating the fractional time ΔT1, by the following operation.

Hereinafter, with reference mainly to FIG. 1, an explanation will be given of the operation for obtaining a signal with a phase difference that is irregular at a fractional time.

The VCO 22 oscillates at a frequency determined by the delay device. (The q-phase detection type 23 outputs a signal according to the phase difference between the two introduced No. 1a (clock signal sr and signal s5 from the VCO 22). On the other hand, the flip-flop 2
7 is low, the selection circuit 24 transmits the signal from the phase detector 23 to the next stage.The signal corresponding to this phase difference is passed through the loop filter 25 to the voltage signal S6. So, variable capacitance diode C2!
l control. Since feedback is applied so that this phase difference becomes zero, the signal S generated by the VCO 22 is
5 and the clock signal sr are in the same phase.

When the start pulse s1 is applied in such a state, the rising edge detection circuit 21 outputs a strobe signal st having a constant pulse width τ0, which is different from that shown in FIG. 3(d). As a result, the VCO 22 stops R imaging during the period of this pulse width τ0. Then, when this strobe signal st disappears,
In synchronization with this, the VCO 22 starts oscillating again.

Note that the flip-flop 27 is inverted in synchronization with the generation of the strobe signal st, so the signal S7 is "high".Therefore, the selection circuit 24 selects the signal @S5 and the clock signal sr immediately before the oscillation stops. Holds and outputs the value of the phase difference between the VCO and the VCO.
Since the output signal S5 of VCO 22 and the clock signal sr are in the same phase, the output signal of the VCO 22 that oscillates again after the strobe signal st disappears has the same frequency as the clock signal sr. , the phase of the re-oscillated output signal S5 at VC○22 is equal to the clock signal sr
This results in a phase difference of δ shown in FIG. Here, from (e) and (g) in FIG. 3, the phase shift amount δ is expressed by equation (2).

δ1=τ1+τo+To/2 TO(2) Here, To: Period of clock signal sr τ1 The time difference between the generation of the Nistart pulse and the rise of the previous clock signal τ, −T0−8T, Therefore, First fractional time ΔT
1 can be expressed by Equation (3) by restating Equation (2).

ΔT+=τ0−δ++TO/2 (3) This phase shift end δ1 is the output 111 of the phase detector 23.
1, which is quickly converted into digital 1 by the AD converter 26 and sent to the microprocessor 11 as a signal S9.

Here, in equation (3), the pulse width τ0 of the strobe signal and the period TO of the clock signal are known in advance, and (lα of δ is known from the signal S9, so the microprocessor 11 calculates ( 3) The first fractional time ΔT1 can be calculated by calculating the equation.

Next, when the signal representing the time width to be measured falls and the stop pulse S2 is generated at the timing shown in FIG.
is applied to the fractional time measuring circuit 9.

In this case, the phase shift distance δ2 of the output signal S5 of the VCO 22 is expressed by equation (4) from (k) and (g) in FIG.

δ2=τ2+τ. -TO(4) τ2 The time difference between the generation of the Nistop pulse and the rise of the previous clock signal. Therefore, the second short period of time is expressed by equation (5).

ΔT2=−τ. -δ2 (5) In this case, as well as above, the value of phase difference δ2 is (No. 3 S9
As you can see, in MicroProcera IL11, (5)
By deriving the formula, the second fractional time ΔT2 can be determined.

Note that the formula for calculating fractional time is (3) and (5).
This differs depending on whether the timing at which the start pulse S1 and stop pulse S2 are generated is when the clock signal is at the "high" level or when the clock signal is at the "lower" level.

That is, if the start pulse S1 or the stop pulse S2 is generated when the clock signal sr is at the ``hyper level'', the fractional time is calculated by equation (3).
If the occurrence occurs during a ruble time, the fractional time is calculated using equation (5).

Therefore, the microprocessor 11 outputs the start pulse S1
, if the "high" or "low" level information of the clock signal when the stop pulse S2 is generated is introduced from the fractional time measurement circuits 8 and 9, the selection of equations (3) and (5) can be easily made. You will be able to calculate fractional hours correctly.

Note that the circuit for detecting this level information and the route for transmitting this information to the microprocessor 11 can be achieved by common sense means, so their description is omitted in FIGS. 1 and 2.

As a result of the above, the microprocessor 11 can calculate the time width Tx of the measurement target image by further calculating the equation (1).

In addition, after the start pulse S1 and stop pulse S2, in preparation for the measurement of the next fractional time, the (
The reset signal S5 must be in the same phase as the clock signal S. Therefore, the reset signal S5 must be connected to the terminal p5.
8 (for example, output from the microprocessor 11), resets the flip-flop 27 and outputs the signal S7.
The output signal S5 of the VCO 22 and the clock signal are brought to the same phase as the output signal S5 of the VCO 22 and the clock signal.

In addition,) Flip-flop 27 or I Uno 1 in 2'r heather
As a result of changing No. 8 S7, if the hold is suddenly released, the frequency may be significantly distorted, and this may gradually return. Here, since it is sufficient to change the phase without changing the frequency, a switch F-33 is provided as shown in FIG. 6, and is normally connected to the contact side. Then, as described above, the contact 9 is connected only when the phase is to be returned. In the case of the contact point 9, a portion proportional to the phase difference (1/α) is energized, and the phase difference can be corrected at high speed. Then, the coincidence detector 32 checks that the phase difference has disappeared, and if they match, the contact of the switch 33 is set to the h side. Subsequently, the hold of the selection circuit 24 is released by the reset signal S8.

By doing so, the above problem can be solved.

Furthermore, if AD conversion is performed multiple times and the results are statistically processed, the phase difference δ7. The measurement accuracy of δ2 can be improved.

Moreover, noise can be cut by providing a low-pass filter (not shown) in front of the AD converter 2G.

Furthermore, if the phase detector 23 is configured to detect the phase difference as a pulse width and convert it into a voltage value using, for example, an RC filter, it will take a time constant until the output becomes stable. Ripples also occur, causing errors. Therefore, by configuring the phase detector 23 as shown in FIG. 7, the above drawbacks can be solved. FIG. 7 is a diagram showing a specific example of the phase detector 23 in FIG. 1, and the output signal s12 in the diagram is guided to the selection circuit 24 and AD converter 2G in FIG. 1. Moreover, FIG. 8 is a time chart of the circuit of FIG. 7. In FIG. 7, a phase discrimination circuit 41 determines the phase of the signal s5 from the VCO 22 and the clock signal sr, and controls switching of the switch 43 with a pulse width corresponding to the phase difference δ (see FIG. 8).

As a result, the switch 43 outputs the signal 510 (see FIG. 8) to the next stage's interval averaging circuit (composed of an integrator 45, a sample-and-hold circuit 47, and a feedback resistor R)/\\.

This number hold circuit 47 receives a signal @sll synchronized with the rising edge of the clock signal sr (see FIG. 8).
The output of the integrator 45 is sampled at the timing of , and the sampled value is held during the other periods. In the time chart of FIG. 8, the phases of the signal S5 and the clock signal sr match until time Co. In this case, both the signal s10 and the output signal s12 of the circuit of FIG.
■It is.

Next, at time C1, when the signal S5 has a phase delay of δ with respect to the clock signal Sr, the output signal s10 of the switch 43
becomes a signal with a pulse width δ.

AT.

It is known that when the constant of the interval averaging circuit is 1, the output follows the input at high speed, and the output of the circuit in Figure 7 (+
The i number s12 becomes constant at 2 samples (time C3). Note that A is the amplification degree of the amplifier of the sample and hold circuit 47, the capacitance of the capacitor of the c t,t MX divider 45, R is the value of the feedback resistor, and TO is the period of the clock signal.

In this way, by combining the phase discrimination circuit 41 and the interval averaging circuit as the phase detector 23 and obtaining a ripple-free phase difference voltage in a short time, high-speed and highly accurate ΔD conversion becomes possible.

No. ``Effects of the Present Invention'' As described above, according to the present invention, the following effects are achieved.σ) The conventional device requires time for the main clock and the vernier clock to match. Even if the operating speed of the AD converter becomes faster in the future than it is now, this time is a theoretically necessary time and there is no room for improvement.

On the other hand, in the device according to the present invention, the output of the phase detector 23 is directly converted into 〇 and then operated by a microcomputer, etc., but the AD converter is currently a parallel-Dari type AD converter. There are very high-speed methods such as, for example, and for this reason, the present invention can operate at higher speeds than conventional means based on its operating principle.

Therefore, the time width can be measured at high speed and in real time.

■ Since the output of the phase detector 23 can be visually measured multiple times as necessary, by statistically processing this,
Fractional time can be measured with high precision.

■ The time vernier method detects the point where the phases of the main clock and vernier clock match, so a certain amount of time is absolutely necessary. In the present invention, since the phase difference between the signal S5 of the V CO22 and the clock signal S' is detected,
It is possible to output this phase difference immediately and measure fractional time in a short time, and although it takes a little extra between R,
It has wide applicability, as it can measure phase differences 51 times and perform statistical processing to improve measurement accuracy.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the configuration of a fractional time measuring circuit which is a main part of the present invention, Fig. 2 is a block diagram of a time width reduction measuring device according to the present invention, Fig. 3 is a time chart, and Fig. 4 is a diagram showing the general principle of time width measurement, FIG. 5 is a diagram to explain the operation of the time vernier method, FIG. 6 is a diagram showing another configuration example of the present invention, and FIG. 7 is a diagram showing phase detection. FIG. 8 is a time chart of the circuit shown in FIG. 7, which is a diagram showing a specific example of the device. DESCRIPTION OF SYMBOLS 1... Input amplifier, 3... Control circuit, 5... Counter, 7... Clock generator, 8, 9... Fractional time measuring circuit, 11... Microprocessor, 21...
- Rise detection circuit, 22... VCO123... Phase detector, 24... Selection@path, 25... Loop filter, 2G... AD converter, 27... Flip-flop, 30...・Adder, 31... Subtractor, 32...
- Coincidence detector, 33... switch. Elementary 1 Figure 2 VCO Figure 2 Figure 4 Figure S

Claims (1)

[Claims] A control circuit capable of outputting a start pulse, a stop pulse, and a gating clock signal corresponding to the start and end points of the time width to be measured, and a counter that counts the gating clock signal. In a device for measuring a measured time width from a counter output and a so-called fractional time, a means for outputting a strobe signal having a constant pulse width in synchronization with a start pulse and a stop pulse, and a pulse of the strobe signal. The period of width stops oscillation,
After the strobe signal pulse disappears, a fractional time measuring circuit consisting of an oscillation means that performs oscillation operation at the period of the clock signal, and a phase detector that detects the phase difference between the output signal of the oscillation means and the clock signal is activated. A time width measuring device comprising: calculating a fractional time by calculating a fractional time based on a phase difference signal from the fractional time measuring circuit, and measuring a measured time width.