JP2524617B2 - Frequency measuring device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a frequency measuring device capable of measuring the frequency of a signal under measurement with high accuracy.

[Prior Art] Generally, a frequency measuring device of a reciprocal system, which digitally and accurately measures a frequency, is configured as shown in FIG. 3, for example. FIG. 4 is a time chart showing the operation. That is, the signal to be measured B input from the input terminal 1 is input to the frequency divider 2 whose frequency division ratio 1 / M is determined based on the setting signal given to the terminal 10. And
When the reset signal B is input from the reset terminal 3, the first output pulse is output from the frequency divider 2 onto the frequency divided signal C at time t ₀ , and the flip-flop 4 at the next stage is set.
Then, an H level gate signal D is output from the Q output terminal of the flip-flop 4 to one input terminal of the AND gate 5. A reference signal E having a known period T is input from the reference signal oscillator 6 to the other input terminal of the AND gate 5. Therefore, the counter 7 starts counting the number of pulses of the reference signal e passing through the AND gate 5 from time t ₀ .

Then, at time t ₁ when the number of pulses of the signal under measurement a input to the frequency divider 2 reaches M, the frequency divider 2 outputs the next output pulse on the frequency divided signal c. As a result, the flip-flop 4 is reset and the gate signal D becomes L level. Then, the counter 7 sends the count value L counted during the H level period (t _{0 to} t ₁ ) of the gate signal D to the arithmetic circuit 8 of the next stage. In the arithmetic circuit 8, the frequency F of the signal under measurement a is calculated by the equation (1) and displayed on the display 9.

F = M / (L · T) (1) [Problems to be Solved by the Invention] However, the frequency measuring device configured as described above also has the following problems. That is, since the rising and falling times of the gate signal d rising and falling in synchronization with the pulse of the signal under test a and the rising and falling times of each pulse of the instrument size signal e are not synchronized, Fractional times of ΔT ₀ and ΔT ₁ occur at the rising and falling edges of signal d. Therefore, this fractional time causes a measurement error in the entire frequency measuring device.

To reduce the fractional time ΔT ₀ , ΔT ₁ and perform accurate measurement, it is sufficient to set the frequency of the reference signal e high, but if the frequency of the reference signal e is set high, this reference signal e Since it is necessary to use an expensive element that responds at high speed to the reference signal oscillator 6 that creates the reference signal and the constituent circuit elements of the AND gate 5 and the counter 7 to which the reference signal e is input, the manufacturing cost of the entire apparatus is significantly increased. There is a problem to rise.

In addition, a reciprocal frequency measuring device has been developed which expands the fractional time ΔT ₀ , ΔT ₁ by analog technology, for example, a time / voltage conversion method, etc., and measures and calculates including error. Since an analog integrator is incorporated in this device, there is a problem that not only the adjustment is complicated, but also errors due to temperature changes and changes over time are likely to occur.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an auxiliary signal that can be synchronized with a gate signal in a phase locked loop (PLL) in addition to the reference signal without setting the frequency of the reference signal high. The purpose of the present invention is to provide a frequency measuring device which can digitally measure the frequency of a signal under measurement including a fractional time with high accuracy.

[Means for Solving the Problem] The frequency measuring device of the present invention includes a voltage-controlled oscillator 15 that outputs an auxiliary signal g having a frequency corresponding to an input voltage level.
A first frequency divider 17 that divides the frequency of the auxiliary signal output from the voltage controlled oscillator into 1 / N, and a frequency of the reference signal d output from the reference signal oscillator 18 into 1 / (N +
n) and the phase difference between the second frequency divider 19 and the output signals output from the frequency dividers, and a voltage signal corresponding to the phase difference is sent to the voltage controlled oscillator. A phase difference detector 22 that forms a phase locked loop (PLL), a third frequency divider 12 that divides the frequency of the signal under measurement a into 1 / M, and a frequency divider from this third frequency divider. In response to the signal c output, monostable circuits 13a and 13b as trigger pulse generating circuits for sending a trigger pulse signal f for stopping the oscillation of the voltage controlled oscillator for a predetermined time T ₀ , and the auxiliary signal A phase coincidence detection circuit 16 which outputs a phase coincidence signal 1 when the phase coincides with the reference signal, and a pre-gate time T ₁ from the output of the trigger pulse signal to the output of the phase coincidence signal.
Auxiliary gate time setting circuit 14 that sets the subsequent gate time T ₂ from the output of the trigger pulse signal output in response to the input of the next divided signal to the output of the next phase matching signal , 25, and a main gate time setting circuit 24, 26 for setting a main gate time T ₃ from the front gate time end time to the rear gate time end time, and counting the number of pulses of the reference signal at the main gate time. The main counter 32, and the up-down counter 27 as an auxiliary counter that counts the number of pulses of the auxiliary signal in the previous gate time by adding, and subtracts the number of pulses of the auxiliary signal in the rear gate time, and the main total. An arithmetic circuit 29 for calculating the frequency of the signal under measurement from the count value of the number counter and the count value of the up / down counter is provided.

[Operation] In the frequency measuring device configured as described above, the reference signal oscillator, the first and second frequency dividers, the phase difference detector,
The voltage controlled oscillator forms a phase locked loop (PLL), and the ratio of the frequency division ratios of the first frequency divider and the second frequency divider is N: (N
+ N), the ratio of the cycles of the reference signal d and the auxiliary signal g finally becomes N: (N + n). Also, the ratio measurement signal a
Before represented by until the third frequency divider of the frequency division signal phase coincidence signal l input time output from the beginning phase coincidence detecting circuit from the operation start signal is output to the predetermined time T ₀ from the output of c synchronized with The gate time T ₁ is an integral multiple of the cycle of the auxiliary signal g. Similarly, the rear gate time T ₂ is also an integral multiple of the cycle of the auxiliary signal g. Since the reference signal d and the auxiliary signal g are synchronized at the end of each gate time T ₁ , T ₂ , the main gate time T ₃
Is also an integral multiple of the reference signal d. Therefore, the surrounding T _X of the frequency-divided signal c, which is M times the signal under measurement a, is given by equation (2).

T _X = (T ₀ + T ₁ ) + T ₃ − (T ₀ + T ₂ ) = T ₁ + T ₃ −T ₂ (2) The above (T ₁ −T ₂ ) is measured by an up / down counter, and T ₃
Is measured by the main counter. Then, the frequency F of the signal under measurement is calculated by the arithmetic circuit by the equation (3).

F = M / T [L + K (N + n) / N] (3) where M is the frequency division ratio of the third frequency divider, T is the period of the reference signal,
L: Count value of main counter, K: Count value of up-down counter,
N: division ratio of the first divider, N + n: second divider.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a frequency measuring device of an embodiment. The signal to be measured a having the frequency F (cycle P) input from the input terminal 11 is divided into 1 / M in the third frequency divider 12 based on the division ratio setting signal provided to the terminal 35. Third
The frequency-divided signal c output from the frequency divider 12 is a monostable circuit 13a.
Is input to. This monostable circuit 13a sends out an inhibit signal e which becomes L level for a predetermined time T _A from the input time when the divided signal c is inputted to the D input terminal of the D-type flip-flop 14 and the monostable circuit 13b of the next stage. To do. The monostable circuit 13b is a trigger pulse signal which becomes H level for a predetermined time T ₀ (T ₀ <T _A ), when the inhibition signal e changes to L level, that is, after the divided signal c is input to the monostable circuit 13a. f is sent to the reset terminal R of the D-type flip-flop 14 and is also supplied to the control terminal of the voltage controlled oscillator (VCO) 15 which constitutes the phase locked loop (PLL).

The voltage controlled oscillator 15 stops oscillating when the level of the trigger pulse signal f supplied to the control terminal becomes H level, and starts oscillating when it becomes L level. That is, the rising edge of the trigger pulse signal f output from the monostable circuit 13b becomes the oscillation stop signal, and the falling edge becomes the operation start signal. The cycle output from this voltage controlled oscillator 15 (T + Δ
The auxiliary signal g of T) acts as a phase coincidence detection circuit D
It is inputted to the clock terminal C of the flip-flop 16 and divided by the first frequency divider 17 into 1 / N. On the other hand, the reference signal d having the period T output from the reference signal oscillator 18
Is input to the D input terminal of the D-type flip-flop 16 and divided by the second frequency divider 19 into 1 / (N + 1). The output signals of the first and second frequency dividers 17 and 19 are input to the phase difference detector 22 via OR gates 20 and 21, respectively. This phase difference detector 22 includes a first and a second frequency divider 17,1
The phase difference between the output signals input from 9 is detected, and the voltage signal corresponding to this phase difference is sent to the voltage controlled oscillator 15 via the loop filter 23. Then, the voltage controlled oscillator
15, reference signal oscillator 18, first and second frequency divider 17,1
9, OR gate 20,21, phase difference detector 22, loop filter
Reference numeral 23 constitutes a phase locked loop (PLL). Therefore, the frequency of the auxiliary signal g output from the voltage controlled oscillator 15 is controlled so that the phase difference between the output signals of the first and second frequency dividing circuits 17 and 19 becomes zero. Finally, the cycle (T + ΔT) of the auxiliary signal g has the relationship of the expression (4) with respect to the cycle T of the reference signal d.

(T + ΔT) = T (N + 1) / N (4) When the auxiliary signal g input to the clock terminal C changes to H level, D
When the reference signal d input to the input terminal is H level, the output terminal Q becomes H level, and when it is L level, it becomes L level. Therefore, when the rising edge of the auxiliary signal g and the rising edge of the reference signal d are substantially synchronized, the output signal of the Q output terminal changes from the L level to the H level. That is, when the phases of both signals g and d match, the phase matching signal 1 is supplied from the D-type flip-flop 16 to the clock terminal C of the D-type flip-flop 14.

When the H-level phase matching signal 1 is input to the clock terminal C, the D-type flip-flop 14 transfers the logical value of the inhibition signal e input to the D input terminal to the clock terminal of the flip-flop 24 via the Q output terminal. At the same time, the inverted logical value of the inhibit signal e is output via the output terminal to the other input terminal of each OR gate 20, 21, the reset terminal R of the first and second frequency dividers 17 and 19, and the AND terminal. Transfer to gate 25. D-type flip-flop 14 and AND gate
Reference numeral 25 constitutes an auxiliary gate time setting circuit. When the input signal at the clock terminal C changes to the H level, the flip-flop 24 sends the H level output signal j from the Q output terminal to the AND gate 26 and the control terminals of the up / down counter 27. The flip-flop 24 and the AND gate 26 form a main gate time setting circuit. The up / down counter 27 counts the number of pulses of the auxiliary signal g input via the inverter 28 and the AND gate 25. However, it counts up while the input signal j of the control terminal is at L level and counts down while the input signal j is at H level. The counting result K is sent to the arithmetic circuit 29. A trigger pulse signal f of the monostable circuit 13b is input to the AND gate 25 via the inverter 30. Further, the reference signal d of the reference signal oscillator 18 is guided to the main counter 32 via the inverter 31 and the AND gate 26, and the number of pulses is counted there. The counting result L is input to the arithmetic circuit 29. The arithmetic circuit 29 calculates the frequency F of the signal under measurement a according to the equation (5).

F = M / T [L + K (N + 1) / N] (5) The calculation result is digitally displayed on the display 33.

Further, in the figure, 34 is a reset terminal, and the reset signal b input to the reset terminal 34 is applied to the counters 27, 32,
The arithmetic circuit 29, the flip-flop 24, and the third frequency divider 12 are reset.

The operation of the frequency measuring device thus configured will be described with reference to the time chart of FIG. In addition, it is assumed that the cycle of the auxiliary signal g of the voltage controlled oscillator 15 is controlled in advance by the action of the phase locked loop (PLL) as shown in the above equation (4).

First, the reset signal b sets the output signal j of the flip-flop 24 to L level, and controls the up / down counter 27 to count up. Then, when the reset signal b is released, the third frequency divider 12 is activated. When the first divided signal c is output at time t _0, the inhibition signal e of the monostable circuit 13a becomes L level. Synchronously, the trigger pulse signal f of the monostable circuit 13b rises to the H level, the D flip-flop 14 is reset, and the oscillation of the voltage controlled oscillator 15 is stopped. Further, the H level of the FF output signal h at the output terminal of the D-type flip-flop 14 holds the first and second frequency dividers 17 and 19 in the reset state and the OR gate 2
0 and 21 are closed, both inputs of the phase difference detector 22 are fixed to H level, the phase difference detection operation is stopped, and the phase synchronization circuit (PLL)
Is temporarily held. The trigger pulse signal f falls to L level becomes from time t ₀ to time t ₁ after a predetermined time T ₀ has elapsed, the output of the auxiliary signal g is started from the voltage controlled oscillator 15 in synchronism with the falling . The frequency of the voltage controlled oscillator 15 is held at the frequency before the stop because the input voltage is in the hold state. Then, the up / down counter 27 starts counting up the number of pulses of the inverted auxiliary signal g.

If the reference signal d is at the H level at the moment when the output of the auxiliary signal g is started, the D-type flip-flop 16 operating as a phase-matching circuit shifts to the D-type flip-flop 14 from the original phase-matching signal rising to the H-level. Is supplied with a signal having a different meaning, but since the pulse width time is set to T ₀ <T _A at this point, the prohibition signal e maintains the L level, so that the FF output signal h It does not flip. Further, even if the original phase matching signal 1 generated at the rising of the auxiliary signal g and the rising of the reference signal d is output during the L level of the prohibiting signal e, the inversion of the D-type flip-flop 14 is made at this point. It is prohibited, and the up / down counter 27 continues the counting up operation.

When the phase of the at time t ₂ after the time T ₁ elapses from the time t ₁ and the reference signal d and the auxiliary signal g match, outputs the phase coincidence signal l, D-type flip-flop 14 is the set and the Q The output signal level is inverted. The L level of the inverted FF output signal h is the first and second frequency divider 1
The reset states of 7 and 19 are released at the same time, the OR gates 20 and 21 are opened to release the temporary hold state of the phase locked loop (PLL), and the phase lock control is started. This time,
Since the phase difference detector 22 detects a falling change in which both inputs are at the L level at the same time, the phase synchronization control state is achieved without outputting the phase difference correction. The AND gate 25 is closed by the inversion of the FF output signal h, and the up / down counter 27 counts the auxiliary signal g by the number of K ₁ pulses. That is, the time T ₁ constitutes the previous gate time. At the same time, since the FF output signal j of the flip-flop 24 is inverted, the counting direction of the up / down counter 27 is inverted, the AND gate 26 is opened, and the main counter 32 counts the number of pulses of the reference signal d. Be started.

Then, when the next divided signal c is input at time t ₃ ,
The same operation as at time t ₀ , the time after the elapse of a predetermined time T ₀
The AND gate 25 opens at t ₄ , and the up-down counter 27 starts counting the number of pulses of the auxiliary signal g again. in this case,
Since the counting direction is reversed, it continues to count down from the previous count value K1 of the gate time T _1.

Then, when the phase of the auxiliary signal g and the reference signal d match at time t ₅ after the time T _{2 has} elapsed from time t ₄ , the phase matching signal 1 is output and the D-type flip-flop 14 is set.
FF output signal h and FF output signal j of flip-flop 24
Is reversed. Then, at time t _5, AND gate 25,32
Is closed, the main counter 32 counts the reference signal e by L pulses, and the up / down counter 27 subtracts K ₂ pulses from the auxiliary signal g, and the value K (= K1−K2) is K ₁ >. positive when K _2, are left as negative when K ₁ <K _2. Then time T
₂ is the rear gate time, and the time T from time t ₂ to time t _5
3 is the main gate time.

The frequency F of the signal to be measured a is obtained from the respective count values L and K obtained by the main counter 32 and the up / down counter 27 in the arithmetic circuit 29 by using the above equation (5).

In the frequency measuring device configured as described above, the front gate time T ₁ and the rear gate time T ₁ whose length is variably adjusted until the rising of the signal under measurement a is synchronized with the reference signal d
By setting T ₂ , the measurement error due to the fractional time can be significantly reduced as compared with the conventional device shown in FIG.

Further, when the ratio of the frequency division ratio between the first frequency divider 17 and the second frequency divider 19 is set to about N: (N + 1), the frequency of the auxiliary signal g is also compared with the frequency of the reference signal d. Since it does not change significantly, it is not necessary to use each electronic component corresponding to a particularly high frequency. Therefore, the measurement accuracy can be significantly improved while the increase in manufacturing cost is suppressed to the minimum.

As described above, according to the present invention, the auxiliary signal that can be synchronized with the gate signal by the phase locked loop (PLL) is used in addition to the reference signal. As a result, it is possible to measure the frequency of the signal under measurement with high accuracy, including the fractional hours, without significantly increasing the manufacturing cost with a simple circuit configuration.

[Brief description of drawings]

1 is a block diagram showing a frequency measuring device according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the same embodiment, FIG. 3 is a block diagram showing a conventional frequency measuring device, and FIG. The figure is a time chart showing the operation of the conventional device. 12 …… Third frequency divider, 13a, 13b …… Monostable circuit, 14,16…
… D-type flip-flop, 15… Voltage controlled oscillator, 17…
… First frequency divider, 18 …… Reference signal oscillator, 19 …… Second frequency divider, 22 …… Phase difference detector, 24 …… Flip-flop, 25,26 …… And gate, 27 …… Up-down counter, 29 ... Arithmetic circuit, 32 ... Main counter, 33 ... Display,
T ₁ …… Front gate time, T ₂ …… Rear gate time, T ₃ …… Main gate time.

Claims (1)

(57) [Claims] 1. A voltage controlled oscillator (15) for outputting an auxiliary signal (g) having a frequency according to an input voltage level, and the frequency of the auxiliary signal output from the voltage controlled oscillator is divided into 1 / N. And a second frequency divider (19) for frequency-dividing the frequency of the reference signal (d) output from the reference signal oscillator (18) into 1 / (N + n)
And a phase difference detector that detects a phase difference between output signals output from the frequency dividers and sends a voltage signal corresponding to the phase difference to the voltage controlled oscillator to form a phase locked loop (PLL). (2
2), a third frequency divider (12) for dividing the frequency of the signal under measurement (a) into 1 / M, and a frequency division signal (c) output from the third frequency divider. And a trigger pulse generating circuit (13a, 13b) for sending a trigger pulse signal (f) for stopping the oscillation of the voltage controlled oscillator for a predetermined time (T ₀ ), and the auxiliary signal and the reference signal. Phase match detection circuit (16) that outputs a phase match signal (l) when the phases match
And setting the previous gate time (T ₁ ) from the output of the trigger pulse signal to the output of the phase matching signal, and the output of the trigger pulse signal in response to the input of the next divided signal. Auxiliary gate time setting circuit (14, 25) for setting the rear gate time (T ₂ ) from the time the signal is output to the next phase match signal, and from the previous gate time end time to the rear gate time end time A main gate time setting circuit (24, 26) for setting a main gate time (T ₃ ) of the main gate time, a main counter (32) for counting the number of pulses of the reference signal in the main gate time, and an auxiliary in the gate time. An auxiliary counter (27) that counts the number of pulses of the signal and subtracts the number of pulses of the auxiliary signal in the subsequent gate time, and the count value of the main counter and the count value of the auxiliary counter. Measurement signal circumference A frequency measuring device having an arithmetic circuit (29) for calculating the wave number.