JPS6048922B2 - frequency discriminator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency discriminator, and by using a reference oscillator that is extremely stable against temperature fluctuations, it is possible to perform highly accurate frequency discrimination with extremely little drift due to temperature, and is suitable for IC implementation. The purpose of this invention is to provide a frequency discriminator with

FIG. 1 shows a block diagram of an example of a conventional frequency discriminator.

In the same figure, a pulse a as shown in FIG. 2A, which has entered from an input terminal 1, is supplied to a delay device 2, where it is delayed by a predetermined fixed time Td to become a pulse as shown in FIG. 2B. and is supplied to the phase comparator 3. This phase comparator 3 compares the phase of the input pulse a and the phase of the pulse b, and outputs a voltage corresponding to the phase difference (time difference) as the output of the frequency discriminator. Conventionally, circuits using CR or LC have been used to generate this delay time Td, but since these have large drifts due to temperature, glass delay lines, etc. are used for applications that require high stability. It was not done.

However, commercially available glass delay lines have a delay of at most 100
However, in order to obtain a larger delay amount, the device would have to be larger in size, the attenuation would be larger, and it would be expensive because it would be a custom-made product. In particular, the phase locked servo loop of a DC motor requires a large amount of delay, so the glass delay line described above is not used, but a monostable multivibrator or a metal delay line is generally used.

However, when using LC, the external dimensions increase in proportion to the value of w, but in the above servo loop that delays a low wide wave number, the value of w must be increased.
This increases the external dimensions of the discriminator, but since it cannot be increased indefinitely, the frequency of motor rotation detection must be increased, which has the disadvantage of increasing the cost of the rotation detector. Ta. In addition, when CR's multivibrator is used, the cost is lower and the external dimensions are smaller than that of the one shown in ↓C above, but the temperature 4 drift is large and the lock-in range of the loop described above is not larger than necessary. Due to the change, the servo will no longer lock. On the other hand, if the lock-in range is too large, the lock-in time tends to become long, which is not preferable in the above-mentioned servo loop. The present invention eliminates the above-mentioned drawbacks, and each embodiment thereof will be described below with reference to FIGS. 3 to 7A.

FIG. 3 is a circuit diagram of the first embodiment of the frequency discriminator according to the present invention, and FIGS. 4A to 4D are signal waveform diagrams for explaining the operation of FIG. 3, respectively. In FIG. 3, the input pulse shown in FIG. 4A, which comes in from the input terminal 4, is applied to the clock terminal - of a D-type flip-flop (hereinafter referred to as DFF) 5, which has a positive DC voltage applied to its D terminal. and its output Q, is ``H''
At the same time, the output Q is set to ``L'' and is applied as a sampling pulse to the analog gate 14, which will be described later. J is applied to gates 9 to open them. As a result, the oscillation output pulses of the crystal oscillator 10, which is an example of a reference oscillator with very high frequency stability and low temperature truncations, are supplied to the N-ary counter 11 through the AND gate 9, and counting is started here. When the counter 131 counts N oscillation output pulses, it applies an ``H'' pulse to the reset terminal of the DFF 5 through the AND gate 7, which is in an ``open'' state, to reset it. This results in
The Q output of the DFF 5 becomes ``L'', the AND gate 4t9 is closed, and the counting operation of the N-ary counter 11 is stopped (reset). On the other hand, the above-mentioned DFF5 has its Q output set to ``H'' due to the above-mentioned reset, and this output is applied to the clock terminal of DFF6, which has a positive DC voltage applied to its D terminal, and this is triggered to trigger the output of DFF6. Q
2 output is ``H''.

This Q. The ``H'' output of the crystal oscillator 1 is supplied to the AND gate 9 through the OR gate 8 to open it, and is simultaneously supplied to the AND gate 12 to open it.
The output oscillation pulse of 0 is applied again to the N-ary counter 11 through the AND gate 9 and counted again here. When this count value reaches N, a ``H'' pulse is sent to the counter 0.
11 to the reset terminal of the DFF6 through the AND gate 12, and the DFF6 is reset. As a result, the AND gate 9 is closed, the counter 11 is forced to stop counting, and the AND gate 12 is also closed. This state continues until Puggles enters input terminal 4 again.
When the pulse comes in again, the same operation as above is repeated.
Therefore, the Q, output of DFF5 and the Q of DFF6. The outputs are as shown in FIGS. 4B and 4C, respectively. In addition, Figure 4B
, C, TR is the period of the oscillation output pulse of the crystal oscillator 10, and NTR is the pulse width. Q of upper security FF6 shown in FIG. 4C.

The output pulse is supplied to the trapezoidal wave conversion circuit 13, where it is converted into a trapezoidal wave as shown in FIG.
4, where it is sampled with the input pulse from the input terminal 1. The output of this analog gate 14 is held in a hold circuit 15 and taken out as a frequency discrimination output. What should be noted in the above embodiment is the time relationship between the output of the N-ary counter 11 and its reset, the reset of the DFF5 and the setting of the DFF6, and the opening and closing of the AND gates 9 and 12. Since the N-ary counter 11 is reset by its own output, its output pulse width is extremely short, and the Q2 output of DFF6 is 'H'.
' By the time the AND gate 12 becomes open, the propagation delay time of the AND gate 7, DFFs 5 and 6, and the AND gate 12 has elapsed, and this is generally longer than the output pulse width of the N-ary counter 11. is long, so there will be no malfunction where the AND gate 12 resets the DFF 6 immediately after it is set for m before the reset of the counter 11 is completed. However, N-ary counter 11
There may be cases where the output pulse width of ), so in this case, for example, Q of DFF6. By providing a delay circuit using a CR that delays the output and applies it to the AND gate 12, malfunctions can be prevented. Also, the crystal oscillator 10 at the time when the AND gate 9 opens and the counter 11 starts counting operation.
Since the output signal phase of is not constant, jitter always occurs in the above embodiment.

For example, the output oscillation frequency f of the crystal oscillator 10 is 3.58M
Hz, and when this embodiment is used for a constant speed servo of a DC motor where the input pulse frequency is several tens to hundreds of Hz, the jitter is on the order of 0.001 to 0.0001%, so there is no problem. When this discriminator is used as a measuring instrument and the input becomes on the order of several tens of kilohertz, this jitter cannot be ignored. In this case, the oscillation output of the crystal oscillator 10 may be forcibly synchronized with the input pulse. FIG. 5 shows a circuit diagram of a second embodiment of the frequency discriminator according to the present invention.

This second embodiment will also be explained with reference to FIG. 8 showing a time chart. In FIG. 5, gate 16,
The portion to the left of 17 is the same as in FIG. 3, so its explanation will be omitted.

Counter 18 counts the output of gate 16.

The input period T is the object of measurement, and this period T changes. On the other hand, N
Since TR is constant, the period Tx during which the gate 16 does not output an output changes as the input cycle changes. Therefore, T
If x is large, the count number of the counter becomes large, so the count number (binary number) of the counter 18 is calculated by dividing the input period T by 2.
It is expressed as a base number. The reason for measuring Tx rather than measuring the period T itself is to increase frequency discrimination sensitivity.

That is, if we consider the case where Tx/T is, for example, 1110, when T changes by ΔT, the rate of change is ΔT/T, but if we consider Tx as the standard, Tx = T/10, so ΔT/Tx=10ΔT/T, and the gain is m
Double.

'(When the count result of the counter 18 is directly input to the D-A converter 20, the Q2 of the DFF6 shown in FIG. 8F is
During the period in which the output (there is also the reset signal C of the counter 18) is H, the output of the DA converter 20 becomes zero, and since this appears periodically every T period, the output of the DA converter 20 will have ripples. The role of the latch 19 is to remove this ripple, and holds the count result of the counter 18 with the signal shown in FIG. 8G until the next count result is output.

The magnitude of the binary number of the latch output is determined by the magnitude of the number of pulses of the outputs A and B of 16, and thereby the magnitude of the output DC voltage of the DA converter 20 is determined.

In other words, a change in period T appears as a change in voltage.

When used as a constant speed servo for a DC motor, there is no problem even if the linearity of the D-A converter 20 is poor, but since the entire circuit is digitized, almost all circuits can be implemented on one chip.
It is easy to convert into a C, and in that case, the number of external parts of the IC can be reduced and the configuration can be simplified.

However, in this case, in order to increase the sensitivity,
If the period corresponding to x is made too small, jitter becomes impossible to ignore. For example, if the output reference signal frequency of the crystal oscillator 10 is F, the jitter is 100/FrTx (%p-p
), so now Fr=3.579545MHz)
When Tx=100μs, the jitter is about 0.28% p-
It becomes p. For carbstan servo, jitter is 0.0
Since I want it to be 5% or less, I want to make Tx 600 μs or more or Fr 20 MHz or more. Or Fr to 1
The frequency may be 0 MHz or more, and the Tx may be 300 μs or more. In this case, the resolution of the DA converter 20 must be at least 12 bits based on the above conditions. Note that in the first and second embodiments, the delay time Td is set to 2NTR by using the DFFs 5 and 6, but this is because the delay time Td can be used not only for measurement but also for constant speed 5 servo of a DC motor, etc. .

In other words, if the counter is configured to count once per input pulse cycle and to output a pulse with a pulse width equivalent to the counter 2NTR, for some reason the motor rotation speed becomes slow and θ is too high, causing the Period T of input pulse. is T. If <2NTR, the delay circuit will divide the input frequency by 112 and the servo will not be able to lock properly. However, by making the counting operation of the counter 11 twice for one input pulse cycle as in each of the above embodiments, the servo will not lose lock unless TO<NTR, and TO<NTR.
This is because disturbances that cause TR are generally not applied to the DC motor. Of course, if it is used for measurement, the N-adic counter may operate once per input cycle. FIG. 6 is a circuit system diagram of a third embodiment of the frequency discriminator according to the present invention, and FIG. 7A shows a signal waveform diagram for explaining the operation of FIG. 6, respectively.

In FIG. 6, the same parts as in FIG. 3 are given the same reference numerals, and their explanations will be omitted. An input pulse as shown in FIG. 7A that comes in from the input terminal 4 is differentiated by a circuit consisting of a capacitor C1 and a resistor R1, and only the positive pulse is taken out by a diode D as shown in FIG. Applied to the terminal. Also, the above input pulse is input to inverter 2.
1, the polarity is inverted and the pulse is made into a pulse as shown in FIG. Only the positive pulse is extracted. This positive polarity pulse as shown in FIG. 7D is applied to the reset terminal of the X-ary counter 23 via the OR gate 26, and is applied to the reset terminal of the DFF 22 via the OR gate 25. Therefore, the X-ary counter 23 starts counting at the trailing edge of the input pulse. Also, the frequency from the crystal oscillator 10. The X-ary counter 23 that counts the pulses of period TR is reset when TO>XTR.
DFF through AND gate 24 and OR gate 25
The pulse applied to the reset terminal of 22 also causes T
. <For XTR, the leading edge of the input pulse! will be reset. This can prevent the phenomenon that the input pulse is frequency-divided. The Q output of DFF22 is T. > When XTR, it becomes as shown in Figure 7E, and the phase comparator (not shown)
supplied to As described above, the frequency discriminator according to the present invention delays an input pulse to be subjected to frequency and wave number discrimination for a certain period of time, and compares the phases of this delayed pulse and the input pulse to obtain a frequency discrimination output. The means for delaying a certain period of time includes a reference oscillator that oscillates and outputs a reference pulse with a period TR, an N-ary counter that counts this reference pulse, and is started by the input of the input pulse and reset after N counts, and this By providing a control circuit that resets the counter by repeating the operation of detecting a reset and counting N counts again a predetermined number of times, and maintains this reset state until the next input pulse arrives. Even when the period of the input pulse is smaller than 2NTR (for example, in a motor speed servo system), it is possible to discriminate the frequency with high precision without dividing the input pulse, and the counting operation of the above counter starts with the input pulse. By stopping (resetting) the counting operation at the leading edge of the next input pulse or after X counts, whichever comes first, frequency division of the input pulse can be prevented. By synchronizing the reference pulse with the input pulse, it has the advantage of being able to remove jitter.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an example of a conventional frequency discriminator.
2A and 2B are signal waveform diagrams for explaining the operation of FIG. 1, FIG. 3 is a circuit system diagram of the first embodiment of the frequency discriminator according to the present invention, and FIGS. 5 is a circuit diagram of the second embodiment of the frequency discriminator according to the present invention, and FIG. 6 is a circuit diagram of the third embodiment of the frequency discriminator according to the present invention.
7A is a signal waveform diagram for explaining the operation of FIG. 6, and FIGS. 8A to 8G are signal waveform diagrams for explaining the operation of FIG. 5, respectively. 5, 6, 22...D type flip-flop, 10...
Crystal oscillator, 11... N-ary counter, 13... Trapezoidal wave conversion circuit, 14... Analog gate, 15... Hold circuit, 18... Counter, 19... Latch,
20...D-A converter, 23...X-ary counter.

Claims (1)

[Scope of Claims] 1. In a frequency discriminator that delays an input pulse to be frequency discriminated for a certain period of time and compares the phase of this delayed pulse with the input pulse to obtain a frequency discrimination output, the means for delaying the certain period of time is A reference oscillator that oscillates and outputs a reference pulse of T_R, an N-ary counter that counts the reference pulse, and a counting operation of the counter is started by the input of the input pulse, and after N counts, the counter is reset. It is characterized by comprising a control circuit that detects the counter and repeats the operation of counting N counts again a predetermined number of times, then resets the counter and maintains this reset state until the next input pulse arrives. Frequency discriminator. 2. In a frequency discriminator that delays the input pulse to be frequency discriminated for a certain period of time and compares the phase of this delayed pulse with the input pulse to obtain a frequency valve output, the means for delaying the certain period of time is used to oscillate a reference pulse with a period T_R. a reference oscillator to output, an X-ary counter to count the reference pulses,
The counting operation of the counter is started at the trailing edge of the input pulse, and when the counter has counted X, the counter is reset by the output pulse of the counter, and when the next input pulse comes before the X count, A frequency discriminator comprising a control circuit that resets the counter at the leading edge of the input pulse.