KR920001718B1 - Pulse detective circuit - Google Patents

Abstract

The check and detection period of the pulse train is reduced to a half with out decreasing the resolution by adding a simple delay unit. The circuit includes a flip-flop (3) for generating gate signal, a gate unit (4) for passing the pulse train during high level of the gate signal, a counter (5) for counting the pulses passed through the gate unit (4), a first delay (6) for generating pulse output signal having a duration, a latch (7) for latching the counted value by the pulse output signal, a second delay (8) for delaying the pulse output signal to generate signal for resetting the counter, and a third delay (10) for delaying the output signal of the second delay (8) to generate the signal for resetting a frequency divier (2).

Description

Pulse train detection circuit

1 is a block diagram of a conventional pulse train detection circuit.

2 is a timing diagram of the first circuit.

3 is a block diagram of a pulse train detection circuit according to the present invention.

4 is a timing diagram of a circuit of FIG.

5 is an example of operation of the detection circuits of FIGS. 1 and 3 when a burst type input is input.

* Explanation of symbols for main parts of the drawings

1: reference frequency generator 2: 1 / N divider

3: flip-flop circuit 4: AND gate

5: counter 6: first delay circuit

7: latch circuit 8: second delay circuit

9: segment driver 10: third delay circuit

The present invention relates to a pulse train detection circuit, in particular a pulse train detection circuit which reduces the inspection and detection cycle by half without damaging the existing resolution by the addition of a simple delay circuit.

In all conventional pulse train detection circuits, such as frequency counters, digital tachometers (R.P.M.meters), speed guns, and gear detectors, reference signals from high-precision reference frequency generators are divided and used to obtain accurate unit time.

The conventional pulse train detection circuit is shown in FIG. 1, and the operation of the pulse train detection circuit will be described with reference to the timing chart of FIG. The pulse train detection circuit shown in FIG. 1 divides the outputs of the high-precision reference frequency generator (1: OSC) and the reference frequency generator (1) in order to maintain the accuracy of the result, and obtains a unit time for measurement. (2), a flip-flop circuit (3: F / F) and a flip-flop circuit (3) for outputting a gate period signal for opening and closing the gate by the unit time pulse output from the 1 / N divider (2). AND gate 4 for receiving the one input from the output terminal of the output terminal and the measured pulse train as the other input and passing the pulse train only during the counting period of the flip-flop circuit 3, and for counting the measured pulses passing through the AND gate 4. The counter 5 outputs the counter output of the counter 5 by the pulse output signals of the first delay circuit 6 and the first delay circuit 6, which generate a pulse output signal after a predetermined time (1) delay from the counter. The latch circuit 7 for latching and the output of the first delay circuit 6 are delayed after a predetermined time (2). And a second delay circuit 8 for generating a pulse output signal for resetting the instrument 5, and at the output of the latch circuit 6, a segment driver 9 for driving a segment for displaying a measurement result. Is connected.

In the pulse train detection circuit of FIG. 1, the time used for pulse train detection in the gate period T of FIG. 2a is a period during which the output of the AND gate 4 is at a high level, and a period during which the output of the AND gate 4 is at a low level. Is composed of a period for preparing the latch circuit and the reset signal to display the result value and preparing for the next recount. In FIG. 2A, 20 pulses are used to obtain a period T necessary for detection, assuming that the reference pulse units of the counting period and the resting period are 10 respectively.

Therefore, when you want to see the result at resolution of 1Hz or less (0.1,0.01, Hz), the time until the next result is displayed is too long (for example, 2sec at 1Hz resolution, 20sec at 0.1Hz resolution). Problems such as over response or instantaneous frequency change have occurred.

In addition, in order to solve this problem, a multiplier using a phase locked loop (PLL), which is widely used, has a narrow bandwidth, high accuracy, and high cost. .

It is an object of the present invention to provide a pulse train detection circuit which significantly reduces the inspection and detection cycles with a cheap structure without compromising the conventional resolution.

In order to achieve the above object, the present invention provides a reference frequency generator for generating a reference frequency, a divider for generating an output pulse signal for obtaining a measurement unit time by dividing the output of the reference frequency generator, and an output from the divider. A flip-flop circuit that outputs a gating signal by a pulse signal, and a gating signal of the flip-flop circuit is supplied to one input terminal, and a pulse string to be measured is supplied to another input terminal so that only the period when the gating signal is high level passes the measurement pulse string. Gate means for counting, counting means for counting a measurement pulse passing through the gate means, first delay means for generating a pulse output signal after a predetermined time delay from the counting period of the counting means, and pulses of the first delay means A latch circuit for latching the count output of the counter with respect to an output signal, the pulse output of the first delay means Second delay means for outputting a pulse output signal for resetting the counter by delaying the output signal by a predetermined time, and a pulse output signal for resetting the frequency divider by delaying the output of the second delay means for a predetermined time. It comprises a third delay means for outputting.

Next, the present invention will be described in detail with reference to the drawings.

3 shows a pulse train detection circuit according to the present invention, and FIG. 4 is a timing diagram thereof. In Fig. 3, the same member numbers are assigned to the same elements as those in Fig. 1.

The third pulse train detecting circuit divides the output of the corrected reference frequency generator (1: OSC) and the reference frequency generator (1) for generating a high-precision reference frequency (1 / N divider (2) to obtain a unit time for measurement. ), The output of the flip-flop circuit (3: F / F) and the flip-flop circuit (3) for outputting the gate period signal for opening and closing the gate by the unit time pulse output from the 1 / N divider (2) An AND gate 4 which receives one input from the terminal and a measurement pulse string as another input and passes a pulse string only during the counting cycle of the flip-flop circuit 3, and a counter for counting the measurement pulses passing through the AND gate 4 ( 5) latching the count output of the counter 5 by the pulse output signals of the first delay circuit 6 and the first delay circuit 6, which generate a pulse output signal after a predetermined time (τ1) delay from the count period; The counter 5 after delaying the output of the latch circuit 7 and the first delay circuit 6 for a predetermined time (τ2). A second delay circuit 8 for generating a pulse output signal for setting, and a 1 / N divider 2 used as a reference frequency divider after delaying the output of the second delay circuit 8 by a predetermined time? And a third delay circuit 10 for outputting a pulse output signal for resetting to zero. The output of the latch circuit 7 is connected with a segment driver 9 for displaying the latched information on the display.

The operation of the FIG. 3 circuit will be described with reference to the FIG. 4 timing diagram. In FIG. 4, 10 reference pulse units (N) of the counting period are assumed. The 1 / N divider 2 divides the output of the reference frequency generator 1 composed of a crystal oscillator to generate a count period reference frequency signal as shown in FIG. 4a.

The flip-flop circuit 3: F / F receives a count period reference frequency signal and generates a gating pulse as shown in FIG. 4B. The AND gate 4 accepts a pulse train to be measured at one input and the output of the flip-flop circuit 3 at the other input. As a result, the pulse train to be measured is passed only during the period during which the output of the flip-flop circuit 3 is high level (i.e., during the counting period). The counter 5 counts input pulses only during the counting period. The count output of the counter 5 is output to the latch circuit 7.

On the other hand, the first delay circuit 6 generates a pulse output after a predetermined time τ1 delay from the counting period of the gating pulse of the flip-flop circuit 3 (see FIG. 4C) to operate the latch circuit 7 to output the count. Latch.

The second delay circuit 8 resets the counter 5 by generating a pulse output after delaying the output of the first delay circuit 6 by a predetermined time [tau] 2 (see also FIG. 4d). The counter 5 thus completes the recount preparation.

On the other hand, the output of the second delay circuit 8 resets the 1 / N frequency divider 2 after a delay of a predetermined time τ3 via the third delay circuit 10 to force a new measurement count cycle to start ( See also section 4e).

Therefore, when the time constants of τ1, τ2, and τ3 are set to 1 msec or less, the actual measurement time T1 is twice the unit time in FIG. 1 according to the present invention. As shown in FIG. 4B, a pulse train detection circuit can be configured in which the unit time (i.e., counting period) and the measurement time T2 are almost the same, and as a result, the detection timing is reduced by 1/2 compared to the conventional method. Table 1 shows the measurement results according to the present invention and the prior art.

TABLE 1

It is assumed here that the measurement time is the counting period plus the rest period and the resting period is 0.03 sec. 5 shows the difference between the present invention and the operation of the conventional detection circuit when a burst type input is input to the detection circuit.

As described above, in the pulse train detection circuit according to the present invention, the detection timing (measuring period) is reduced to 1/2 as compared with the related art. It also improves reliability in transient response and instantaneous changes (see Figure 5).

Many modifications and variations are possible to those skilled in the art without departing from the spirit of the invention, all of which are within the scope of the invention.

Claims (1)

A reference frequency generator (1) for generating a reference frequency, a divider (2) for generating an output pulse signal for obtaining a measurement unit time by dividing the output of the reference frequency generator (1), and from the divider (2) A flip-flop circuit 3 for outputting a gating signal by an output pulse signal of?, A gating signal of the flip-flop circuit 3 is supplied to one input terminal, and a pulse string measured to the other input terminal is supplied so that the gating signal is high. The gate means 4 for passing the measurement pulse train only at the level of the level, the counter means 5 for counting the measurement pulse passed through the gate means 4, and the counter 5 after a predetermined time delay from the counting period. A first delay circuit 6 for generating a pulse output signal, a latch circuit 7 for latching the count output of the counter 5 by the pulse output signal of the first delay circuit 6, and the first Pulse output signal of delay circuit 6 The second delay circuit 8 for outputting a pulse output signal for resetting the counter 5 by a predetermined time delay, and the output of the second delay circuit 8 for a predetermined time delay for the divider 2 And a third delay time (10) for outputting a pulse output signal for resetting < RTI ID = 0.0 >) < / RTI > to restart a new measurement unit time of the divider (5).

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