KR910010196A - Pulse train detection circuit - Google Patents

Pulse train detection circuit

Info

Publication number
KR910010196A
KR910010196A KR1019890017445A KR890017445A KR910010196A KR 910010196 A KR910010196 A KR 910010196A KR 1019890017445 A KR1019890017445 A KR 1019890017445A KR 890017445 A KR890017445 A KR 890017445A KR 910010196 A KR910010196 A KR 910010196A
Authority
KR
South Korea
Prior art keywords
pulse
signal
delay
output
divider
Prior art date
Application number
KR1019890017445A
Other languages
Korean (ko)
Other versions
KR920001718B1 (en
Inventor
박찬현
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890017445A priority Critical patent/KR920001718B1/en
Publication of KR910010196A publication Critical patent/KR910010196A/en
Application granted granted Critical
Publication of KR920001718B1 publication Critical patent/KR920001718B1/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/10Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

내용 없음.No content.

Description

펄스열 검출회로Pulse train detection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 제1도 회로의 타이밍도.2 is a timing diagram of the first circuit.

제3도는 본 발명에 따른 펄스열 검출회로의 블록도.3 is a block diagram of a pulse train detection circuit according to the present invention.

제4도는 제3도 회로의 타이밍도.4 is a timing diagram of a circuit of FIG.

Claims (1)

기준주파수를 발생하기 위한 기준주파수 발생기(1), 상기 기준주파수 발생기(1)의 출력을 분주하여 측정단위시간을 얻기 위한 출력 펄스신호를 발생하는 분주기(2), 상기 분주기(2)로부터의 출력펄스신호에 의해 게이팅 신호를 출력하는 플립플롭회로(3), 일입력단자에 상기 플립플롭회로(3)의 게이팅신호가 공급되고, 다른 입력단자에 측정된 펄스열이 공급되어 게이팅신호가 하이레벨인 기간만 측정 펄스열을 통과시키기 위한 게이트수단(4), 상기 게이트수단(4)을 통과한 측정 펄스를 계수하기 위한 계수기수단(5), 상기 계수기(5)가 계수기간으로부터 소정시간 지연후 펄스출력신호를 발생하기 위한 제1지연회로(6), 상기 제1지연회로(6)의 펄스출력신호에 의해 상기 계수기(5)의 계수 출력을 래치시키기 위한 래치회로(7), 상기 제1지연회로(6)의 펄스출력신호를 소정시간 지연하여 상기 계수기(5)를 리세트시키기 위한 펄스출력신호를 출력하는 제2지연회로(8), 및 상기 제2지연회로(8)의 출력을 소정시간 지연하여 상기 분주기(2)를 리세트시키기 위한 펄스출력신호를 출력하는 제3지연시간(10)으로 구성되어 상기 분주기(5)의 새로운 측정단위 시간을 재시동시키는 것을 특징으로 하는 펄스열 검출회로.A reference frequency generator (1) for generating a reference frequency, a divider (2) for generating an output pulse signal for obtaining a measurement unit time by dividing the output of the reference frequency generator (1), and from the divider (2) A flip-flop circuit 3 for outputting a gating signal by an output pulse signal of?, A gating signal of the flip-flop circuit 3 is supplied to one input terminal, and a pulse string measured to the other input terminal is supplied so that the gating signal is high. The gate means 4 for passing the measurement pulse train only at the level of the level, the counter means 5 for counting the measurement pulse passed through the gate means 4, and the counter 5 after a predetermined time delay from the counting period. A first delay circuit 6 for generating a pulse output signal, a latch circuit 7 for latching the count output of the counter 5 by the pulse output signal of the first delay circuit 6, and the first Pulse output signal of delay circuit 6 The second delay circuit 8 for outputting a pulse output signal for resetting the counter 5 by a predetermined time delay, and the output of the second delay circuit 8 for a predetermined time delay for the divider 2 And a third delay time (10) for outputting a pulse output signal for resetting < RTI ID = 0.0 >) < / RTI > to restart a new measurement unit time of the divider (5). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890017445A 1989-11-29 1989-11-29 Pulse detective circuit KR920001718B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890017445A KR920001718B1 (en) 1989-11-29 1989-11-29 Pulse detective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890017445A KR920001718B1 (en) 1989-11-29 1989-11-29 Pulse detective circuit

Publications (2)

Publication Number Publication Date
KR910010196A true KR910010196A (en) 1991-06-29
KR920001718B1 KR920001718B1 (en) 1992-02-24

Family

ID=19292227

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890017445A KR920001718B1 (en) 1989-11-29 1989-11-29 Pulse detective circuit

Country Status (1)

Country Link
KR (1) KR920001718B1 (en)

Also Published As

Publication number Publication date
KR920001718B1 (en) 1992-02-24

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