JPH0455274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Object of the Invention [Field of Industrial Application] The present invention relates to a time width measuring device. More specifically, the present invention relates to a time width measuring device that can accurately measure even so-called fractional hours that are less than the period of a reference clock signal.

[Conventional technology]

Universal counters are widely used as devices for measuring the frequency, period, etc. of signals. In addition, not only counters like this, but also counters such as
Devices such as LSI testers use devices that measure the time width from a certain point to a certain point in a signal to be measured.

BACKGROUND ART In recent years, with the development of the telecommunications field, the frequencies of signals handled have increased, and there has also been a demand for measuring the time width of signals with high precision (high resolution).

Generally, the following principle is adopted to measure time width with high precision. Measured time width Tx
A clock signal with a period T ₀ is passed through a gate that is opened at , and the number N of the clocks passing through is counted. And, NT ₀ is the time width. Although this method improves resolution as the clock frequency increases, there is actually a limit to the speed of the circuit elements. That is, this means cannot measure with a resolution greater than the clock period.

Strictly speaking, in the above method, Tx does not equal NT ₀ , but TxNT ₀ . This is typically Tx
This is because T ₀ is not divisible and there are small fractional times. This is shown in FIG. In FIG. 4, ΔT ₁ is the fractional time from the rising edge of Tx to the clock C ₀ that occurs immediately thereafter;
ΔT ₂ is the fractional time from the falling edge of Tx to the immediately following clock C _o . Then, the gate is opened during the period between the clock signals _C0 and _C0 (see d in FIG. 4), and the number of clocks passing through is counted.
Assuming that the number of clocks in that period is N, the time width Tx is expressed by equation (1).

Tx=NT ₀ +ΔT ₁ −ΔT ₂ (1) Therefore, if we measure the fractional times ΔT ₁ and ΔT ₂ , we get
It can be seen from equation (1) that the time width Tx can be measured with a resolution greater than the clock period _T0 .

A time vernier method is a known means for measuring this fractional time ΔT. This time vernier method is an application of the caliper principle to the time axis, and will be explained using FIG. 5. This scheme requires, in addition to a main clock with period T ₀ , a vernier clock with period T ₀ ' (T ₀ '>T ₀ ) occurring at the beginning of the fractional time ΔT. By counting the number of clocks N until the phases of both clocks match, ΔT can be found as ΔT=N(T ₀ '−T ₀ ). The resolution is given by the period difference (T ₀ '−T ₀ ) between the two clocks.

[Problem that the invention seeks to solve]

However, the above-mentioned means has the problem that it takes time for the main clock and the vernier clock to match, as shown in FIG. 5, and high-speed repeated measurements or real-time measurements cannot be performed.

An object of the present invention is to provide a time width measuring device that can perform high-speed repetitive measurements, real-time measurements, and high-resolution measurements.

B "Structure of the Invention" [Means for Solving the Problems] In order to solve the above problems, the present invention provides a start pulse and a stop pulse corresponding to the start and end points of the time width to be measured, and a gating clock signal. In a device that is equipped with a control circuit that can output the gating clock signal and a counter that counts this gating clock signal, and that measures the time width to be measured from the output of the counter and the so-called fractional time, , a means for outputting a strobe signal having a constant pulse width, and an oscillation device that stops oscillating during the pulse width period of the strobe signal, and after the strobe signal pulse disappears, performs oscillation operation at the period of the clock signal. and a phase detector for detecting the phase difference between the output signal of the oscillation means and the clock signal. is calculated and the time width to be measured is measured.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an example of the configuration of a fractional time measuring circuit, which is a main part of the present invention. Further, FIG. 2 shows a block diagram of a time width measuring device according to the present invention, and FIG. 3 shows a time range measuring device.

First, the entire time width measuring device according to the present invention will be explained using FIG. In the figure, reference numeral 1 denotes an input amplifier, which shapes the waveform of a signal having a time width to be measured introduced from an input terminal p1 into a rectangular wave as shown in FIG. 3A. 3 is a control circuit which introduces the signal from the input amplifier 1 having the time width Tx to be measured and the clock signal, and
Start pulse s1 corresponding to the start and end points of Tx
, a stop pulse s2, and a gating clock signal s4. A counter 5 measures the number of times the gating clock signal s4 introduced from the control circuit 3 crosses a certain level. 7 is a clock generator, which generates a clock signal serving as a time reference with a period _T0 . 8,9
is a fractional time measuring circuit, and the start pulse s
1. It has a function of introducing a stop pulse s2 and a clock signal and outputting a phase difference signal which is the basis for calculating fractional time. 8 and 9 both have the same configuration, and the fractional time measuring circuit 8 outputs a phase difference signal that is the basis for calculating the first fractional time ΔT ₁ that occurs at the time of the start pulse s1. Reference numeral 9 outputs a phase difference signal that is the basis for calculating the second fractional time ΔT ₂ occurring at the time of the stop pulse s2. The configuration of the fractional time measuring circuits 8 and 9 is shown in detail in FIG. 11 is a microprocessor which receives signals from the counter 5 and fractional time measuring circuits 8 and 9;
This is used to perform calculations to calculate the time width.

In FIG. 1, 21 is a rising edge detection circuit, in which the start pulse s applied to the input terminal p3
1 or the rising edge of the stop pulse s2, and outputs a strobe signal st having a constant pulse width τ ₀ shown in FIG. 3D.

22 is VCO (voltage controlled oscillator)
The inverter a and the delay device b form a loop as shown in FIG. For example, by providing a variable capacitance diode _c2 and changing this capacitance with a voltage signal s6 applied from the outside,
It is designed to oscillate at a frequency that corresponds to this voltage. In this VCO22, the strobe signal st is “low”
If it is "high", it will oscillate, and if it is "high", it will stop oscillating. Then, it operates so that oscillation starts when it changes from "high" to "low".

A phase detector 23 receives the output signal s5 of the VCO 22 and the clock signal sr, and outputs a signal corresponding to the phase difference between these two signals. The output of this phase detector 23 is guided to a selection circuit 24.

Selection circuit 24 is controlled by signal s7 from flip-flop 27. For example, if this signal s7 is "low", the signal from the phase detector 23 is output as is to the next stage, and if it is "high", the output state of the phase detector 23 when this signal s7 is applied is held. It is then output to the next stage. The output of the selection circuit 24 is introduced into a loop filter 25, and the output signal s6 of this loop filter 25 is
Controls variable capacitance diode _c2 of VCO22.
This loop filter 25 is combined with the VCO 22.
It constitutes a PLL circuit and has an appropriate time constant for this PLL circuit. The output of the phase detector 23 is
The AD converter 26 converts the signal into a digital signal at high speed, and the microprocessor 11 in FIG. 2 performs calculations to be described later. flipflop 2
7 is set and reset by the signal s8 applied to the terminal p5.

The operation of the circuits of FIGS. 1 and 2 configured as described above will be explained.

The signal having the time width to be measured applied to the input terminal p1 is waveform-shaped by the input amplifier 1, and then
The signal is introduced into the control circuit 3 as a signal as shown in A in the figure. The control circuit 3 outputs a start pulse s1 and a stop pulse s2 as shown in FIG. 3B and C, respectively, at the rising edge and falling edge of the signal in FIG. 3A. In addition, the control circuit 3 introduces a clock signal from the clock generator 7, and the periods of the clock signals _C0 and Cn that occur after the start pulse s1 and stop pulse s2 are generated,
It has a gate circuit (not shown) which is open, and the gating clock signal s4 passing through this gate circuit is represented by H in FIG. This gating clock signal s4 is counted by the counter 5 (count number N), and then the microprocessor 11 performs the calculation of NT ₀ as shown in equation (1).

On the other hand, in the fractional time measuring circuit 8, the start pulse s1 is introduced, and the fractional time ΔT ₁ is determined by the following operation.
Outputs a phase difference signal that is the basis for calculation.

The operation for obtaining the phase difference signal that is the basis for calculating the fractional time will be described below, mainly with reference to FIG.

The VCO 22 is oscillated at a certain frequency by a delay device b. The phase detector 23 receives two introduced signals (clock signal sr and signal s from the VCO 22).
5) outputs a signal according to the phase difference. On the other hand, if the signal s7 from the flip-flop 27 is "low", the selection circuit 24 transmits the signal from the phase detector 23 to the next stage. Then, a signal corresponding to this phase difference becomes a voltage signal s6 via the loop filter 25, and controls the variable capacitance diode _c2 . Since feedback is applied so that this phase difference becomes zero, the phase of the signal s5 oscillated by the VCO 22 and the clock signal sr are in the same phase.

When the start pulse s1 is applied in this state, the rising edge detection circuit 21 outputs a strobe signal st having a constant pulse width τ ₀ as shown in FIG. 3D. As a result, the VCO 22 stops oscillating during the period of this pulse width τ ₀ . Then, when this strobe signal st disappears, VCO22 synchronizes with this.
starts oscillating again.

Incidentally, since the flip-flop 27 is inverted in synchronization with the generation of the strobe signal st, the signal s7 is at "high" level. Therefore, the selection circuit 24
Signal s5 and clock signal sr just before oscillation stops
Holds and outputs the value of the phase difference. This hold value is, in principle, the output signal s5 of the VCO22.
Since this is the value when strobe signal st and clock signal sr are in the same phase, the output signal of VCO 22, which oscillates again after strobe signal st disappears, is equal to the clock signal sr.
It has the same frequency as sr. That is, the phase of the re-oscillated output signal s5 in the VCO 22 has a phase difference of δ ₁ shown in FIG. 3 from the clock signal sr. here,
From the photo in FIG. 3, the phase shift amount δ ₁ is expressed by equation (2).

δ ₁ = τ ₁ + τ ₀ +T ₀ /2−T ₀ (2) where, T ₀ : Period of clock signal sr τ ₁ : Time difference between the start pulse generation and the previous rise of the clock signal τ ₁ = T ₀ - ΔT ₁ , so the first fractional time ΔT ₁
can be expressed as equation (3) by rewriting equation (2).

ΔT ₁ =τ ₀ −δ ₁ +T ₀ /2 (3) This phase shift amount δ ₁ is the output value of the phase detector 23, which is quickly converted into a digital value by the AD converter 26, The signal is sent to the microprocessor 11 as a signal s9.

Here, in equation (3), the pulse width τ ₀ of the strobe signal and the period T ₀ of the clock signal are known in advance, and the value of δ ₁ is known from the signal s9. , (3), the first fractional time ΔT ₁ can be calculated.

Next, when the signal representing the time width to be measured falls and a stop pulse s2 is generated at the timing shown in FIG. 3, s2 is applied to the fractional time measuring circuit 9. In this case, the phase shift amount δ ₂ of the output signal s5 of the VCO 22 is expressed by equation (4) from the beginning of FIG.

δ ₂ = τ ₂ + τ ₀ −T ₀ (4) τ ₂ : Time difference between the generation of the stop pulse and the previous rise of the clock signal Therefore, the second fractional time ΔT ₂ is expressed by equation (5). .

ΔT ₂ =τ ₀ −δ ₂ (5) In this case as well, since the value of the phase difference δ ₂ is known from the signal s9 as described above, by performing the calculation of equation (5) in the microprocessor 11, , a second fractional time ΔT ₂ can be calculated.

Note that the formula for calculating fractional time is (3) and (5).
The start pulse s
1. The timing at which the stop pulse s2 is generated differs depending on whether the clock signal is at a "high" level or a "low" level.

That is, if the start pulse s1 or the stop pulse s2 is generated when the clock signal sr is at the "high" level, the fractional time is calculated using equation (3). Conversely, if the occurrence occurs when the level is "low", the fractional time is calculated using equation (5).

Therefore, the microprocessor 11 can easily calculate (3 ) and (5) can be selected, and fractional time can be calculated correctly.

Note that the circuit for detecting this level information and the path for transmitting this information to the microprocessor 11 can be achieved by common sense means, so as shown in FIG.
In FIG. 2, the description thereof is omitted.

As a result of the above, in microprocessor 11, (1)
The time width Tx of the measurement target is further calculated by the formula
can be calculated.

In addition, after the start pulse s1 and stop pulse s2, in preparation for the measurement of the next fractional time, the VCO
The signal s5 at 22 must be in phase with the clock signal sr. Therefore, the terminal p
A reset signal s8 is applied to the phase detector 5 (eg, output from the microprocessor 11) to reset the flip-flop 27 and make the signal s7 "low" so that the signal from the phase detector 23 is transmitted to the next stage.

It should be noted that, as a result of changing the signal s7 from the flip-flop 27 as described above, if the hold is suddenly released, there is a possibility that the frequency will be greatly distorted and this will gradually return. Here, it is only necessary to return the phase without changing the frequency, so as shown in FIG. 6, a switch 33 is provided and normally connected to the contact h side.
Then, as mentioned above, only when returning the phase, contact g
Connect to. In the case of contact g, a value proportional to the phase difference (1/α) is added, and the phase difference can be corrected at high speed. Then, the coincidence detector 32 checks that the phase difference has disappeared, and if they match, the contact of the switch 33 is set to the h side. Subsequently, the hold of the selection circuit 24 is released by the reset signal s8. By doing so, the above problem can be solved.

Furthermore, by performing AD conversion multiple times and statistically processing the results, it is possible to improve the measurement accuracy of the phase differences δ ₁ and δ ₂ .

Further, by providing a low pass filter (not shown) in front of the AD converter 26, the nozzle can be cut off.

Furthermore, if the phase detector 23 is configured to detect the phase difference as a pulse width and convert it into a voltage value using, for example, an RC filter, it will take a time constant until the output becomes stable. Ripples also occur, causing errors. Therefore, by configuring the phase detector 23 as shown in FIG. 7, the above drawbacks can be solved. FIG. 7 is a diagram showing a specific example of the phase detector 23 in FIG.
is guided to a transducer 26. Moreover, FIG. 8 is a time chart of the circuit of FIG. 7. In FIG. 7, a phase discrimination circuit 41 discriminates the phase of the signal s5 from the VCO 22 and the clock signal sr, and controls switching of the switch 43 with a pulse width corresponding to the phase difference δ (see FIG. 8). As a result, the switch 43 outputs the signal s10 (see FIG. 8) to the next-stage section averaging circuit (comprised of an integrator 45, a sample-and-hold circuit 47, and a feedback resistor R). This sample and hold circuit 47 samples the output of the integrator 45 at the timing of the signal s11 (see FIG. 8) synchronized with the rising edge of the clock signal sr, and holds the sampled value during other periods.
In the time chart of FIG. 8, the phases of the signal s5 and the clock signal sr match until time _C0 .
In this case, both the signal s10 and the output signal s12 of the circuit of FIG. 7 are Ov.

Next, at time _C1 , when the signal s5 becomes delayed in phase by δ with respect to the clock signal sr, the output signal s10 of the switch 43 becomes a signal with a pulse width δ.

It is known that when the constant of the interval averaging circuit is AT ₀ /CR=1, the output follows the input at high speed, and the output signal s12 of the circuit in FIG. 7 becomes constant at the second sample (time C ₃ ). becomes. Note that A is the amplification degree of the amplifier of the sample-and-hold circuit 47, C is the capacitance of the integrator 45, R is the value of the feedback resistor, and T ₀ is the period of the clock signal.

In this way, by combining the phase discrimination circuit 41 and the interval averaging circuit as the phase detector 23 and obtaining a ripple-free phase difference voltage in a short time, high-speed and highly accurate AD conversion becomes possible.

C. “Effects of the Present Invention” As described above, according to the present invention, the following effects can be obtained.

Conventional devices require time for the main clock and vernier clock to coincide. Even if the operating speed of the AD converter becomes faster in the future than it is now, this time is a theoretically necessary time and there is no room for improvement.

On the other hand, in the device according to the present invention, the output of the phase detector 23 is directly AD-converted, and then the calculation is performed by a microcomputer or the like.
There are very high-speed methods, and for this reason, the present invention can operate at higher speeds than conventional means based on its operating principle.

Therefore, the time width can be measured at high speed and in real time.

Since the output of the phase detector 23 can be measured multiple times as necessary, by statistically processing the output, it is possible to measure fractional times with high accuracy.

In the time vernier method, a certain amount of time is absolutely necessary because the point where the phases of the main clock and the vernier clock match is detected. In the present invention, since the phase difference between the signal s5 of the VCO 22 and the clock signal sr is detected, this phase difference can be immediately output and fractional time can be measured in a short time. It takes a while, but
It has a wide range of applications, such as being able to measure the phase difference multiple times and perform statistical processing to improve measurement accuracy.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a fractional time measuring circuit which is a main part of the present invention, FIG. 2 is a block diagram of a time width measuring device according to the present invention, FIG. 3 is a time chart, and FIG. Figure 5 is a diagram illustrating the general time width measurement principle, Figure 5 is a diagram explaining the operation of the time vernier method, Figure 6 is a diagram showing another configuration example of the present invention, Figure 7 is a phase detector. FIG. 8 is a time chart of the circuit shown in FIG. 7. DESCRIPTION OF SYMBOLS 1... Input amplifier, 3... Control circuit, 5... Counter, 7... Clock generator, 8, 9... Fractional time measuring circuit, 11... Microprocessor, 2
1...Rise detection circuit, 22...VCO, 23
... Phase detector, 24 ... Selection circuit, 25 ... Loop filter, 26 ... AD converter, 27 ... Flip-flop, 30 ... Adder, 31 ... Attenuator, 32 ... Coincidence detector, 33 ...Switch.

Claims (1)

[Claims] 1. A control circuit capable of outputting a start pulse, a stop pulse, and a gating clock signal corresponding to the start and end points of the time width to be measured, and a counter that counts the gating clock signal. In a device for measuring a measured time width from a counter output and a so-called fractional time, a means for outputting a strobe signal having a constant pulse width in synchronization with a start pulse and a stop pulse, and a pulse width of the strobe signal. oscillation is stopped during the period of , and after the pulse of the strobe signal disappears, an oscillation means that performs oscillation operation at the period of the clock signal, and a phase detector that detects the phase difference between the output signal of the oscillation means and the clock signal. What is claimed is: 1. A time width measuring device comprising: a fractional time measuring circuit comprising: , which calculates a fractional time by calculating a fractional time based on a phase difference signal from the fractional time measuring circuit, and measures a measured time width.