JP2001313550A - Pulse delay control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse delay control circuit with high precision that can detect a phase difference without increasing the circuit scale. SOLUTION: The pulse delay control circuit that controls a 1st input signal being a clock signal and a 2nd input signal being a data signal to have a prescribed phase relation, is provided with a delay circuit 3 that gives a prescribed delay in correspondence to a control voltage to the 1st input signal, a time- voltage conversion circuit 9 that receives an output signal from the delay circuit 3 and the 2nd input signal and outputs a 1st voltage in correspondence to the time difference between both signals, a frequency detection circuit 8 that outputs a 2nd voltage in correspondence to the frequency of the 1st input signal, and a standard deviation arithmetic circuit 10 that receives that 1st voltage and the 2nd voltage, calculates a standard deviation of a phase difference between the 1st input signal and the 2nd input signal and calculates a control voltage of the delay circuit 3 on the basis of an arithmetic mean obtained during the arithmetic operation and the 1st input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pulse delay control circuit, and more particularly to a pulse delay control circuit that controls a clock signal and a data signal to maintain a predetermined phase relationship.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional pulse delay control circuit. Clock signals and data signals as shown in FIG. 7 are input to the input terminals 1 and 2, respectively. As the data signal, for example, there is a signal obtained by binarizing an RF signal read from an optical disk, and a clock signal is generated from this data signal. As shown in FIG. 7, the clock signal and the data signal require that the falling timing of the clock signal and the rising timing of the data signal match without any phase difference. The reason why the phase difference between the clock signal and the data signal is set as shown in FIG. 7 is to correctly measure the jitter of the two signals.

The clock signal is input to a delay circuit 3 whose delay amount changes arbitrarily according to a control voltage. The output of the delay circuit 3 and the data signal are input to the phase difference detection circuit 6, and a voltage corresponding to the phase difference is input to the control voltage generation circuit 5. The clock signal is also input to the frequency-voltage conversion circuit 4, converted into a voltage corresponding to the frequency, and input to the control voltage generation circuit 5. The control voltage generation circuit 5 generates a control voltage for controlling the delay amount of the delay circuit 3 by using the voltage supplied from the phase difference detection circuit 6 and the voltage supplied from the frequency-voltage conversion circuit 4, and generates the control voltage. Output to the delay circuit 3. Thus, the delay circuit 3,
Due to the feedback loop of the phase difference detection circuit 6 and the control voltage generation circuit 5, the clock signal can maintain a constant phase relationship regardless of the frequency of the data signal. The phase difference between the output of the delay circuit 3 and the data signal is measured by the jitter measuring circuit 7.

FIG. 8 shows the input / output characteristics of the frequency-to-voltage conversion circuit 4. An output voltage proportional to the frequency is obtained. FIG. 9 shows the phase difference between the clock signal and the data signal. In the case of FIG. 9A, the phase difference is such that the data signal advances with respect to the clock signal. In the case of FIG. 9B, there is a phase difference such that the data signal lags behind the clock signal. The phase difference between the clock signal and the data signal is detected by the phase difference detection circuit 6 and the output signal is input to the control voltage generation circuit 5. FIG. 10 shows the output characteristics of the phase difference detection circuit 6, and it can be seen that an output voltage according to the phase difference can be obtained.

FIG. 11 is a diagram showing the relationship between the output voltage of the control voltage generation circuit 5 and the delay amount of the delay circuit 3.
FIG. 12 is a circuit diagram showing an example of the delay circuit 3. Several stages of delay circuits composed of a varicap diode D and R, C, L are cascaded, and the capacitance of the varicap diode D changes by changing the control voltage applied to the varicap diode D. And LC
The delay amount of the clock signal changes depending on the circuit.

[0006]

With the speeding up of the optical disk, the period of the clock signal is reduced to 10 ns or less.
At this time, for example, if the phase difference between the clock signal and the data signal is to be suppressed to about 1%, the amount of delay must be controlled with a resolution of 100 ps or less. On the other hand, the control of the delay circuit having a variable frequency is a non-linear control, so that the configuration of the control voltage generation circuit 5 shown in FIG. 6 is complicated, and it is difficult to realize high precision. Further, if the accuracy of the phase difference detection circuit 6 is to be improved, the circuit scale is increased, and the cost is increased. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and provides a pulse delay control circuit that can realize high-accuracy pulse delay control without increasing the circuit scale even when the clock signal speeds up. The purpose is to do.

[0007]

According to the present invention, there is provided a pulse delay control circuit for controlling a first input signal as a clock signal and a second input signal as a data signal so as to maintain a predetermined phase relationship. A delay circuit that gives a predetermined delay amount according to a control voltage to the first input signal and outputs the delay signal, an output signal of the delay circuit, and the second input signal,
A time-voltage conversion circuit that outputs a first voltage value according to a time difference between the two signals, a frequency detection circuit that outputs a second voltage value according to the frequency of the first input signal; Inputting the second voltage value and calculating a standard deviation of a phase difference between the first input signal and the second input signal;
A standard deviation calculation circuit for calculating a control voltage value of the delay circuit from the arithmetic average value obtained during the calculation and the first input signal. In the pulse delay control circuit, the first voltage value can be input to the standard deviation calculation circuit via an AD converter. In the pulse delay control circuit, the control voltage value may be input to the delay circuit via a DA converter as the control voltage.

[0008]

FIG. 1 is a block circuit diagram showing an example of a pulse delay control circuit according to an embodiment of the present invention. In the circuit shown in FIG. 1, the clock signal is input to the frequency detection circuit 8 and its output is input to the standard deviation calculation circuit 10. The clock signal is delayed by a predetermined delay amount by the delay circuit 3 and input to the time-voltage conversion circuit 9, while the data signal is also input to the time-voltage conversion circuit 9. The time-voltage conversion circuit 9 outputs a voltage value according to the time difference between the two input signals. The output voltage from the time-voltage conversion circuit 9 is converted into a digital signal by the AD converter 11 and input to the standard deviation calculation circuit 10.

The frequency detection circuit 8 receives a clock signal, converts a voltage value corresponding to the frequency of the clock signal into a digital value, and outputs the digital value to the standard deviation calculation circuit 10. The standard deviation calculation circuit 10 is composed of a digital signal processing circuit (DSP) and a microcomputer, and performs an operation of calculating a standard deviation value of jitter from an arbitrary number of voltage values corresponding to the AD sampled time differences. At this time, the control voltage to the delay circuit 3 is calculated from the arithmetic average value and the clock frequency obtained during the calculation of the standard deviation value. Note that the arithmetic mean value obtained during the calculation of the standard deviation value in the standard deviation calculation circuit 10 is equivalent to the phase difference. The arithmetic average value calculated by the standard deviation calculation circuit 10 becomes an analog value by the DA converter 12, and this is given to the delay circuit 3 as a control voltage.

FIG. 4 is a waveform diagram for explaining the operation of the time-voltage conversion circuit 9. The clock signal delayed by passing through the delay circuit 3 and the data signal are input, and a phase difference signal corresponding to the phase difference is created. FIG. 5 is a circuit diagram showing an example of the time-voltage conversion circuit 9. The constant current source 9a, the switch 9b, and the capacitor 9e are connected in series and grounded. The connection point between the switch 9b and the capacitor 9e is connected to the non-inverting input terminal of the operational amplifier 9d, and the inverting input terminal is connected to the output terminal. Further, a connection point between the switch 9b and the capacitor 9e is grounded via the switch 9c. The switches 9b and 9c are driven by the phase difference signal and the discharge signal shown in FIG. 4, and the switches close when each signal becomes high level. By performing such control, an output is obtained at a timing as shown in FIG. The output obtained here is A
It is sampled by the D converter 11 and input to the standard deviation calculation circuit 10.

FIG. 2 is a circuit diagram showing a configuration example of the frequency detection circuit 8. The frequency dividing circuit 8a, the crystal oscillator 8b, and the counter 8c are configured as shown in FIG. The output of the counter 8c is output to the standard deviation calculation circuit 10. When a clock signal, a frequency-divided output, and a crystal oscillator output as shown in FIG. 2B are provided, the counter 8c counts these, and counts the count value to the standard deviation calculation circuit 10.
Output to

FIG. 3 is a circuit diagram showing another configuration example of the frequency detection circuit 8. As shown in FIG. In the example shown in FIG. 3, the frequency-voltage conversion circuit 4 is the same as the frequency-voltage conversion circuit 4 shown in FIG. 6, and an AD converter 8d. Therefore, FIG.
Is converted into a digital value by the AD converter 8d, and the standard deviation calculating circuit 10
Will be output to

As described above, in the present invention, simplification of the phase difference detection circuit is realized by sharing the standard deviation calculation necessary for measuring the jitter as the phase difference detection circuit. Also,
The delay amount of the delay circuit 3 is digitally calculated by a microcomputer constituting the standard deviation calculation circuit 10, and the control according to the delay amount is also calculated by a digital value.

[0014]

As described above, according to the present invention, by providing the standard deviation value calculation circuit including the microcomputer and the DSP, a value equivalent to the phase difference detection circuit is obtained. Was unnecessary. Therefore, the need for a conventional control voltage generation circuit is eliminated. Since the control voltage of the delay circuit is calculated by the microcomputer, highly accurate calculation can be performed, and complicated control can be accurately performed even in an unstable state such as when a signal is input or a signal is lost. . Also, in the conventional circuit, the phase was changed regardless of the jitter calculation, so the change during measurement could also cause jitter,
In the present invention, since the calculation and the phase change are synchronized, a stable jitter measurement can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a pulse delay control circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of the frequency detection circuit 8 shown in FIG.

FIG. 3 is a diagram showing another configuration example of the frequency detection circuit 8.

FIG. 4 is a waveform chart for explaining the operation of the time-voltage conversion circuit 9;

FIG. 5 is a diagram for explaining the configuration and operation of a time-voltage conversion circuit 9;

FIG. 6 is a block diagram showing an example of a conventional pulse delay control circuit.

FIG. 7 is a waveform chart showing a relationship between a clock signal and a data signal supplied to a pulse delay control circuit.

FIG. 8 is a diagram showing input / output characteristics of the frequency-voltage conversion circuit 4.

FIG. 9 is a waveform chart showing a phase difference relationship between a clock signal and a data signal.

FIG. 10 is a diagram for explaining the operation of the phase difference detection circuit 6.

FIG. 11 is a diagram for explaining the operation of the control voltage generation circuit 5;

FIG. 12 is a diagram showing a specific circuit example of a delay circuit 3;

[Explanation of symbols]

 Reference Signs List 3 delay circuit 8 frequency detection circuit 9 time-voltage conversion circuit 10 standard deviation calculation circuit 11 AD converter 12 DA converter

Claims (3)

[Claims] A first input signal that is a clock signal;
A pulse delay control circuit that controls a second input signal, which is a data signal, to maintain a predetermined phase relationship, a delay circuit that applies a predetermined delay amount according to a control voltage to the first input signal and outputs the first input signal. A time-voltage conversion circuit that receives an output signal of the delay circuit and the second input signal and outputs a first voltage value corresponding to a time difference between the two signals; A frequency detection circuit that outputs a second voltage value corresponding to the first voltage value and the second voltage value;
The standard deviation of the phase difference between the input signal and the second input signal is calculated, and the arithmetic average obtained during the calculation and the first deviation are calculated.
And a standard deviation calculating circuit for calculating a control voltage value of the delay circuit from the input signal of the pulse delay control circuit. 2. The pulse delay control circuit according to claim 1, wherein the first voltage value is input to the standard deviation calculation circuit via an AD converter. 3. The delay control circuit according to claim 1, wherein the control voltage value is input to the delay circuit via a DA converter as the control voltage.