JP6891528B2 - Circuit devices, physical quantity measuring devices, electronic devices and mobile objects - Google Patents

Description

The present invention relates to a circuit device, a physical quantity measuring device, an electronic device, a mobile body, and the like.

A phase difference detection type time digital converter that detects the phase difference between a transmission signal and a reception signal and measures TOF (Time Of Flight) based on the phase difference is known. In the conventional phase difference detection method, the phase difference between the transmitted signal and the received signal is converted into an electric charge by a sensor (the amount of electric charge corresponding to the integrated value of the electric charge is accumulated), and the phase difference is detected based on the electric charge. ..

For example, in Patent Documents 1 to 3, light is emitted toward a measurement target, the reflected light from the measurement target is received by the sensor, and the amount of charge corresponding to the phase difference between the light emission timing and the light reception timing is accumulated in the sensor. A method of measuring the distance to be measured based on the amount of charge read from is disclosed.

Japanese Unexamined Patent Publication No. 2012-93256 Japanese Unexamined Patent Publication No. 2008-164496 Japanese Unexamined Patent Publication No. 2011-53216

In the above-mentioned conventional technique, since the received light signal obtained based on the light emission timing is converted into an electric charge (integral value) by the sensor and the distance is measured, it is necessary for the time digital converter to spontaneously generate the transmission signal. Therefore, it is not possible to measure the time between two signals input from the outside of the time-digital conversion circuit at an arbitrary timing.

The present invention has been made to solve at least a part of the above problems, and can be realized as the following forms or embodiments.

One aspect of the present invention includes a first phase difference signal output unit, which receives a first signal and outputs a first phase difference signal representing the phase difference between the reference clock signal and the first signal, and a second phase difference signal output unit. A second phase difference signal output unit that inputs the signal of the above and outputs a second phase difference signal representing the phase difference between the reference clock signal and the second signal, the first phase difference signal, and the first phase difference signal. It relates to a circuit apparatus including a measuring unit for measuring a time difference between the first signal and the second signal based on the phase difference signal of 2.

According to one aspect of the present invention, a first phase difference signal representing the phase difference between the reference clock signal and the first signal is output, and a second phase difference representing the phase difference between the reference clock signal and the second signal. A signal is output. As a result, the phase difference between the reference clock signal and the first signal can be detected based on the first signal (so-called non-spontaneous) input at an arbitrary timing with respect to the reference clock signal, and the reference clock signal can be detected. The phase difference between the reference clock signal and the second signal can be detected based on the second signal input at an arbitrary timing. Then, the time difference between the first signal and the second signal can be measured based on the first phase difference signal and the second phase difference signal representing these phase differences. In this way, in one aspect of the invention, the time between two non-spontaneous signals can be measured.

Further, in one aspect of the present invention, the first phase difference signal output unit performs integration processing based on the reference clock signal and the first signal, outputs the first phase difference signal, and outputs the first phase difference signal. The phase difference signal output unit of 2 may output the second phase difference signal by performing integration processing based on the reference clock signal and the second signal.

In this way, the first phase difference signal representing the phase difference between the reference clock signal and the first signal can be output by performing the integration process based on the reference clock signal and the first signal. Further, by performing the integration process based on the reference clock signal and the second signal, it is possible to output a second phase difference signal representing the phase difference between the reference clock signal and the second signal.

Further, in one aspect of the present invention, the first phase difference signal output unit generates a first pulse signal having a pulse width corresponding to the pulse width of the reference clock signal based on the first signal. The second phase difference signal output unit has one pulse signal generation unit, and the second phase difference signal output unit generates a second pulse signal having a pulse width corresponding to the pulse width of the reference clock signal based on the second signal. It may have a second pulse signal generator to generate.

In this way, the reference clock signal can be integrated in the integration period defined by the first pulse signal, and the first phase difference signal can be generated from the integrated value. Further, the reference clock signal can be integrated in the integration period defined by the second pulse signal, and the second phase difference signal can be generated by the integrated value. That is, when the first signal and the second signal are input at an arbitrary timing by generating the first pulse signal from the first signal and generating the second pulse signal from the second signal. Even if it is, the integration process becomes possible and the phase difference can be detected.

Further, in one aspect of the present invention, the first phase difference signal output unit has a first integration processing unit that performs integration processing based on the reference clock signal and the first pulse signal, and the second The phase difference signal output unit may have a second integration processing unit that performs integration processing based on the reference clock signal and the second pulse signal.

In this way, the first integration processing unit performs integration processing based on the reference clock signal and the first pulse signal, so that the first phase difference signal representing the phase difference between the reference clock signal and the first signal. Can be output. Further, the second integration processing unit performs integration processing based on the reference clock signal and the second pulse signal, so that a second phase difference signal representing the phase difference between the reference clock signal and the second signal can be output.

Further, in one aspect of the present invention, the first pulse signal generation unit has a first delay circuit, and the first phase difference signal output unit sets the delay time of the first delay circuit. The second delay control circuit for setting the delay time corresponding to the pulse width of the reference clock signal, the second pulse signal generation unit has the second delay circuit, and the second phase difference. The signal output unit may have a second delay control circuit that sets the delay time of the second delay circuit to a delay time corresponding to the pulse width of the reference clock signal.

In this way, the first pulse signal having a pulse width corresponding to the pulse width of the reference clock signal can be generated by using the first delay circuit set to the delay time corresponding to the pulse width of the reference clock signal. .. Further, a second pulse signal having a pulse width corresponding to the pulse width of the reference clock signal can be generated by using the second delay circuit set to the delay time corresponding to the pulse width of the reference clock signal.

Further, in one aspect of the present invention, the first phase difference signal output unit outputs the reference clock signal to the first delay circuit in the pulse width measurement mode, and the first phase difference detection mode. The pulse signal generation unit has a first selector that outputs the first signal, and the second phase difference signal output unit has the reference clock signal in the second delay circuit in the pulse width measurement mode. In the phase difference detection mode, the second pulse signal generation unit may have a second selector that outputs the second signal.

In this way, in the pulse width measurement mode, the delay time of the first delay circuit is set by the first delay circuit and the first delay control circuit, and the second delay circuit and the second delay control circuit set the delay time. The delay time of the delay circuit of 2 can be set. Then, in the phase difference detection mode, the first pulse signal generation unit generates the first pulse signal from the first signal using the first delay circuit, and the second pulse signal generation unit is the second delay circuit. Can be used to generate a second pulse signal from the second signal and detect the phase difference based on these pulse signals.

Further, in one aspect of the present invention, the circuit device includes a clock signal generation unit that generates first to nth clock signals (n is an integrator of 2 or more) having different phases from each other based on the reference clock signal. The first phase difference signal output unit has the first to nth clock signals and the first to nth integrators that perform integrator processing based on the first signal, and the second phase difference. The signal output unit may have an n + 1 to 2n integrator that performs an integrating process based on the first to nth clock signals and the second signal.

In this way, the characteristics of the first to nth integrated values having different phases from each other can be obtained. As a result, n integral values based on n characteristics having different phases can be obtained with respect to the input phase difference. The integration process may have non-linearity due to variations in the characteristics of the integrator, etc., which may cause non-linearity between the input phase difference and the output phase difference. In this regard, according to one aspect of the present invention, the non-linearity between the input phase difference and the output phase difference can be reduced by, for example, averaging n integrated values to obtain the phase difference.

Further, in one aspect of the present invention, the measuring unit has a selector for selecting one of the output signal of the first to nth integrators and the output signal of the n + 1 to 2n integrators, and the selector. Based on the A / D conversion circuit that A / D converts the signal, the output signal of the first to nth integrators that have been A / D converted, and the output signal of the n + 1 to 2n integrators. It may have a processing unit for obtaining the time difference.

In this way, the output signal of the first to nth integrators and the output signal of the n + 1 to 2n integrators can be A / D converted into time division. As a result, the circuit scale can be saved. Further, by performing such A / D conversion, the time difference can be obtained based on the output signal (integrated value) of the integrator by digital signal processing.

Further, in one aspect of the present invention, the circuit device includes a counter that counts the number of clocks of the reference clock signal from the activation of the first signal to the activation of the second signal. The measuring unit may measure the time difference between the first signal and the second signal based on the count value of the counter, the first phase difference signal, and the second phase difference signal.

In the conventional phase difference detection method, it is difficult to widen the dynamic range because the integration process is performed by the sensor. In this regard, according to one aspect of the present invention, the number of clocks of the reference clock signal from the activation of the first signal to the activation of the second signal is counted, and the count value is used to count the number of clocks. The time difference between the first signal and the second signal is measured. Thereby, even when the phase difference between the first signal and the second signal is larger than one cycle of the reference clock signal, the phase difference can be detected. This makes it possible to measure a wide dynamic range.

Further, another aspect of the present invention relates to a physical quantity measuring device including the circuit device according to any one of the above.

Yet another aspect of the present invention relates to an electronic device including the circuit device according to any of the above.

Yet another aspect of the invention relates to a mobile body comprising the circuit device according to any of the above.

A first configuration example of the circuit device of this embodiment. The figure explaining the method of time difference measurement in this embodiment. A timing chart for explaining the operation of the first phase difference signal output unit. The figure which shows the characteristic of the integrated value. A second configuration example of the circuit device of this embodiment. A timing chart for explaining the operation of the circuit device of the second configuration example. A detailed configuration example of the circuit device of this embodiment. The flowchart explaining the operation of the circuit apparatus of the detailed configuration example. The figure explaining the operation of the 1st phase difference signal output part in a pulse width measurement mode. The figure explaining the operation of the 1st phase difference signal output part in the phase difference detection mode. A detailed configuration example of the first integration processing unit. A timing chart of the clock signal generated by the clock signal generator. The figure which shows the characteristic of the integral value of the integral processing by a polyphase clock. The figure which shows the characteristic of the integral value of the integral processing by a polyphase clock. The figure which shows the characteristic of the integral value of the integral processing by a polyphase clock. Detailed configuration example of the measuring unit. Detailed configuration example of the integrator. A timing chart that illustrates the operation of the integrator. The figure explaining the variation of the characteristic of the integrated value among the integrators. An example of the characteristics of the output phase difference with respect to the input phase difference. The figure explaining the variation correction of an integrator. Configuration example of physical quantity measuring device. Configuration example of electronic equipment. Configuration example of a moving body.

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as a means for solving the present invention. Not necessarily.

1. 1. First Configuration Example As described above, in the conventional phase difference detection method, the signal is integrated by the sensor, and the output signal of the sensor is the phase difference signal. This method is used for, for example, three-dimensional measurement. That is, the distance is measured at each pixel using the two-dimensional sensor, and the three-dimensional information of the measurement target is acquired.

Since the phase difference detection method measures the phase difference (time difference) between the transmitted signal and the received signal, it can be considered as a kind of time digital converter. However, since it is necessary to spontaneously generate a transmission signal and it is converted into a phase difference by a sensor, its use as a time digital converter is limited. For example, it is difficult to measure the time difference between two non-spontaneous signals such as the delay difference between two signal paths and the phase difference detection in the PLL by the conventional phase difference detection method.

FIG. 1 is a first configuration example of the circuit device of the present embodiment. The circuit device 100 includes a first phase difference signal output unit 10 (first phase difference signal output circuit), a second phase difference signal output unit 20 (second phase difference signal output circuit), and a measurement unit 30 (measurement). Circuit) is included. The present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting a part of the constituent elements or adding other constituent elements are possible. For example, in FIG. 1, the reference clock signal RFCK is input to the phase difference signal output units 10 and 20, but the present invention is not limited to this, and the clock signal generated with the reference clock signal RFCK as the reference for the phase or frequency is the phase difference. It may be input to the signal output units 10 and 20.

The circuit device 100 of FIG. 1 is a time digital conversion circuit that converts the time difference between the transition timings of the first signal SG1 and the second signal SG2 into a digital value (time difference data TQ).

Specifically, the first phase difference signal output unit 10 receives the first signal SG1 and outputs the first phase difference signal PH1 representing the phase difference between the reference clock signal RFCK and the first signal SG1. .. The second phase difference signal output unit 20 receives the second signal SG2 and outputs the second phase difference signal PH2 representing the phase difference between the reference clock signal RFCK and the second signal SG2. The measuring unit 30 measures the time difference between the transition timings of the first signal SG1 and the second signal SG2 based on the first phase difference signal PH1 and the second phase difference signal PH2. The measuring unit 30 outputs the time difference data TQ representing the measured time difference.

FIG. 2 is a diagram illustrating a method of measuring the time difference in the present embodiment. In the following, the case where the transition timing of each signal is the rising edge of the signal will be described as an example, but the transition timing of the signal is not limited to this. That is, the transition timing may be any timing at which the signal level changes.

The first phase difference signal output unit 10 generates a first phase difference signal PH1 corresponding to the phase difference between the rising edge of the reference clock signal RFCK and the rising edge of the first signal SG1. For example, assume that one cycle of the reference clock signal RFCK is 360 degrees and the phase difference is 60 degrees. The second phase difference signal output unit 20 generates a second phase difference signal PH2 corresponding to the phase difference between the rising edge of the reference clock signal RFCK and the rising edge of the second signal SG2. For example, suppose the phase difference is 150 degrees. The measuring unit 30 obtains the phase difference between the rising edge of the first signal SG1 and the rising edge of the second signal SG2 from the two phase difference signals PH1 and PH2. Specifically, the phase difference (60 degrees) is obtained from the first phase difference signal PH1, the phase difference (150 degrees) is obtained from the second phase difference signal PH2, and the difference between the two phase differences is 150 degrees -60 degrees. = 90 degrees is calculated. For example, the measuring unit 30 outputs a digital value representing a phase difference of 90 degrees as time difference data TQ. Alternatively, when one cycle of the reference clock signal RFCK is TRF, the phase difference of 90 degrees is converted into the time difference TDF = (90 degrees / 360 degrees) × TRF, and the time difference data TQ representing the time difference TDF is output.

Various signals can be assumed as the first signal SG1 and the second signal SG2. For example, the signals SG1 and SG2 may be a start signal and a stop signal in the TOF type distance measuring sensor. In this case, the time from the first signal SG1 (start signal) input first to the second signal SG2 (stop signal) input later is measured. Alternatively, the signals SG1 and SG2 are a reference signal (for example, a reference clock, a time pulse, etc.) and a signal to be synchronized with the reference signal (for example, a timing signal, a clock signal, etc. that are synchronized with the reference clock or the time pulse). May be good. Alternatively, it may be a signal that has passed through the first signal path (delay signal) and a signal that has passed through the second signal path (delay signal). In these examples, the context of the first signal SG1 and the second signal SG2 is not determined. For example, when the first signal SG1 and the second signal SG2 are input in this order, a positive time difference TDF is output, and when the second signal SG2 and the first signal SG1 are input in this order, the time difference TDF is output. Outputs a negative time difference TDF.

The phase difference signal (each of PH1 and PH2) is a signal whose signal value corresponds to a phase difference of 0 to 360 degrees, for example, a signal whose phase difference of 0 to 360 degrees corresponds to 1: 1. Is. For example, the phase difference signal is a combination of phase difference sine and cosine, or a combination of signals similar to them (for example, PHQ, PHI in FIG. 4). The phase difference signal is not limited to this, and any signal that can specify the phase difference from the phase difference signal may be used.

According to the present embodiment, the phase difference between the reference clock signal RFCK and the first signal SG1 is detected, the phase difference between the reference clock signal RFCK and the second signal SG2 is detected, and the first is based on the phase difference. The time difference between the transition timings of the first signal SG1 and the second signal SG2 is measured. Thereby, even when the time digital conversion circuit does not spontaneously generate the first signal SG1 (for example, the start signal), the time difference between the transition timings of the first signal SG1 and the second signal SG2 can be measured. Further, it can be applied to various applications as a time digital conversion circuit for measuring the time difference between two signals, not limited to the TOF type ranging sensor as in the conventional phase difference detection method.

Further, in the present embodiment, the first phase difference signal output unit 10 performs integration processing based on the reference clock signal RFCK and the first signal SG1 to output the first phase difference signal PH1. The second phase difference signal output unit 20 performs integration processing based on the reference clock signal RFCK and the second signal SG2, and outputs the second phase difference signal PH2.

FIG. 3 is a timing chart illustrating the operation of the first phase difference signal output unit. Although the first phase difference signal output unit 10 will be described here as an example, the same operation is performed for the second phase difference signal output unit 20.

The first phase difference signal output unit 10 generates the first pulse signal PSG1 from the first signal SG1. The rising edge (transition timing) of the first signal SG1 and the first pulse signal PSG1 has the same timing, and the pulse width TPS of the first pulse signal PSG1 is the pulse width TH (high level) of the reference clock signal RFCK. Period) is the same. The first phase difference signal output unit 10 integrates the reference clock signal RFCK during the integration period in which the first pulse signal PSG1 is active (high level, first logic level). Specifically, during the integration period, the negative signal level is integrated during the period when the reference clock signal RFCK is low level TAM, and the positive signal level is integrated during the period TAP when the reference clock signal RFCK is high level, and the integrated value PHI. (Signal) is output. The integrated negative signal level and positive signal level are signal levels with the same absolute value. Further, the first phase difference signal output unit 10 integrates the clock signal RFCK', which is 90 degrees out of phase with the reference clock signal RFCK, in the integration period. Specifically, in the integration period, the negative signal level is integrated in the period TBM where the clock signal RFCK'is low level, and the positive signal level is integrated in the period TBP when the clock signal RFCK' is high level, and the integrated value PHQ (Signal) is output. The first phase difference signal output unit 10 outputs the integrated values PHI and PHQ as the first phase difference signal PH1.

FIG. 4 is a diagram showing the characteristics of the integrated value. The upper limit of the range in which the integrated value changes is + VP, and the lower limit is -VP. The integrated value PHI has the characteristics of a pseudo cosine wave. Specifically, it is a triangular wave having the same phase as the cosine wave, and is a waveform obtained by linearly interpolating (straight line approximation) between the vertices of the cosine wave (0 degrees, 180 degrees, 360 degrees) and the zero crossing point (90 degrees, 270 degrees). Is. Further, the integrated value PHQ has a pseudo sine wave characteristic. Specifically, it is a triangular wave having the same phase as the sine wave, and is a waveform obtained by linearly interpolating (straight line approximation) between the zero cross point (0 degree, 180 degree, 360 degree) and the apex (90 degree, 270 degree) of the sine wave. Is. Since the angle (phase difference) can be uniquely determined in the range of 0 degrees to 360 degrees with respect to the sine and cosine values, the phase difference can be determined from the integrated values PHI and PHQ. For example, when the integral value (PHI, PHQ) = (-VP / 2, + VP / 2) as shown in FIG. 4, the phase difference can be determined to be 135 degrees.

By performing the integration process based on the reference clock signal RFCK and the first signal SG1 in this way, the first phase difference signal PH1 representing the phase difference between the reference clock signal RFCK and the first signal SG1 can be output. Similarly, by performing the integration process based on the reference clock signal RFCK and the second signal SG2, the second phase difference signal PH2 representing the phase difference between the reference clock signal RFCK and the second signal SG2 can be output.

Further, in the present embodiment, the first phase difference signal output unit 10 generates the first pulse signal PSG1 of the pulse width TPS corresponding to the pulse width TH of the reference clock signal RFCK based on the first signal SG1. It has a first pulse signal generation unit (first pulse signal generation unit 40 in FIG. 7). The second phase difference signal output unit 20 generates a second pulse signal PSG2 having a pulse width corresponding to the pulse width TH of the reference clock signal RFCK based on the second signal SG2. It has (the second pulse signal generation unit 70 of FIG. 7).

In this way, the first phase difference signal PH1 can be generated by integrating the reference clock signal RFCK in the integration period (TPS in FIG. 3) defined by the first pulse signal PSG1. Further, by integrating the reference clock signal RFCK in the integration period defined by the second pulse signal PSG2, the second phase difference signal PH2 can be generated. That is, by generating the first pulse signal PSG1 from the first signal SG1 and generating the second pulse signal PSG2 from the second signal SG2, the first signal SG1 and the second signal SG2 are externally generated. Even when it is input, integration processing is possible and the phase difference can be detected.

Further, in the present embodiment, the first phase difference signal output unit 10 is a first integration processing unit (first integration processing unit in FIG. 7) that performs integration processing based on the reference clock signal RFCK and the first pulse signal PSG1. 60). The second phase difference signal output unit 20 has a second integration processing unit (second integration processing unit 90 in FIG. 7) that performs integration processing based on the reference clock signal RFCK and the second pulse signal PSG2.

In this way, integration processing based on the reference clock signal RFCK and the first pulse signal PSG1 can be performed, and the first phase difference signal PH1 representing the phase difference between the reference clock signal RFCK and the first signal SG1 can be output. .. Further, the integration process based on the reference clock signal RFCK and the second pulse signal PSG2 can be performed to output the second phase difference signal PH2 representing the phase difference between the reference clock signal RFCK and the second signal SG2.

Further, in the present embodiment, the first pulse signal generation unit has a first delay circuit (first delay circuit 41 in FIG. 7). The first phase difference signal output unit 10 sets the delay time of the first delay circuit to the delay time corresponding to the pulse width TH of the reference clock signal RFCK (the first delay control circuit of FIG. 7). It has a delay control circuit 50). Then, a first DLL (Delay Locked Loop) circuit (first DLL circuit 130 in FIG. 7) is configured including the first delay circuit and the first delay control circuit. The second pulse signal generation unit has a second delay circuit (second delay circuit 71 in FIG. 7). The second phase difference signal output unit 20 sets the delay time of the second delay circuit to the delay time corresponding to the pulse width TH of the reference clock signal RFCK (second delay control circuit of FIG. 7). It has a delay control circuit 80). Then, a second DLL (Delay Locked Loop) circuit (second DLL circuit 140 in FIG. 7) is configured including the second delay circuit and the second delay control circuit.

In this way, the first pulse signal of the pulse width TPS corresponding to the pulse width TH of the reference clock signal RFCK is provided by the first delay circuit set to the delay time corresponding to the pulse width TH of the reference clock signal RFCK. PSG1 can be generated. Further, the second delay circuit set to the delay time corresponding to the pulse width TH of the reference clock signal RFCK can generate the second pulse signal PSG2 having the pulse width corresponding to the pulse width TH of the reference clock signal RFCK.

Further, in the present embodiment, the first phase difference signal output unit 10 has a first selector (first selector 15 in FIG. 7). The first selector outputs the reference clock signal RFCK to the first delay circuit in the pulse width measurement mode (step S1 and FIG. 9 of FIG. 8), and outputs the reference clock signal RFCK to the phase difference detection mode (step S2 and FIG. 10 of FIG. 8). Then, the first signal SG1 is output to the first pulse signal generation unit. The second phase difference signal output unit 20 has a second selector (second selector 25 in FIG. 7). The second selector outputs the reference clock signal RFCK to the second delay circuit in the pulse width measurement mode, and outputs the second signal SG2 to the second pulse signal generation unit in the phase difference detection mode.

For example, the pulse width measurement mode is set intermittently. That is, the first period in which the pulse width measurement mode is set and the second period in which the phase difference detection mode is set are alternately repeated, and the phase difference is detected (measurement of the time difference) in the second period. It is said. The second period corresponds to a waiting period for waiting for input of the first signal SG1 and the second signal SG2. When the first signal SG1 and the second signal SG2 are input during this standby period, the time difference is measured. One measurement may be made during one second period, or multiple measurements may be made.

In this way, in the pulse width measurement mode, the delay time of the first delay circuit is set by the first delay circuit and the first delay control circuit, and the second delay circuit and the second delay control circuit set the delay time. The delay time of the delay circuit of 2 can be set. Then, in the phase difference detection mode, the first pulse signal generation unit generates the first pulse signal PSG1 based on the first signal SG1, and the second pulse signal generation unit generates the first pulse signal SG2 based on the second signal SG2. 2 pulse signals PSG2 can be generated, and the phase difference can be detected (time difference is measured) based on these pulse signals.

Further, in the present embodiment, the circuit device 100 is a clock signal generation unit that generates first to nth clock signals (clock signals CKAI1, CKBI1, CKCI1 in FIG. 12) having different phases from each other based on the reference clock signal RFCK. (Clock signal generation unit 120 in FIG. 7) is included. The first phase difference signal output unit 10 uses the first to nth integrators (integrators 61 to 63 in FIG. 11) that perform integration processing based on the first to nth clock signals and the first signal SG1. Have. The second phase difference signal output unit 20 has n + 1 to 2n integrators that perform integration processing based on the first to nth clock signals and the second signal SG2.

Specifically, the phase of the first to nth clock signals is in increments of 360 degrees / n with reference to the reference clock signal RFCK. For example, in FIG. 12, n = 3, and the phases of the first to third clock signals (CKAI1, CKBI1, CKCI1) are in 360 degree / 3 = 120 degree increments. The clock signals (CKAQ1, CKBQ1, CKCQ1) whose phase is 90 degrees different from that of the first to third clock signals (CKAI1, CKBI1, CKCI1), and the clock signals (CKAI2, CKBI2, CKCI2, CKAQ2) whose phase is 180 degrees different from them. , CKBQ2, CCKQ2), it becomes a multi-phase clock of 360 degrees / 12 = 30 degrees.

In this way, as will be described later in FIGS. 13 to 15, the characteristics (PHAI1, PHBI1, PHCI1) of the first to nth integrated values having different phases from each other can be obtained. As a result, n integral values based on n characteristics having different phases can be obtained with respect to the input phase difference. The integration process may have non-linearity due to variations in the characteristics of the integrator, etc., which may cause non-linearity between the input phase difference and the output phase difference. In this regard, according to the present embodiment, the non-linearity between the input phase difference and the output phase difference can be reduced by, for example, averaging n integrated values to obtain the phase difference.

Further, in the present embodiment, the measuring unit 30 includes a selector (selector 31 in FIG. 16) for selecting one of the output signal of the first to nth integrators and the output signal of the n + 1 to 2n integrators. The A / D conversion circuit (A / D conversion circuit 32 in FIG. 16) that A / D converts the signal from the selector, the output signal of the first to nth integrators that have been A / D converted, and the n + 1 to 1st It has a processing unit (processing unit 33 in FIG. 16) for obtaining a time difference based on the output signal of the 2n integrator.

In this way, the output signal of the first to nth integrators and the output signal of the n + 1 to 2n integrators can be A / D converted into time division. As a result, the circuit scale can be saved. Further, by performing such A / D conversion, the time difference can be obtained based on the output signal (integrated value) of the integrator by digital signal processing. Further, in digital signal processing, various processes such as correction of variation of the integrator, which will be described later in FIGS. 19 to 21, can be realized with a simple configuration.

2. Second Configuration Example FIG. 5 is a second configuration example of the circuit device of the present embodiment. In FIG. 5, the circuit device 100 further includes a counter 110.

The counter 110 counts the number of clocks of the reference clock signal RFCK from the activation of the first signal SG1 to the activation of the second signal SG2. Then, the measuring unit 30 measures the time difference between the first signal SG1 and the second signal SG2 based on the count value CNQ of the counter 110, the first phase difference signal PH1 and the second phase difference signal PH2.

FIG. 6 is a timing chart illustrating the operation of the circuit device of the second configuration example. The counter 110 detects that the first signal SG1 has become active and starts the counting operation, and detects that the second signal SG2 has become active and stops the counting operation. In the example of FIG. 6, since one clock of the reference clock signal RFCK is input between the rising edge of the first signal SG1 and the rising edge of the second signal SG2, the count value CNQ = 1.

The counting operation may be started by detecting that the first pulse signal PSG1 has become active, and may stop the counting operation by detecting that the second pulse signal PSG2 has become active.

As shown in FIG. 6, it is assumed that the phase difference between the first signal SG1 and the reference clock signal RFCK is detected as 60 degrees, and the phase difference between the second signal SG2 and the reference clock signal RFCK is detected as 270 degrees. In this case, the measuring unit 30 determines the phase difference between the first signal SG1 and the second signal SG2 as −60 degrees + (CNQ × 360 degrees) + 270 degrees. Since CNQ = 1 in FIG. 6, the phase difference is 570 degrees.

When the second signal SG2 is input before the first signal SG1, the counter 110 detects that the second signal SG2 has become active and starts the counting operation, and the first signal SG2 is started. Detects that the signal SG1 has become active and stops the counting operation. In this case, the sign of the count value CNQ is made negative.

In the conventional phase difference detection method, since the integration process is performed by the sensor, it is difficult to widen the dynamic range (measureable phase difference, distance, and time range). In this regard, according to the present embodiment, even when the phase difference between the first signal SG1 and the second signal SG2 is larger than 360 degrees (the time difference is larger than one cycle of the reference clock signal RFCK), the phase difference Can be detected. This makes it possible to measure a wide dynamic range.

3. 3. Detailed Configuration Example FIG. 7 is a detailed configuration example of the circuit device of the present embodiment. The circuit device 100 includes a first phase difference signal output unit 10, a second phase difference signal output unit 20, a measurement unit 30, and a clock signal generation unit 120 (clock signal generation circuit). The present embodiment is not limited to the configuration shown in FIG. 7, and various modifications such as omitting a part of the constituent elements or adding other constituent elements (for example, the counter 110 in FIG. 5) can be performed. It is possible.

The clock signal generation unit 120 generates clock signals RFCK2, CKI, and CKQ from the clock signal MCK (master clock signal). The clock signal RFCK2 is a clock signal having a frequency twice that of the reference clock signal RFCK. The clock signals CKI and CKQ are clock signals (multiphase clock signals) whose phase is shifted from the reference clock signal RFCK. The clock signal MCK is a clock signal having a frequency higher than that of the reference clock signal RFCK, and is a clock signal generated inside the circuit device 100 or a clock signal supplied from the outside of the circuit device 100. For example, the clock signal generation unit 120 is composed of a frequency divider and the like.

The first phase difference signal output unit 10 includes a first selector 15, a first DLL circuit 130, and a first integration processing unit 60 (first integration processing circuit). The first DLL circuit 130 includes a first pulse signal generation unit 40 (first pulse signal generation circuit) and a first delay control circuit 50.

The first selector 15 selects either the first signal SG1 or the clock signal RFCK2, and outputs the selected signal SLQ1. The first pulse signal generation unit 40 includes the first delay circuit 41 and generates the first pulse signal PSG1 whose pulse width is set by the delay time of the first delay circuit 41. The first delay control circuit 50 outputs a control signal CT1 that controls the delay time of the first delay circuit 41, and controls the delay time so as to be the pulse width of the reference clock signal RFCK. For example, the first delay circuit 41 is a circuit in which a plurality of delay elements are connected in series. The delay element is, for example, an inverter and a variable capacitance capacitor (load capacitance) provided at the output of the inverter. Then, the capacitance value of the variable capacitance capacitor is controlled by the control signal CT1, and the delay time of the first delay circuit 41 is controlled. The first delay control circuit 50 includes a phase difference detection unit 51 (phase difference detection circuit) that detects the phase difference between the output signal DLQ1 of the first delay circuit 41 and the clock signal RFCK2 and outputs the signal DT1, and a signal. It includes a control unit 52 (control circuit) that outputs a control signal CT1 based on the DT1. The first integration processing unit 60 performs integration processing based on the first pulse signal PSG1 and the clock signals CKI and CKQ, and outputs the first phase difference signal PH1.

The second phase difference signal output unit 20 includes a second selector 25, a second DLL circuit 140, and a second integration processing unit 90 (second integration processing circuit). The second DLL circuit 140 includes a second pulse signal generation unit 70 (second pulse signal generation circuit) and a second delay control circuit 80.

The second selector 25 selects either the second signal SG2 or the clock signal RFCK2, and outputs the selected signal SLQ2. The second pulse signal generation unit 70 includes the second delay circuit 71 and generates the second pulse signal PSG2 whose pulse width is set by the delay time of the second delay circuit 71. The second delay control circuit 80 outputs a control signal CT2 that controls the delay time of the second delay circuit 71, and controls the delay time so as to be the pulse width of the reference clock signal RFCK. The second delay circuit 71 has the same configuration as the first delay circuit 41. The second delay control circuit 80 includes a phase difference detection unit 81 (phase difference detection circuit) that detects the phase difference between the output signal DLQ2 of the second delay circuit 71 and the clock signal RFCK2 and outputs the signal DT2, and a signal. It includes a control unit 82 (control circuit) that outputs a control signal CT2 based on the DT2. The second integration processing unit 90 performs integration processing based on the second pulse signal PSG2 and the clock signals CKI and CKQ, and outputs the second phase difference signal PH2.

FIG. 8 is a flowchart illustrating the operation of the circuit device of the detailed configuration example. When the operation is started, the measurement unit 30 (processing unit 33 in FIG. 16) sets the pulse width measurement mode (S1). In the pulse width measurement mode, the first phase difference signal output unit 10 and the second phase difference signal output unit 20 measure the pulse width of the reference clock signal RFCK and set the delay time (delay amount) of the delay circuit (delay amount). The pulse width measurement mode to be locked) is set (S1).

FIG. 9 is a diagram illustrating the operation of the first phase difference signal output unit in the pulse width measurement mode. Here, the first phase difference signal output unit 10 will be described as an example, but the operation of the second phase difference signal output unit 20 is also the same. Note that FIG. 9 illustrates the components related to the operation, and the other components are not shown.

In the pulse width measurement mode, the first selector 15 selects the clock signal RFCK2 and outputs it as the signal SLQ1. The delay circuit 41 outputs the signal DLQ1 in which the signal SLQ1 (= RFCK2) is delayed. The phase difference detection unit 51 detects the phase difference between the clock signal RFCK2 and the signal DLQ1, and outputs a signal DT1 representing the detected phase difference. Based on the signal DT1, the control unit 52 generates the control signal CT1 so that the phase difference between the clock signal RFCK2 and the signal DLQ1 becomes zero. Since the frequency of the clock signal RFCK2 is twice the frequency of the reference clock signal RFCK, the delay time of the first delay circuit 41 is a half cycle of the reference clock signal RFCK (reference when the duty of the reference clock signal RFCK is 50%). It is locked to the high pulse width of the clock signal RFCK).

As shown in FIG. 8, the measuring unit 30 sets the phase difference detection mode (S2). In the phase difference detection mode, the first phase difference signal output unit 10 and the second phase difference signal output unit 20 detect the phase difference between the first signal SG1 and the second signal SG2.

FIG. 10 is a diagram illustrating the operation of the first phase difference signal output unit in the phase difference detection mode. Here, the first phase difference signal output unit 10 will be described as an example, but the configuration and operation of the second phase difference signal output unit 20 are also the same. Note that FIG. 10 illustrates the components involved in the operation, and the other components are not shown.

The first pulse signal generation unit 40 includes a first delay circuit 41, a latch circuit 42, and a NOR circuit 43. In the phase difference detection mode, the first selector 15 selects the first signal SG1 and outputs it as the signal SLQ1. The latch circuit 42 captures a high level at the rising edge of the signal SLQ1 (= SG1), changes the signal LQ1 from low level to high level, and changes the signal LQB1 (logical inversion signal of LQ1) from high level to low level. .. The first delay circuit 41 delays the signal LQ1 by the delay time set by the control signal CT1 and outputs the signal DLQ1. The control signal CT1 maintains the value set in the pulse width measurement mode. The NOR circuit 43 outputs the NOR signal of the signal LQB1 and the signal DLQ1 as the first pulse signal PSG1. The value set in the pulse width measurement mode is maintained for the control signal CT1, and the pulse width of the first pulse signal PSG1 becomes the same as the pulse width of the reference clock signal RFCK. The first integration processing unit 60 performs integration processing based on the first pulse signal PSG1 and outputs the first phase difference signal PH1.

As shown in FIG. 8, the measuring unit 30 converts the first phase difference signal PH1 and the second phase difference signal PH2 output in the phase difference detection mode into the first phase difference data and the second phase difference data. A / D conversion (S3). Next, the measuring unit 30 obtains the time difference between the transition timings of the first signal SG1 and the second signal SG2 from the first phase difference data and the second phase difference data by digital signal processing (S4).

4. Integral processing unit FIG. 11 is a detailed configuration example of the first integral processing unit. The first integrator processing unit 60 includes integrators 61 to 66 (a plurality of integrators, first to sixth integrators). Although the first integration processing unit 60 will be described here as an example, the second integration processing unit 90 also includes a plurality of integrators (seventh to twelfth integrators), and the second integrator is similarly operated. Integral processing based on the pulse signal PSG2 of 2 is performed.

The clock signal generation unit 120 generates clock signals CKAI, CKBI, CKCI, CKAQ, CKBQ, and CKCQ and supplies them to the integrators 61, 62, 63, 64, 65, and 66. The clock signals CKAI, CKBI, and CKCI correspond to the clock signals CKI of FIG. 7, and the clock signals CKAQ, CKBQ, and CKCQ correspond to the clock signals CKQ of FIG. The integrators 61, 62, 63, 64, 65, 66 perform integration processing based on the supplied clock signal and the first pulse signal PSG1, and output integrated values PHAI1, PHBI1, PHCI1, PHAQ1, PHBQ1, and PHCQ1. To do. The integrated values PHAI1, PHBI1, PHCI1, PHAQ1, PHBQ1, and PHCQ1 correspond to the first phase difference signal PH1 in FIG. 7.

FIG. 12 is a timing chart of the clock signal generated by the clock signal generation unit.

Clock signals Each of CKAI, CKBI, CKCI, CKAQ, CKBQ, and CKCQ is a combination of two clock signals whose phases are inverted (phases differ by 180 degrees). For example, the clock signal CKAI is composed of clock signals CKAI1 and CKAI2. The 12 clock signals are multi-phase clock signals that are out of phase by 30 degrees (= 360 degrees / 12) with respect to the reference clock signal RFCK.

Specifically, the clock signal CKAI1 has the same phase as the reference clock signal RFCK, and the clock signals CKBI1 and CKCI1 are delayed by 120 degrees and 240 degrees from the reference clock signal RFCK. The clock signals CKAQ1, CKBQ1, and CKCQ1 are 90 degrees out of phase with the clock signals CKAI1, CKBI1, and CKCI1. The phases of the clock signals CKAI2, CKBI2, CKCI2, CKAQ2, CKBQ2, and CKCQ2 are inverted with respect to the clock signals CKAI1, CKBI1, CKCI1, CKAQ1, CKBQ1, and CKCQ1 (the phases are 180 degrees different).

13 to 15 are diagrams showing the characteristics of the integrated value of the integral processing by the polymorphic clock. The phase difference on the horizontal axis is the phase difference between the reference clock signal RFCK and the first signal SG1. As described with reference to FIG. 12, the phases of the clock signals CKAI, CKBI, and CKCI are 0 degrees, 120 degrees, and 240 degrees with reference to the reference clock signal RFCK. Therefore, as shown in FIGS. 13 to 15, the characteristics of the integrated values PHBI1 and PHCI1 deviate from the characteristics of the integrated value PHAI1 by 120 degrees and 240 degrees. Similarly, the characteristics of the integrated values PHBQ1 and PHCQ1 deviate from the characteristics of the integrated value PHAQ1 by 120 degrees and 240 degrees.

The measuring unit 30 obtains the first phase difference from the integrated values PHAI1 and PHAQ1, obtains the second phase difference from the integrated values PHBI1 and PHBQ1, and obtains the third phase difference from the integrated values PHCI1 and PHCQ1. Then, the average value of the first to third phase differences is obtained as the phase difference between the first signal SG1 and the reference clock signal RFCK.

Ideally, the output phase difference having a characteristic linear with respect to the input phase difference can be obtained only with the set of the integrated values PHAI1 and PHAQ1. The input phase difference is the phase difference between the input reference clock signal RFCK and the first signal SG1, and the output phase difference is the phase difference based on the integration process. However, there is a possibility that the input phase difference and the output phase difference will not be linear due to the error of the integrator (for example, the full-scale error of the integrated value, the offset, etc.).

In this regard, in the present embodiment, a plurality of phase differences (first to third phase differences) are obtained by performing integration processing with polyphase clocks having different phases, and the plurality of phase differences are averaged. The non-linearity between the phase difference and the output phase difference can be averaged. For example, when the input phase difference is 180 degrees, the characteristic of the integrated value PHAI1 in FIG. 13 is a point that folds back at −VP. Non-linearity is likely to occur at the point where such characteristics are folded back. However, in FIGS. 14 and 15, the characteristics of the integrated values PHBI1 and PHCI1 at a phase difference of 180 degrees are linear. Therefore, the non-linearity can be reduced by averaging the first to third phase differences.

5. Measuring unit FIG. 16 is a detailed configuration example of the measuring unit. The measuring unit 30 includes a selector 31 (multiplexer), an A / D conversion circuit 32, and a processing unit 33 (digital signal processing unit, processing circuit, logic circuit).

Integral values PHAI1, PHAQ1, PHBI1, PHBQ1, PHCI1, PHCQ1 are input to the selector 31 from the first phase difference signal output unit 10, and integrated values PHAI2, PHAQ2, PHBI2, PHBQ2, PHCI2, and PHCQ2 are input. The selector 31 selects these signals one by one in a time division manner, and outputs the selected signal as a signal MXQ. The A / D conversion circuit 32 A / D-converts the integrated values PHAI1, PHAQ1, PHBI1, PHBQ1, PHCI1, PHCQ1, PHAI2, PHAQ2, PHBI2, PHBQ2, PHCI2, and PHCHQ2 input as the signal MXQ into time divisions. The A / D converted integral value (integral data) is output as data ADQ. The processing unit 33 obtains the time difference data TQ based on the data ADQ by digital signal processing.

Specifically, the processing unit 33 includes a phase difference calculation unit 34 and a time difference calculation unit 35. The phase difference calculation unit 34 obtains the first phase difference from the integrated values PHAI1 and PHAQ1, obtains the second phase difference from the integrated values PHBI1 and PHBQ1, and obtains the third phase difference from the integrated values PHCI1 and PHCQ1. Further, the fourth phase difference is obtained from the integrated values PHAI2 and PHAQ2, the fifth phase difference is obtained from the integrated values PHBI2 and PHBQ2, and the sixth phase difference is obtained from the integrated values PHCI2 and PHCQ1. The phase difference calculation unit 34 averages the first to third phase differences to obtain the phase difference between the first signal SG1 and the reference clock signal RFCK, and averages the fourth to sixth phase differences to obtain a third. The phase difference between the signal SG2 of 2 and the reference clock signal RFCK is obtained. The time difference calculation unit 35 determines the position of the first signal SG1 and the second signal SG2 from the phase difference between the first signal SG1 and the reference clock signal RFCK and the phase difference between the second signal SG2 and the reference clock signal RFCK. The phase difference is obtained, and the time difference data TQ is output based on the phase difference. The method of converting the phase difference into the time difference is the same as the method described with reference to FIG. 2 and the like.

6. The integrator FIG. 17 is a detailed configuration example of the integrator. Further, FIG. 18 is a timing chart illustrating the operation of the integrator. Although the integrator 61 of FIG. 11 will be described here as an example, other integrators (integrators 62 to 66 of FIG. 11 and the integrator of the second integrator processing unit 90) have the same configuration.

As shown in FIG. 17, the integrator 61 includes an integrator signal generation unit GIS, a current generation unit IGEN, and an integrator unit CINT.

The integration signal generation unit GIS generates integration signals INCKA and INCKB from the first pulse signal PSG1 and clock signals CKAI (CKAI1, CKAI2). As shown in FIG. 18, the logical product of the first pulse signal PSG1 and the clock signal CKAI1 is output as the integrated signal INCKA, and the logical product of the first pulse signal PSG1 and the clock signal CKAI2 is output as the integrated signal INCKB.

The current generation unit IGEN generates currents IP and IN based on the integration signals INCKA and INCKB, and supplies the currents IP and IN to the input nodes NINP and NINN of the integration unit CINT. Specifically, when the integration signal INCKA is high level (active) and the integration signal INCKB is low level (inactive), the switch elements SWA1 and SWA2 are turned on, and the switch elements SWB1 and SWB2 are turned off. become. Then, a negative current having a constant current value is supplied to the node NINP as a current IP from the current source IBB, and a positive current having a constant current value is supplied to the node NINN as a current IN from the current source IBA, so that IP-IN <0. On the other hand, when the integration signal INCKA is low level (inactive) and the integration signal INCKB is high level (active), the switch elements SWA1 and SWA2 are turned off, and the switch elements SWB1 and SWB2 are turned on. Then, a positive current having a constant current value is supplied to the node NINP as a current IP from the current source IBA, and a negative current having a constant current value is supplied to the node NINN as a current IN from the current source IBB, and IP-IN> 0.

The integrating unit CINT integrates the differentially input currents IP and IN, and differentially outputs the integrated values as voltages VOUT and VOUTN. That is, charge-voltage conversion is performed to convert the electric charge supplied by the currents IP and IN into the voltages VOUTP and VOUTN. The integrator CINT performs inverting amplification that converts a negative input charge into a positive voltage. That is, when the integration signal INCKA is at a high level and the integration signal INCKB is at a low level, since IP-IN <0 as described above, the voltages VOUTP and VOUTN increase in the direction in which VOUTP-VOUTN increases as shown in FIG. Changes. On the other hand, when the integration signal INCKA is at a low level and the integration signal INCKB is at a high level, IP-IN> 0 as described above, so that the voltages VOUTP and VOUTN decrease in the direction in which VOUTP-VOUTN decreases as shown in FIG. Changes. In this way, the first pulse signal PSG1 is converted into the integrated value PHAI1, and the characteristics of the integrated value PHAI1 shown in FIG. 13 are obtained.

In the integrating unit CINT, when the control signal APCK (clock signal) is low level (inactive) and the control signal XAPCK (clock signal) which is a logical inversion signal of the control signal APCK is high level (active), the switch element. SWP1 to SWP4 are turned off, and switch elements SWP5 to SWP8 are turned on. In this case, the capacitors CP1 to CP4 and the amplifier circuit AMP form a differential integrator circuit (differential charge-voltage conversion circuit), and the above-mentioned integration operation is performed. On the other hand, when the control signal APCK is at a high level (active) and the control signal XAPCK is at a low level (inactive), the switch elements SWP1 to SWP4 are turned on and the switch elements SWP5 to SWP8 are turned off. In this case, the input nodes NINP and NINN are set to the common voltage VCM, the input charge is reset, and the voltages VOUTP and VOUTN are reset to the common voltage VCM.

7. Correction of integrator variation FIG. 19 is a diagram illustrating variations in the characteristics of integrated values between integrators. FIG. 20 is an example of the characteristics of the output phase difference with respect to the input phase difference.

As shown in FIG. 19, it is assumed that the upper limit of the change range of the integrated value PHAQ1 is + VP and the lower limit is −VP. That is, it is assumed that the full scale (output full scale) of the integrated value PHAQ1 is 2VP. At this time, it is ideal that the integrated value PHAI1 is also the same full-scale 2VP as in the integrated value PHAI1'. In this ideal case, as shown in the characteristic CHA of FIG. 20, the output phase difference has a linear characteristic with respect to the input phase difference.

However, as shown in FIG. 19, the full scale of the integrated value PHAI1 may be 2VP'≠ 2VP. For example, in FIG. 17, the magnitude of the current output by the current sources IBA and IBB is large. The variation between the integrators causes a full-scale variation between the integrators. When such a full-scale variation occurs, the output position is relative to the input phase difference as shown in the characteristic CHA'in FIG. The phase difference has a non-linear characteristic.

Moreover, not only full-scale variation but also offset variation may occur. Due to the variation in offset, the output phase difference may have a non-linear characteristic with respect to the input phase difference.

FIG. 21 is a diagram illustrating variation correction of the integrator. Although the first pulse signal PSG1 is shown in FIG. 21 for reference, the first pulse signal PSG1 does not have to be supplied to the integrator at the time of variation correction.

As shown in FIG. 21, the circuit device 100 performs upper limit measurement, lower limit measurement, and offset measurement for each integrator. These measurements are performed before measuring the time difference between the first signal SG1 and the second signal SG2. For example, this is performed when the power of the circuit device 100 is turned on.

At the time of upper limit measurement, the integration signal generation unit GIS outputs an integration signal INCKA that has the same pulse width as the first pulse signal PSG1 and has a high level, and outputs a low-level integration signal INCKB. Since this corresponds to measuring the upper limit of the integrated value, for example, in FIG. 19, + VP'is obtained as the integrated value. At the time of lower limit measurement, the integration signal generation unit GIS outputs a low-level integration signal INCKA and outputs an integration signal INCKB that has the same pulse width as the first pulse signal PSG1 and becomes a high level. Since this corresponds to measuring the lower limit of the integrated value, for example, in FIG. 19, -VP'is obtained as the integrated value. At the time of offset measurement, the integration signal generation unit GIS outputs low-level integration signals INCKA and INCKB. Since this corresponds to measuring the offset of the integrated value, for example, in FIG. 19, 0 is obtained as the integrated value.

The upper limit of the integrated value obtained in the above measurement is IMAX, the lower limit is IMIN, the offset is IOF, and the expected value of full scale is FLS. Further, the integrated value obtained when the time difference between the first signal SG1 and the second signal SG2 is measured is defined as MES. The processing unit 33 of the measuring unit 30 obtains the corrected integrated value MES'by, for example, MES'= (FLS / (IMAX-IMIN)) × (MES-IOF). For example, in the example of FIG. 19, MES'= (VP / VP') × MES. Such correction is made for each integrator. Then, the phase difference is obtained based on the corrected integral value, and the time difference is obtained based on the phase difference.

The integrated value may be corrected by the measured values of the upper limit and the lower limit without performing the offset measurement. In this case, MES'= (FLS / (IMAX-IMIN)) × MES.

8. Physical quantity measuring device, electronic device, mobile body FIG. 22 is a configuration example of a physical quantity measuring device including the circuit device 100 of the present embodiment. The physical quantity measuring device 200 includes a signal supply unit 210 (signal supply circuit), a circuit device 100, and a processing unit 220 (processing circuit, processing device). The present embodiment is not limited to the configuration shown in FIG. 22, and various modifications such as omitting a part of the component (for example, a signal supply unit) or adding another component can be performed. is there.

The physical quantity measuring device 200 of FIG. 22 is a device that measures various physical quantities based on the result of time digital conversion. For example, the physical quantity to be measured is, but is not limited to, time, distance, and the like.

The signal supply unit 210 supplies the first signal SG1 and the second signal SG2 to the circuit device 100. For example, when the physical quantity measuring device 200 is a distance measuring sensor, the signal supply unit 210 includes a light emitting unit, a light receiving unit, and a control unit. Then, the control unit causes the light emitting unit to emit light by the transmission signal, and supplies the transmission signal as the first signal SG1 to the circuit device 100. Further, the control unit generates a received signal by waveform-forming the received signal from the light receiving unit, and supplies the received signal as a second signal SG2 to the circuit device 100. Alternatively, when the physical quantity measuring device 200 is a time digital converter, the signal supply unit 210 waveform-shapes the two signals input from the outside and outputs them as the first signal SG1 and the second signal SG2. Alternatively, the two signals input from the outside are buffered and output as the first signal SG1 and the second signal SG2. Alternatively, the signal supply unit 210 may be a connector for connecting a cable or the like for inputting the first signal SG1 and the second signal SG2 from the outside.

The circuit device 100 measures the time difference between the first signal SG1 and the second signal SG2, and outputs the time difference data TQ. The processing unit 220 performs various digital signal processing based on the time difference data TQ. For example, the processing unit 220 performs a process of converting the time difference data TQ into a physical quantity, and outputs the data of the physical quantity.

FIG. 23 is a configuration example of an electronic device including the circuit device 100 of the present embodiment. The electronic device 300 includes a circuit device 100, an antenna ANT, a communication unit 510 (communication device), and a processing unit 520 (processing device). Further, the operation unit 530 (operation device), the display unit 540 (display device), and the storage unit 550 (memory) can be included. For example, a physical quantity measuring device is composed of a circuit device 100 and a processing unit 520. The electronic device 300 is not limited to the configuration shown in FIG. 23, and various modifications such as omitting some of these components (for example, antenna ANT, communication unit 510, etc.) or adding other components can be performed. It is possible.

As the electronic device 300 of FIG. 23, for example, an in-vehicle electronic device such as an ECU (Electronic Control Unit), an ultrasonic measuring device such as a medical or industrial ultrasonic inspection device, and radio waves and ultrasonic waves are used. You can imagine a radar. Further, as the electronic device 300, a game device, a video device such as a digital camera or a video camera, a mobile information terminal (mobile terminal) such as a smartphone, a mobile phone, a portable game device, a notebook PC or a tablet PC, and contents can be used. Various devices such as content providing terminals to be distributed or network-related devices such as base stations or routers can be assumed.

The communication unit 510 (wireless circuit) performs a process of receiving data from the outside or transmitting data to the outside via the antenna ANT. The processing unit 520 performs control processing of the electronic device 300, various digital processing of data transmitted / received via the communication unit 510, digital processing using the time difference data output by the circuit device 100, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer. The operation unit 530 is for the user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information, and can be realized by a display such as a liquid crystal or an organic EL. When a touch panel display is used as the operation unit 530, the touch panel display also functions as the operation unit 530 and the display unit 540. The storage unit 550 stores data, and its function can be realized by a semiconductor memory such as RAM or ROM, an HDD (hard disk drive), or the like.

FIG. 24 shows an example of a mobile body including the circuit device of the present embodiment. The circuit device 100 (physical quantity measuring device) of the present embodiment can be incorporated into various moving bodies such as a car, an airplane, a motorcycle, a bicycle, or a ship. A moving body is a device / device that is provided with, for example, a drive mechanism such as an engine or a motor, a steering mechanism such as a handle or a rudder, and various electronic devices (vehicle-mounted devices), and moves on the ground, in the air, or on the sea. FIG. 24 schematically shows an automobile 206 as a specific example of the moving body. A physical quantity measuring device (not shown) having the circuit device 100 of the present embodiment is incorporated in the automobile 206. The control device 208 operates based on the physical quantity generated by this physical quantity measuring device. For example, the control device 208 may be an ECU that performs driving assist control or automatic driving control according to the distance between the automobile 206 and the object. The device in which the circuit device and the physical quantity measuring device of the present embodiment are incorporated is not limited to such a control device 208, and can be incorporated into various devices (vehicle-mounted devices) provided in a moving body such as an automobile 206. Is.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present invention are possible. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present invention. Further, the configuration / operation of the circuit device, the physical quantity measuring device, the electronic device, the moving body, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

10 ... 1st phase difference signal output unit, 15 ... 1st selector,
20 ... 2nd phase difference signal output unit, 25 ... 2nd selector, 30 ... Measuring unit,
31 ... Selector, 32 ... A / D conversion circuit, 33 ... Processing unit, 34 ... Phase difference calculation unit,
35 ... Time difference calculation unit, 40 ... First pulse signal generation unit, 41 ... Delay circuit,
41 ... 1st delay circuit, 42 ... latch circuit, 43 ... NOR circuit,
50 ... First delay control circuit, 51 ... Phase difference detection unit, 52 ... Control unit,
60 ... 1st integrator processing unit, 61-66 ... integrator, 70 ... second pulse signal generator,
71 ... second delay circuit, 80 ... second delay control circuit, 81 ... phase difference detector,
82 ... control unit, 90 ... second integration processing unit, 100 ... circuit device, 110 ... counter,
120 ... Clock signal generator, 130 ... First DLL circuit,
140 ... second DLL circuit, 200 ... physical quantity measuring device, 206 ... automobile (mobile body),
208 ... control device, 210 ... signal supply unit, 220 ... processing unit, 300 ... electronic device,
510 ... Communication unit, 520 ... Processing unit, 530 ... Operation unit, 540 ... Display unit, 550 ... Storage unit,
PH1 ... 1st phase difference signal, PH2 ... 2nd phase difference signal, PSG1 ... 1st pulse signal,
PSG2 ... second pulse signal, RFCK ... reference clock signal, SG1 ... first signal,
SG2 ... second signal, TDF ... time difference, TH ... pulse width, TPS ... pulse width,
TQ ... Time difference data

Claims (12)

A first phase difference signal output unit that receives a first signal and outputs a first phase difference signal that represents the phase difference between the reference clock signal and the first signal.
A second phase difference signal output unit that receives a second signal and outputs a second phase difference signal that represents the phase difference between the reference clock signal and the second signal.
A measuring unit that measures the time difference between the first signal and the second signal based on the first phase difference signal and the second phase difference signal.
Including
The first phase difference signal output unit is
It has a first pulse signal generation unit that generates a first pulse signal having a pulse width corresponding to the pulse width of the reference clock signal based on the first signal.
The second phase difference signal output unit is
A circuit device including a second pulse signal generation unit that generates a second pulse signal having a pulse width corresponding to the pulse width of the reference clock signal based on the second signal. In the circuit device according to claim 1,
The first phase difference signal output unit is
Integral processing based on the reference clock signal and the first signal is performed, and the first phase difference signal is output.
The second phase difference signal output unit is
A circuit device characterized in that an integration process based on the reference clock signal and the second signal is performed to output the second phase difference signal. In the circuit device according to claim 1 or 2.
The first pulse signal generation unit
It has a first delay circuit and
The first phase difference signal output unit is
It has a first delay control circuit that sets the delay time of the first delay circuit to a delay time corresponding to the pulse width of the reference clock signal.
The second pulse signal generation unit
Has a second delay circuit,
The second phase difference signal output unit is
A circuit device comprising a second delay control circuit that sets the delay time of the second delay circuit to a delay time corresponding to the pulse width of the reference clock signal. In the circuit device according to claim 3,
The first phase difference signal output unit is
In the pulse width measurement mode, the reference clock signal is output to the first delay circuit, and in the phase difference detection mode, the first pulse signal generation unit has a first selector that outputs the first signal. And
The second phase difference signal output unit is
In the pulse width measurement mode, the reference clock signal is output to the second delay circuit, and in the phase difference detection mode, the second signal is output to the second pulse signal generation unit. A circuit device characterized by having. A first phase difference signal output unit that receives a first signal and outputs a first phase difference signal that represents the phase difference between the reference clock signal and the first signal.
A second phase difference signal output unit that receives a second signal and outputs a second phase difference signal that represents the phase difference between the reference clock signal and the second signal.
A measuring unit that measures the time difference between the first signal and the second signal based on the first phase difference signal and the second phase difference signal.
Including
The first phase difference signal output unit is
A first pulse signal generation unit that generates a first pulse signal having a predetermined pulse width based on the first signal, and a first pulse signal generation unit .
A first integration processing unit that performs integration processing based on the reference clock signal and the first pulse signal, and
Have,
The second phase difference signal output unit is
A second pulse signal generation unit that generates a second pulse signal having the predetermined pulse width based on the second signal.
A second integration processing unit that performs integration processing based on the reference clock signal and the second pulse signal, and
A circuit device characterized by having. In the circuit device according to claim 5,
A circuit device characterized in that the predetermined pulse width is a pulse width corresponding to the pulse width of the reference clock signal. A first phase difference signal output unit that receives a first signal and outputs a first phase difference signal that represents the phase difference between the reference clock signal and the first signal.
A second phase difference signal output unit that receives a second signal and outputs a second phase difference signal that represents the phase difference between the reference clock signal and the second signal.
A measuring unit that measures the time difference between the first signal and the second signal based on the first phase difference signal and the second phase difference signal.
A clock signal generation unit that generates first to nth clock signals (n is an integer of 2 or more) having different phases based on the reference clock signal.
Including
The first phase difference signal output unit is
It has the first to nth clock signals and the first to nth integrators that perform integration processing based on the first signal.
The second phase difference signal output unit is
A circuit device including an n + 1 to 2n integrator that performs an integration process based on the first to second clock signals and the second signal. In the circuit device according to claim 7.
The measuring unit
A selector that selects one of the output signal of the first to nth integrators and the output signal of the n + 1 to 2n integrators, and
An A / D conversion circuit that A / D converts the signal from the selector,
A processing unit that obtains the time difference based on the output signal of the first to nth integrators and the output signal of the n + 1 to second n integrators that have been A / D converted.
A circuit device characterized by having. In the circuit device according to any one of claims 1 to 8.
A counter that counts the number of clocks of the reference clock signal from the activation of the first signal to the activation of the second signal is included.
The measuring unit
A circuit device for measuring the time difference between the first signal and the second signal based on the count value of the counter, the first phase difference signal, and the second phase difference signal. A physical quantity measuring device comprising the circuit device according to any one of claims 1 to 9. An electronic device comprising the circuit device according to any one of claims 1 to 9. A mobile body including the circuit device according to any one of claims 1 to 9.

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