JPS62299786A - Time measuring instrument - Google Patents

Abstract

PURPOSE:To measure a time to be measured even when a fractional pulse is generated continuously at short time intervals by providing two time-voltage converters. CONSTITUTION:A time width signal SX to be measured and a clock signal SC are inputted to a fractional pulse generating circuit 3a, which outputs a start fractional pulse and a stop fractional pulse. Then the start fractional pulse is applied to a time-voltage converter 6a through a switch 20a and the stop fractional pulse is applied to a time-voltage converter 6b through a switch 20b. Then both pulses are latched 9a and 9b at a high speed through AD converters 7a and 7b and both latch outputs are inputted to a CPU 8. Namely, a time measuring instrument is equipped with two sets of circuits consisting of the time-voltage converters, AD converters, and latches and the start and stop fractional pulses are switched by the switches 20a and 20b and measured, so even if both pulses are generated closely, they can be securely converted into voltages and the time to be measured can be measured.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention A. [Invention 1] (Industrial Application Field) The present invention provides a method for changing the voltage according to the start fractional time and the stop fractional time. This invention relates to a device that can measure the time to be measured by adding arithmetic operations to a digital signal based on this voltage at U.

(Prior Art) Generally, the following principle is adopted to measure time at high degrees. A clock signal with a period of I'll j o is passed through a gate that is open during the period of the measured time width Tx, and the number N of the clocks passing through is counted. And, Nto is the time width.

Strictly speaking, this method does not hold Tx = Nto, but Tx~Nto. This typically means that T x is 1
This is because it is not divisible by 0 and there are times that are small fractions. This is shown in FIG. In Figure 4, ΔT in (C)
+ is the starting fractional time from the rising edge of Tx to the clock Co generated immediately after that, and Δ in (d)
T2 is the stop fractional time from the falling edge of Tx to the clock Cn generated immediately thereafter. and,
The gate is opened during the period between clock signals Co and CTI [see (6) in FIG. 4], and the number of clocks passing through is counted. Assuming that the number of clocks in that period is N, the time width Tχ [FIG. 4(f)] is expressed by equation (1).

Ding χ−Njo ten ΔT+ −ΔT 2 (
1) Therefore, if we measure the fractional times ΔT1 and ΔT2, we get
It can be seen from equation (1) that the time width Tχ can be measured with a resolution of 10 or more clock cycles.

As a known means capable of measuring this fractional time ΔT, so-called time expansion (ttme ex
There is a method called ``pansion'' method.

This method uses a period of fractional time Δt, a current value consisting of, for example, 2
A capacitor is charged with a current value of 001, and then this capacitor is slowly discharged with a current value of I, for example. By measuring this discharge period with a clock, fractional hours are measured. This conventional time expansion method is described in detail in the patent application entitled "Hour Meter S Apparatus 1" (hereinafter simply referred to as "Prior Application 1") filed by the present applicant on June 6, 1986.

[Problem that the invention seeks to solve]

However, in order to accurately measure the minute pulse width that represents fractional time, the time expansion type device described above expands the minute pulse width and counts this expanded pulse width with a clock. It is an alternative to measuring time. Therefore, an expanded pulse width period is required, which deteriorates the responsiveness of the time measurement circuit. Therefore, when the measured time width Tχ shown in FIG. 4(a) is small, the start fractional pulse and the stop fractional pulse occur successively within close time, so there is no time margin for discharging the capacitor. There is a problem that will disappear. That is, there is a problem in that it is not possible to perform measurements at short time intervals (high-speed repeated measurements).

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a time measurement device that can measure short time intervals and also measure with high resolution.

[Structure of the Invention J (Means for Solving the Problems) In order to solve the above problems, the present invention changes the voltage according to the start fractional time and the stop fractional time, and calculates the voltage based on this voltage. In a device that calculates the time to be measured (Tχ) by h1 by adding calculations to the digital signal in the CPU (8), a time width signal to be measured (sx) and a clock signal are introduced, and a start fractional pulse and a stop fractional pulse are generated. A fractional pulse generation circuit (3a) to output, and two time-voltage converters (
6a, 6b) and this time/voltage converter (6a, 6
b) An AD converter (
7).

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the overall configuration of a time measurement aAH according to the present invention, and FIG. 2 is a diagram showing in detail the portion of FIG. 1 that measures fractional time.

Also, Figures 3 and 4 are time chit! - It is.

First, the entire time measuring device according to the present invention will be explained using FIG. In the figure, pl and p2 are input terminals into which signals to be measured are introduced, and two signals for measuring a time difference are applied to input terminals pi and p2, respectively. In addition,
The time meter S device according to the present invention can also measure the frequency, period, etc. of a signal, and when measuring these, the signal under measurement is applied to only one input terminal.

1a and 1b are input amplifiers, which operate as buffer 7 amplifiers for the signal under test, attenuators, DC coupling/
It has functions such as selection of ΔC bonds.

2a and 2b are comparators, and the trigger level signals @st1. st2 and the signals introduced from the input amplifiers Ia and 1b to shape the signal under test into a pulse waveform. By shaping the signal to be measured in this way, signal processing by the gate circuit Izaki, which will be described next, becomes easier.

3 is a gate circuit into which the output signals of the comparators 2a and 2b and the clock signal SC from the clock generator 11 are introduced. Then, using the signals introduced from the comparators 2a and 2b, a measured time width signal SX as shown in FIG. , the start fractional time (ΔT+) and the stop fractional time (ΔT2) shown in (d)
) and the gating clock signal S shown in FIG. 4(f) are generated and output to the next stage.

A counter 4 counts the gating clock signal sg as shown in FIG. 4(f).

Reference numeral 5 denotes a known pulse generation circuit, which generates a signal whose pulse width is accurately known in order to eliminate disturbances such as bias current in fractional time measurements. Here, the pulse width of the clock signal is t.

is the known pulse width.

A time/voltage converter 6 outputs a signal whose voltage changes according to the pulse width of the signal S3 from the gate circuit 3 and the signal S5 from the known pulse generating circuit 5. The present invention is characterized in that two-phase time/voltage converters capable of high-speed, high-resolution time measurement are biased in correspondence with the star 1 fractional pulse and the stop fractional pulse.

FIG. 5 shows an example of the configuration of a time/voltage converter.

7 is an AD converter, which converts the output of the time/voltage converter 6 into a digital signal. In Figure 1, this A
An example is shown in which two sets of D converters 7 are used. However, as will be described later, the present invention can be established even if there is only one AD converter 7.

Since high speed is required in the field to which the present invention relates, a flash type (fully parallel type) AD converter is usually used.

The outputs of this AD converter 7 and counter 4 are sent to the CPU (cen
tral processing unit ) 8, where the time width Tχ of the measured object is calculated by performing an operation as shown in equation (1), for example. In addition, the CPU
8 also performs a correction calculation to remove the influence of bias current, off-hit voltage, etc., using the measured value of the known pulse when calculating the above-mentioned lower X. For example, a microprocessor can be used as this CPU.

FIG. 2 is a diagram that does not show the main part of the present invention, and shows in detail the portion of FIG. 1 that measures the fractional time.

In the figure, 3a is a fractional pulse generation circuit, and the first
This is included in the gate circuit 3 shown in the figure. A measured time width signal SX as shown in FIG. 4(a) is applied to this @several pulse generating circuit 3a. This measured time width signal Sx is a signal generated inside the gate circuit 3 based on the output signals of the comparators 2a and 2b. The fractional pulse generating circuit 3a also introduces the clock signal @SC, and outputs a start fractional pulse and a stop fractional pulse as shown in FIGS. 4(C) and 4(d). In addition,
In FIG. 1, the start fractional pulse and the stop fractional pulse are collectively represented by a signal S3.

Reference numeral 5 denotes a known pulse generation circuit, which has already been explained in FIG. 1, so its explanation will be omitted.

20a and 20b are switches which switch between a start fractional pulse, a stop fractional pulse, and a known pulse and transmit them to the next stage. Note that this switch 20a,
The switching it, l III of 20b is performed by the CPU 8.

Oa and 6b are time/voltage transformers 211 having the same configuration as already explained in FIG.

The following description will be made assuming that the start fractional pulse is applied to the time/voltage converter 6a via the switch 20a, and the stop fractional pulse is applied to the time/voltage converter 6h via the switch 20b.

7a and 7b are △D weird! ! llI device, and has already been explained in FIG. 1, so further explanation thereof will be omitted.

9a, 9b, and AD converters 7a, 7b.
(7) This is a circuit that latches the output value at high speed and temporarily stores it. The output of these latches 9a and 91+ is the CPU
8 will be introduced.

The time 5 sub-device of the present invention shown in FIGS. Switch 20a for pulse and stop fractional pulse,
20b, each pulse is measured separately, so even if a start fractional pulse and a stop fractional pulse occur close to each other, they can be measured reliably.

Hereinafter, the operation of the apparatus according to the present invention will be explained in detail.

Input terminal p1. The signal to be measured applied to p2 is passed through input amplifiers la and lb to comparators 2a and 2b.
added to. Then, the waveform is shaped here and introduced into the gate circuit 3. The gate circuit 3 internally generates a measured time width upward curve SX as shown in FIG. In the fractional pulse generation circuit 3a, the fourth
A start fractional pulse and a stop fractional pulse as shown in FIGS. (C) and (d) are generated, and below, the d811I operation of the width (ΔT+) of the start fractional pulse will be explained.

When the start fractional pulse is input, the time/voltage converter 6
a operates as follows. Here, the time/voltage converter can be configured as shown in FIG. 5, for example.

In FIG. 5, 61 is a buffer amplifier, and when a fractional pulse S3 is applied, two differential signals (S(11, s
q2). This buffer amplifier 0
1 is ECL gate, differential amplification, for example? 9i or the like. One output 5 (11) of this buffer amplifier 61 is introduced into the base of transistor Q+, and the other output sq2 is introduced into the base of transistor Q2.The emitters of these two transistors Q1 and 02 are connected to each other and are connected to a constant current source. 62. This constant current gi
62 can be composed of, for example, a transistor or a resistor. A constant current l flows through the constant current source 62 and is connected to the voltage (-■). The collector of the transistor Q is connected to the circuit ground f-, and the collector of the transistor Q2 is introduced into the amplifier 64.

Furthermore, a capacitor 63 is connected between the input section of this amplifier 64 and circuit ground. This capacitor 63 is connected to a voltage (Vo) via a switch 68.

This switch 68 is controlled by a reset signal sr from outside the circuit of FIG. The output of the amplifier 64 is introduced into the ΔD converter 7a and converted into a digital signal.

Time/voltage variation l! configured as shown in Figure 5! i! The operation of the I-device is explained in detail in the specification of the "earlier application".

Since the gist of the present invention does not lie in this time/voltage converter, a detailed explanation of the operation in FIG. 5 will be omitted in Honkawa aS.

Before the start fractional pulse is applied, the capacitor v63
The voltage V is applied via the switch 68 to the voltage V.

(See Figure 3 (11)).

When a fractional pulse is input, the transistor Q2 in FIG.
is turned on, so the capacitor 63 starts alternating current with a current of 1. And this discharge is from star 1 to fractional time Δ
T+ continues, and the voltage of the capacitor 63 becomes Vχ like a river in FIG.
The voltage (vO9X) in figure (11).

V+, . . . ) are sequentially converted into digital signals and stored. These voltages have the following (2) to
There is a relationship shown in equation (4).

= te (i-c) ΔT + 10Vo-υoFF (2) Similarly, + = c (J ia ) to 10Vo-υ, F
F(3)■? -Up (i-us) ・2 to +Vo
-υ, FF (4) i: Current value of constant current source 62 (integrated current) C: Current value of capacitor 63 iB: Bias current υOFF' Offset voltage to: Period of clock signal (known value) V+, V2
: Voltage corresponding to the period of the clock signal, and the CPU
At step 8, the next stop is applied to numb the time width Tχ to be measured.

First, the starting fractional time (ΔT+) is obtained by equation (5).

Similarly for the stop fractional time (△T2), V+
-, V2' is the output of the time-to-voltage converter corresponding to the width of the known pulse seen during stop fractional pulse measurement. That is, the voltages correspond to V+ and V2 shown in FIG. 3 (11).

From the above ΔTI+ΔT2, the measured time width Tχ is calculated by 1q using the following equation.

...(7) In this way, the bias N current IB1 offset voltage υ
Therefore, the influence of the charging voltage value Vo of the capacitor 63 can be removed.

In addition, although it was explained above that two sets each of AD converters and latches are provided, regarding the AD converter and the latch,
The present invention can be achieved even with one set.

FIG. 6 shows an example of the configuration in this case.

The difference between FIG. 6 and FIG. 2 is that the switch 70 is
This switch 70 is added in front of the converter 11, and the output voltages of the two time/voltage converters 6a and 6b are switched and applied to the ΔD converter 71, respectively.

The response of the △D converter 11 is usually sufficiently fast, and the output value of the time/voltage converter is connected to the capacitor length, so even if a start fractional pulse and a stop fractional pulse occur in close proximity, they are each digital. It can be converted into a signal. This digital signal is then stored in the latch 91,
It is later read out by the CPU 8 and by adding the above-mentioned exponent, the time width Tχ to be measured can be calculated.

C. ``Effects of the present invention'' According to the present invention, since two sets of time/voltage converters are provided, even if fractional pulses occur seven times in a row at short time intervals, they can be reliably converted into voltage. Can be done. That is, high-speed repetitive measurements can be performed. Furthermore, since AD conversion has high precision and high resolution, it is possible to precisely measure time widths. Therefore, the device of the present invention can solve the problems that the conventional devices had.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time measuring device according to the present invention, and FIG.
The figure shows an example of the configuration of the fractional time measuring circuit which is the main part of the present invention, Figures 3 and 4 are time charts of the device according to the present invention, and Figure 5 shows a specific example of the time/voltage converter. A diagram showing a configuration example, FIG. 6 shows another configuration example of the present invention. Figure 1. la, lb...input amplifier, 2a, 2b...
Comparator, 3... Gate circuit, 3a... Fractional pulse generation circuit, 4... Counter, 5... Known pulse generation circuit, 6a, 6b... Time/voltage converter, 7.
...AD converter, 8...CPU120a, 20b
···switch. Figure 3 Figure 4

Claims (1)

[Claims] The voltage is changed according to the start fractional time and the stop fractional time, and the CPU (8) converts the voltage into a digital signal based on this voltage.
In a device that measures the time to be measured (T_χ) by adding calculations, a fractional pulse generation circuit (3a) that introduces the time width signal to be measured (sx) and a clock signal and outputs a start fractional pulse and a stop fractional pulse. and two time/voltage converters (6a, 6b) that output signals whose voltage changes according to the pulse width of the signal introduced from the fractional pulse generating circuit (3a), and the time/voltage converters (6a, 6b). A time measuring device comprising: an AD converter (7) that converts the output signal of step 6b) into a digital signal.