JP6878943B2 - Circuit devices, physical quantity measuring devices, electronic devices and mobile objects - Google Patents

Description

The present invention relates to a circuit device, a physical quantity measuring device, an electronic device, a mobile body, and the like.

A phase difference detection type time digital converter that detects the phase difference between a transmission signal and a reception signal and measures TOF (Time Of Flight) based on the phase difference is known. In the conventional phase difference detection method, the phase difference between the transmitted signal and the received signal is converted into an electric charge by a sensor (the amount of electric charge corresponding to the integrated value of the electric charge is accumulated), and the phase difference is detected based on the electric charge. ..

For example, in Patent Documents 1 to 3, light is emitted toward a measurement target, the reflected light from the measurement target is received by the sensor, and the amount of charge corresponding to the phase difference between the light emission timing and the light reception timing is accumulated in the sensor. A method of measuring the distance to be measured based on the amount of charge read from is disclosed.

Japanese Unexamined Patent Publication No. 2012-93256 Japanese Unexamined Patent Publication No. 2008-164496 Japanese Unexamined Patent Publication No. 2011-53216

In the above-mentioned conventional technique, the phase difference between the transmission signal and the reception signal is converted into an electric charge (integral value) by a sensor, and the distance is measured based on the phase difference represented by the electric charge. Therefore, it has been difficult to apply the phase difference detection method to applications other than TOF (used as a general-purpose time-digital converter).

The present invention has been made to solve at least a part of the above problems, and can be realized as the following forms or embodiments.

One aspect of the present invention is a pulse signal generation unit that generates a pulse signal having a pulse width corresponding to the pulse width of the reference clock signal based on the input signal, and an integration process based on the reference clock signal and the pulse signal. The present invention relates to a circuit device including an integration processing unit that generates a phase difference signal representing a phase difference between the reference clock signal and the input signal.

According to one aspect of the present invention, a pulse signal having a pulse width corresponding to the pulse width of the reference clock signal is generated. By performing the integration process based on the pulse signal having such a pulse width and the reference clock signal, it is possible to generate an integrated value representing the phase difference between the reference clock signal and the input signal as a phase difference signal. Then, by generating the phase difference signal by such a method, the phase difference detection method can be applied to a general-purpose time digital converter.

Further, in one aspect of the present invention, the circuit device includes a delay control circuit, the pulse signal generation unit has a delay circuit, and the delay control circuit sets the delay time of the delay circuit to the pulse of the reference clock signal. The delay time corresponding to the width may be set.

In this way, a pulse signal having a pulse width corresponding to the pulse width of the reference clock signal can be generated by using the delay circuit set to the delay time corresponding to the pulse width of the reference clock signal.

Further, in one aspect of the present invention, the circuit device outputs the reference clock signal to the delay circuit in the pulse width measurement mode, and outputs the input signal to the pulse signal generation unit in the phase difference detection mode. It may be included.

In this way, the delay time of the delay circuit can be set by the delay circuit and the delay control circuit in the pulse width measurement mode. Then, in the phase difference detection mode, the pulse signal generation unit can generate a pulse signal from the input signal using the delay time of the delay circuit, and can generate a phase difference signal based on the pulse signal.

Further, in one aspect of the present invention, the circuit device includes a clock signal generation unit that generates first to nth clock signals (n is an integrator of 2 or more) having different phases from each other based on the reference clock signal. The integrator may include the first to nth clock signals and the first to nth integrators that perform integrator processing based on the input signal.

In this way, the characteristics of the first to nth integrated values having different phases from each other can be obtained. As a result, n integral values based on n characteristics having different phases can be obtained with respect to the input phase difference. The integration process may have non-linearity due to variations in the characteristics of the integrator, etc., which may cause non-linearity between the input phase difference and the output phase difference. In this regard, according to one aspect of the present invention, the non-linearity between the input phase difference and the output phase difference can be reduced by, for example, averaging n integrated values to obtain the phase difference.

Further, in one aspect of the present invention, the circuit device may include a measuring unit that measures the phase difference between the reference clock signal and the input signal based on the output signals of the first to nth integrators. ..

In this way, n integrated values (output signals of the first to nth integrators) based on n characteristics having different phases can be obtained with respect to the phase difference between the reference clock signal and the input signal. .. Then, by measuring the phase difference based on the n integral values, the non-linearity between the input phase difference and the output phase difference can be reduced.

Further, in one aspect of the present invention, the clock signal generation unit has a phase with respect to the reference clock signal as the i-th clock signal (i is an integrator of 1 or more and n or less) of the first to nth clock signals. (I-1) × Δθ Different clock signals are generated, and the integrator i of the first to nth integrators performs an integrating process based on the i-th clock signal and the pulse signal, and the integrator is described. The measuring unit obtains the first to nth phase differences based on the output signals of the first to nth integrators, and performs the averaging processing of the first to nth phase differences to obtain the phase difference. You may.

In this way, the first to nth phase differences are obtained based on the n integral values based on the n characteristics having different phases, and the averaging of the first to nth phase differences is performed. The phase difference is required. By such averaging processing, the variation of the integrator can be averaged and the non-linearity between the input phase difference and the output phase difference can be reduced.

Further, in one aspect of the present invention, the circuit device includes a clock signal generation unit that generates a first phase clock signal and a second phase clock signal that are 90 degrees out of phase with each other based on the reference clock signal, and the above-mentioned position. The integrator including the measuring unit for measuring the phase difference, the integrator for the first phase which performs the integrating process based on the clock signal of the first phase and the input signal, and the clock signal of the second phase. And an integrator for the second phase that performs integrator processing based on the input signal, and the measuring unit corrects the variation between the integrator for the first phase and the integrator for the second phase. The phase difference may be measured by performing the correction process.

Due to the variation between the integrator for the first phase and the integrator for the second phase, the linearity of the output phase difference with respect to the input phase difference may decrease (non-linearity occurs). In this regard, according to one aspect of the present invention, a correction process for correcting the variation between the integrator for the first phase and the integrator for the second phase is performed. By obtaining the phase difference, the linearity of the output phase difference with respect to the input phase difference can be improved.

Further, in one aspect of the present invention, the measuring unit has a second selector for selecting either an output signal of the integrator for the first phase or an output signal of the integrator for the second phase, and the first. The signal from the selector 2 is A / D converted, and the A / D converted output signal of the integrator for the first phase and the phase difference data which is the output signal of the integrator for the second phase are output. It may have an A / D conversion circuit and a processing unit that performs the correction processing on the phase difference data and obtains the phase difference based on the phase difference data after the correction processing.

In this way, the output signal of the integrator of the first phase and the output signal of the integrator of the second phase can be A / D converted into time division. As a result, the circuit scale can be saved. Further, by performing such A / D conversion, the phase difference can be obtained based on the output signal (integrated value) of the integrator by digital signal processing. Further, by performing the correction processing by the digital signal processing, the variation correction of the integrator can be realized with a simple configuration.

Further, another aspect of the present invention relates to a physical quantity measuring device including the circuit device according to any one of the above.

Yet another aspect of the present invention relates to an electronic device including the circuit device according to any of the above.

Yet another aspect of the invention relates to a mobile body comprising the circuit device according to any of the above.

A first configuration example of the circuit device of this embodiment. The figure explaining the method of time difference measurement in this embodiment. A timing chart for explaining the operation of the first phase difference signal output unit. The figure which shows the characteristic of the integrated value. A second configuration example of the circuit device of this embodiment. A timing chart for explaining the operation of the circuit device of the second configuration example. A detailed configuration example of the circuit device of this embodiment. The flowchart explaining the operation of the circuit apparatus of the detailed configuration example. The figure explaining the operation of the 1st phase difference signal output part in a pulse width measurement mode. The figure explaining the operation of the 1st phase difference signal output part in the phase difference detection mode. A detailed configuration example of the first integration processing unit. A timing chart of the clock signal generated by the clock signal generator. The figure which shows the characteristic of the integral value of the integral processing by a polyphase clock. The figure which shows the characteristic of the integral value of the integral processing by a polyphase clock. The figure which shows the characteristic of the integral value of the integral processing by a polyphase clock. Detailed configuration example of the measuring unit. Detailed configuration example of the integrator. A timing chart that illustrates the operation of the integrator. The figure explaining the variation of the characteristic of the integrated value among the integrators. An example of the characteristics of the output phase difference with respect to the input phase difference. The figure explaining the variation correction of an integrator. A configuration example of a circuit device when the method of this embodiment is applied to a PLL. Configuration example of physical quantity measuring device. Configuration example of electronic equipment. Configuration example of a moving body.

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as a means for solving the present invention. Not necessarily.

1. 1. First Configuration Example As described above, in the conventional phase difference detection method, the signal is integrated by the sensor, and the output signal of the sensor is the phase difference signal. This method is used for, for example, three-dimensional measurement. That is, the distance is measured at each pixel using the two-dimensional sensor, and the three-dimensional information of the measurement target is acquired.

Since the phase difference detection method measures the phase difference (time difference) between the transmitted signal and the received signal, it can be considered as a kind of time digital converter. However, since it is necessary to spontaneously generate a transmission signal and it is converted into a phase difference by a sensor, its use as a time digital converter is limited. For example, it is difficult to apply a time digital converter of a conventional phase difference detection method to measurement of the delay difference between two signal paths, phase difference detection in a PLL, and the like.

FIG. 1 is a first configuration example of the circuit device of the present embodiment. The circuit device 100 includes a pulse signal generation unit 40 (pulse signal generation circuit), an integration processing unit 60 (integration processing circuit), and a measurement unit 30 (measurement circuit). The present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting a part of the constituent elements or adding other constituent elements are possible. For example, in FIG. 1, the reference clock signal RFCK is input to the pulse signal generation unit 40, but the present invention is not limited to this, and the clock signal generated using the reference clock signal RFCK as a phase or frequency reference is the pulse signal generation unit 40. May be entered in.

The circuit device 100 of FIG. 1 detects the phase difference between the input signal SG1 and the reference clock signal RFCK, and converts the time difference between the transition timings of the input signal SG1 and the reference clock signal RFCK into a digital value (time difference data TQ). It is a circuit.

FIG. 2 is a diagram illustrating a method of measuring the phase difference (time difference) in the present embodiment. In the following, the case where the transition timing of each signal is the rising edge of the signal will be described as an example, but the transition timing of the signal is not limited to this. That is, the transition timing may be any timing at which the signal level changes.

The pulse signal generation unit 40 generates the pulse signal PSG1 based on the reference clock signal RFCK and the input signal SG1. Further, the integration processing unit 60 generates a phase difference signal PH1 corresponding to the phase difference between the rising edge of the reference clock signal RFCK and the rising edge of the input signal SG1 based on the pulse signal PSG1. The measuring unit 30 obtains the phase difference between the rising edge of the reference clock signal RFCK and the rising edge of the input signal SG1 from the phase difference signal PH1. For example, assume that one cycle of the reference clock signal RFCK is 360 degrees and the phase difference is 60 degrees. The measuring unit 30 obtains a phase difference of 60 degrees from the phase difference signal PH1, and outputs a digital value representing the phase difference of 60 degrees as time difference data TQ. Alternatively, when one cycle of the reference clock signal RFCK is TRF, the phase difference of 60 degrees is converted into the time difference TDF = (60 degrees / 360 degrees) × TRF, and the time difference data TQ representing the time difference TDF is output.

Various signals can be assumed as the input signal SG1. For example, the input signal SG1 may be a stop signal in the TOF type ranging sensor. In this case, a start signal is generated based on the reference clock signal RFCK, and the time between the start signal and the stop signal is measured. Alternatively, the input signal SG1 may be a signal to be synchronized with a reference signal (for example, a reference clock, a time pulse, etc.) (for example, a timing signal, a clock signal, etc., which is synchronized with the reference clock or the time pulse). In this case, the reference signal corresponds to the reference clock signal RFCK, and the time difference between the reference signal and the signal to be synchronized with the reference signal is measured. In this example, the context of the reference clock signal RFCK and the input signal SG1 is not determined. For example, when the transition timing of the reference clock signal RFCK and the transition timing of the input signal SG1 are input in this order, a positive phase difference (time difference TDF) is output, and the transition timing of the input signal SG1 and the reference clock signal RFCK are output. When input in the order of transition timing, a negative phase difference (time difference TDF) is output.

The phase difference signal PH1 is a signal whose signal value corresponds to a phase difference of 0 degrees to 360 degrees, and is, for example, a signal whose phase difference of 0 degrees to 360 degrees corresponds to 1: 1. For example, the phase difference signal is a combination of phase difference sine and cosine, or a combination of signals similar thereto (for example, PHQ, PHI in FIG. 4). The phase difference signal is not limited to this, and any signal that can specify the phase difference from the phase difference signal may be used.

More specifically, in the present embodiment, the pulse signal generation unit 40 generates a pulse signal PSG1 having a pulse width corresponding to the pulse width of the reference clock signal RFCK based on the input signal SG1. The integration processing unit 60 performs integration processing based on the reference clock signal RFCK and the pulse signal PSG1 to generate a phase difference signal PH1 representing the phase difference between the reference clock signal RFCK and the input signal SG1.

FIG. 3 is a timing chart illustrating the operations of the pulse signal generation unit and the integration processing unit.

The pulse signal generation unit 40 generates the pulse signal PSG1 from the input signal SG1. The rising edge (transition timing) of the input signal SG1 and the pulse signal PSG1 is the same timing, and the pulse width TPS of the pulse signal PSG1 is the same as the pulse width TH (high level period) of the reference clock signal RFCK. The integration processing unit 60 integrates the reference clock signal RFCK during the integration period in which the pulse signal PSG1 is active (high level, first logic level). Specifically, during the integration period, the negative signal level is integrated during the period when the reference clock signal RFCK is low level TAM, and the positive signal level is integrated during the period TAP when the reference clock signal RFCK is high level, and the integrated value PHI. (Signal) is output. The integrated negative signal level and positive signal level are signal levels with the same absolute value. Further, the integration processing unit 60 integrates the clock signal RFCK'in which the phase is 90 degrees different from that of the reference clock signal RFCK in the integration period. Specifically, in the integration period, the negative signal level is integrated in the period TBM where the clock signal RFCK'is low level, and the positive signal level is integrated in the period TBP when the clock signal RFCK' is high level, and the integrated value PHQ (Signal) is output. The integration processing unit 60 outputs the integrated values PHI and PHQ as the phase difference signal PH1.

FIG. 4 is a diagram showing the characteristics of the integrated value. The upper limit of the range in which the integrated value changes is + VP, and the lower limit is -VP. The integrated value PHI has the characteristics of a pseudo cosine wave. Specifically, it is a triangular wave having the same phase as the cosine wave, and is a waveform obtained by linearly interpolating (straight line approximation) between the vertices of the cosine wave (0 degrees, 180 degrees, 360 degrees) and the zero crossing point (90 degrees, 270 degrees). Is. Further, the integrated value PHQ has a pseudo sine wave characteristic. Specifically, it is a triangular wave having the same phase as the sine wave, and is a waveform obtained by linearly interpolating (straight line approximation) between the zero cross point (0 degree, 180 degree, 360 degree) and the apex (90 degree, 270 degree) of the sine wave. Is. Since the angle (phase difference) can be uniquely determined in the range of 0 degrees to 360 degrees with respect to the sine and cosine values, the phase difference can be determined from the integrated values PHI and PHQ. For example, when the integral value (PHI, PHQ) = (-VP / 2, + VP / 2) as shown in FIG. 4, the phase difference can be determined to be 135 degrees.

According to the above embodiment, the pulse signal PSG1 having a pulse width corresponding to the pulse width of the reference clock signal RFCK is generated. As a result, the integration process for integrating the reference clock signal RFCK in the integration period defined by the pulse width of the pulse signal PSG1 becomes possible, and the integrated value corresponding to the phase difference between the reference clock signal RFCK and the input signal SG1 is converted into the phase difference signal PH1. Can be generated as. Then, by detecting the phase difference by such a method, it is possible to realize a time digital conversion circuit applicable to various applications, not limited to the TOF type ranging sensor as in the conventional phase difference detection method.

Further, in the present embodiment, the pulse signal generation unit 40 has a delay circuit (delay circuit 41 in FIG. 7). The circuit device 100 includes a delay control circuit (delay control circuit 50 in FIG. 7) that sets the delay time of the delay circuit to a delay time corresponding to the pulse width TH of the reference clock signal RFCK. Then, a DLL (Delay Locked Loop) circuit (DLL circuit 130 in FIG. 7) is configured including a delay circuit and a delay control circuit.

In this way, the pulse signal PSG1 having the pulse width TPS corresponding to the pulse width TH of the reference clock signal RFCK can be generated by the delay circuit set to the delay time corresponding to the pulse width TH of the reference clock signal RFCK.

Further, in the present embodiment, the circuit device 100 has a selector (selector 15 in FIG. 7). The selector outputs the reference clock signal RFCK to the delay circuit in the pulse width measurement mode, and outputs the input signal SG1 to the pulse signal generation unit 40 in the phase difference detection mode.

For example, the pulse width measurement mode is set intermittently. That is, the first period in which the pulse width measurement mode is set and the second period in which the phase difference detection mode is set are alternately repeated, and the phase difference is detected (measurement of the time difference) in the second period. It is said. The second period corresponds to a waiting period for waiting for the input of the input signal SG1. When the input signal SG1 is input during this standby period, the phase difference (time difference) is measured. One measurement may be made during one second period, or multiple measurements may be made.

In this way, the delay time of the delay circuit can be set by the delay circuit and the delay control circuit in the pulse width measurement mode. Then, in the phase difference detection mode, the pulse signal generation unit 40 can generate a pulse signal PSG1 based on the input signal SG1 and detect the phase difference (measure the time difference) based on the pulse signal PSG1.

Further, in the present embodiment, the circuit device 100 is a clock signal generation unit that generates first to nth clock signals (clock signals CKAI1, CKBI1, CKCI1 in FIG. 12) having different phases from each other based on the reference clock signal RFCK. (Clock signal generation unit 120 in FIG. 7) is included. The integration processing unit 60 has first to nth integrators (integrators 61 to 63 in FIG. 11) that perform integration processing based on the first to nth clock signals and the input signal SG1.

Specifically, the phase of the first to nth clock signals is in increments of 360 degrees / n with reference to the reference clock signal RFCK. For example, in FIG. 12, n = 3, and the phases of the first to third clock signals (CKAI1, CKBI1, CKCI1) are in 360 degree / 3 = 120 degree increments. The clock signals (CKAQ1, CKBQ1, CKCQ1) whose phase is 90 degrees different from that of the first to third clock signals (CKAI1, CKBI1, CKCI1), and the clock signals (CKAI2, CKBI2, CKCI2, CKAQ2) whose phase is 180 degrees different from them. , CKBQ2, CCKQ2), it becomes a multi-phase clock of 360 degrees / 12 = 30 degrees.

In this way, as will be described later in FIGS. 13 to 15, the characteristics (PHAI1, PHBI1, PHCI1) of the first to nth integrated values having different phases from each other can be obtained. As a result, n integral values based on n characteristics having different phases can be obtained with respect to the input phase difference. The integration process may have non-linearity due to variations in the characteristics of the integrator, etc., which may cause non-linearity between the input phase difference and the output phase difference. In this regard, according to the present embodiment, the non-linearity between the input phase difference and the output phase difference can be reduced by, for example, averaging n integrated values to obtain the phase difference.

Further, in the present embodiment, the measuring unit 30 measures the phase difference between the reference clock signal RFCK and the input signal SG1 based on the output signals of the first to nth integrators (integrators 61 to 63 in FIG. 11). To do.

In this way, with respect to the phase difference between the reference clock signal RFCK and the input signal SG1, n integral values (output signals of the first to nth integrators) based on n characteristics having different phases are obtained. can get. Then, by measuring the phase difference based on the n integral values, the non-linearity between the input phase difference and the output phase difference can be reduced as described above.

Further, in the present embodiment, the clock signal generator has a phase (i-) with respect to the reference clock signal RFCK as the i-th clock signal (i is an integer of 1 or more and n or less) of the first to nth clock signals. 1) × Δθ Generate different clock signals. The i-th integrator of the first to n-th integrators performs integration processing based on the i-th clock signal and the pulse signal PSG1. The measuring unit 30 obtains the first to nth phase differences based on the output signals of the first to nth integrators, and performs averaging processing of the first to nth phase differences to obtain the phase difference.

For example, in FIG. 12, n = 3, and the first to third clock signals are CKAI1, CKBI1, and CKCI1. Further, Δθ = 360 degrees / 3 = 120 degrees. The first clock signal CKAI1, the second clock signal CKBI1, and the third clock signal CKCI1 have a phase of 0 × 120 degrees = 0 degrees, 1 × 120 degrees = 120 degrees, and 2 × 120 with respect to the reference clock signal RFCK. Degree = 240 degrees different. The measuring unit 30 obtains the first to third phase differences based on the output signals (integrated values PHAI1, PHBI1, PHCI1) of the first to third integrators (integrators 61 to 63), and obtains the first to third phase differences. The phase difference is obtained by performing the averaging process of the phase difference of 3.

According to the present embodiment, the first to nth phase differences are obtained based on n integral values based on n characteristics having different phases, and the averaging of the first to nth phase differences is performed. The phase difference is obtained. By such averaging processing, the variation of the integrator can be averaged and the non-linearity between the input phase difference and the output phase difference can be reduced.

Further, in the present embodiment, the clock signal generation unit has a first phase clock signal (CKAI1 in FIG. 12) and a second phase clock signal (CKAQ1 in FIG. 12) which are 90 degrees out of phase with each other based on the reference clock signal RFCK. ) Is generated. The integrator processing unit 60 uses the integrator for the first phase (integrator 61 in FIG. 11) that performs integrative processing based on the integrator of the first phase and the input signal SG1 and the integrator 61 of the second phase in the integrator and the input signal SG1. It has an integrator for the second phase (integrator 64 in FIG. 11) that performs integrator processing based on the above. The measuring unit 30 (correction processing unit 36 in FIG. 16) performs correction processing for correcting the variation between the integrator for the first phase and the integrator for the second phase, and measures the phase difference.

Specifically, the measuring unit 30 makes corrections for reducing the full-scale variation between the integrator for the first phase and the integrator for the second phase, and for the integrator for the first phase and the integrator for the second phase. At least one of the corrections for reducing the offset variation between the integrators is performed as the correction process.

As will be described later in FIGS. 19 and 20, the variation between the integrator for the first phase and the integrator for the second phase reduces the linearity of the output phase difference with respect to the input phase difference (non-linearity occurs). )there is a possibility. In this regard, according to the present embodiment, the correction process for correcting the variation between the integrator for the first phase and the integrator for the second phase is performed, so that the phase difference is calculated by the integrated value after the correction process. By finding it, the linearity of the output phase difference with respect to the input phase difference can be improved.

Further, in the present embodiment, the measuring unit 30 includes a second selector (selector 31 in FIG. 16), an A / D conversion circuit (A / D conversion circuit 32 in FIG. 16), and a processing unit (processing unit in FIG. 16). 33) and. The second selector selects either the output signal of the integrator for the first phase or the output signal of the integrator for the second phase. The A / D conversion circuit A / D-converts the signal (MXQ) from the second selector, and A / D-converted the output signal of the integrator for the first phase and the output of the integrator for the second phase. The phase difference data (ADQ) which is a signal is output. The processing unit performs correction processing on the phase difference data, and obtains the phase difference based on the phase difference data after the correction processing.

In this way, the output signal of the integrator of the first phase and the output signal of the integrator of the second phase can be A / D converted into time division. As a result, the circuit scale can be saved. Further, by performing such A / D conversion, the phase difference (time difference) can be obtained based on the output signal (integrated value) of the integrator by digital signal processing. Further, by performing the correction processing by the digital signal processing, the variation correction of the integrator can be realized with a simple configuration.

2. Second Configuration Example FIG. 5 is a second configuration example of the circuit device of the present embodiment. The circuit device 100 of FIG. 5 includes a first phase difference signal output unit 10, a second phase difference signal output unit 20, a measurement unit 30, and a counter 110. The present embodiment is not limited to the configuration shown in FIG. 5, and various modifications such as omitting a part of the component (for example, counter 110 or the like) or adding another component can be performed. is there.

The first phase difference signal output unit 10 includes a pulse signal generation unit 40 (first pulse signal generation unit) and an integration processing unit 60 (first integration processing unit). The pulse signal generation unit 40 generates a pulse signal PSG1 (first pulse signal) having a pulse width corresponding to the pulse width of the reference clock signal RFCK based on the input signal SG1 (first signal). The integration processing unit 60 performs integration processing based on the reference clock signal RFCK and the pulse signal PSG1 to generate a phase difference signal PH1 (first phase difference signal) representing the phase difference between the reference clock signal RFCK and the input signal SG1. ..

The second phase difference signal output unit 20 includes a second pulse signal generation unit 70 and a second integration processing unit 80. The second pulse signal generation unit 70 generates a second pulse signal PSG2 having a pulse width corresponding to the pulse width of the reference clock signal RFCK based on the second signal SG2. The second integration processing unit 80 performs integration processing based on the reference clock signal RFCK and the second pulse signal PSG2, and the second phase difference signal PH2 representing the phase difference between the reference clock signal RFCK and the second signal SG2. To generate.

The counter 110 counts the number of clocks of the reference clock signal RFCK from the time when the input signal SG1 becomes active until the second signal SG2 becomes active. Then, the measuring unit 30 measures the time difference between the input signal SG1 and the second signal SG2 based on the count value CNQ of the counter 110, the phase difference signal PH1 and the second phase difference signal PH2.

FIG. 6 is a timing chart illustrating the operation of the circuit device of the second configuration example. The counter 110 detects that the input signal SG1 has become active and starts the counting operation, and detects that the second signal SG2 has become active and stops the counting operation. In the example of FIG. 6, since one clock of the reference clock signal RFCK is input between the rising edge of the input signal SG1 and the rising edge of the second signal SG2, the count value CNQ = 1.

As shown in FIG. 6, it is assumed that the phase difference between the input signal SG1 and the reference clock signal RFCK is detected as 60 degrees, and the phase difference between the second signal SG2 and the reference clock signal RFCK is detected as 270 degrees. In this case, the measuring unit 30 determines the phase difference between the input signal SG1 and the second signal SG2 as −60 degrees + (CNQ × 360 degrees) + 270 degrees. Since CNQ = 1 in FIG. 6, the phase difference between the input signal SG1 and the second signal SG2 is 570 degrees. The measuring unit 30 outputs a digital value representing a phase difference of 570 degrees between the input signal SG1 and the second signal SG2 as time difference data TQ. Alternatively, when one cycle of the reference clock signal RFCK is TRF, the phase difference 570 degrees is converted into the time difference TDF = (570 degrees / 360 degrees) × TRF, and the time difference data TQ representing the time difference TDF is output.

When the second signal SG2 is input before the input signal SG1, the counter 110 detects that the second signal SG2 has become active and starts the counting operation, and the input signal SG1 becomes active. Detects that the value has become and stops the counting operation. In this case, the sign of the count value CNQ is made negative.

According to the present embodiment, the phase difference between the reference clock signal RFCK and the input signal SG1 (first signal) is detected, the phase difference between the reference clock signal RFCK and the second signal SG2 is detected, and the phase difference between them is determined. Based on this, the time difference between the transition timings of the input signal SG1 and the second signal SG2 is measured. Thereby, even when the time digital conversion circuit does not spontaneously generate the input signal SG1 (for example, the start signal), the time difference between the transition timings of the input signal SG1 and the second signal SG2 can be measured.

Further, in the conventional phase difference detection method, since the integration process is performed by the sensor, it is difficult to widen the dynamic range (measureable phase difference, distance, and time range). In this regard, according to the present embodiment, the phase difference between the input signal SG1 (first signal) and the second signal SG2 is larger than 360 degrees (the time difference is larger than one cycle of the reference clock signal RFCK). Can also detect the phase difference. This makes it possible to measure a wide dynamic range.

3. 3. Detailed Configuration Example FIG. 7 is a detailed configuration example of the circuit device of the present embodiment. The circuit device 100 includes a phase difference signal output unit 10 (phase difference signal output circuit), a measurement unit 30, and a clock signal generation unit 120 (clock signal generation circuit). The present embodiment is not limited to the configuration shown in FIG. 7, and various modifications such as omitting a part of the constituent elements or adding other constituent elements can be performed.

The clock signal generation unit 120 generates clock signals RFCK2, CKI, and CKQ from the clock signal MCK (master clock signal). The clock signal RFCK2 is a clock signal having a frequency twice that of the reference clock signal RFCK. The clock signals CKI and CKQ are clock signals (multiphase clock signals) whose phase is shifted from the reference clock signal RFCK. The clock signal MCK is a clock signal having a frequency higher than that of the reference clock signal RFCK, and is a clock signal generated inside the circuit device 100 or a clock signal supplied from the outside of the circuit device 100. For example, the clock signal generation unit 120 is composed of a frequency divider and the like.

The phase difference signal output unit 10 includes a selector 15, a DLL circuit 130, and an integration processing unit 60. The DLL circuit 130 includes a pulse signal generation unit 40 and a delay control circuit 50.

The selector 15 selects either the input signal SG1 or the clock signal RFCK2, and outputs the selected signal SLQ1. The pulse signal generation unit 40 includes the delay circuit 41 and generates the pulse signal PSG1 whose pulse width is set by the delay time of the delay circuit 41. The delay control circuit 50 outputs a control signal CT1 that controls the delay time of the delay circuit 41, and controls the delay time so that it becomes the pulse width of the reference clock signal RFCK. For example, the delay circuit 41 is a circuit in which a plurality of delay elements are connected in series. The delay element is, for example, an inverter and a variable capacitance capacitor (load capacitance) provided at the output of the inverter. Then, the capacitance value of the variable capacitance capacitor is controlled by the control signal CT1, and the delay time of the delay circuit 41 is controlled. The delay control circuit 50 is a control signal based on the phase difference detection unit 51 (phase difference detection circuit) that detects the phase difference between the output signal DLQ1 of the delay circuit 41 and the clock signal RFCK2 and outputs the signal DT1 and the signal DT1. It includes a control unit 52 (control circuit) that outputs CT1. The integration processing unit 60 performs integration processing based on the pulse signal PSG1 and the clock signals CKI and CKQ, and outputs the phase difference signal PH1.

FIG. 8 is a flowchart illustrating the operation of the circuit device of the detailed configuration example. When the operation is started, the measurement unit 30 (processing unit 33 in FIG. 16) sets the pulse width measurement mode (S1). In the pulse width measurement mode, the phase difference signal output unit 10 measures (locks) the delay time (delay amount) of the delay circuit by measuring the pulse width of the reference clock signal RFCK.

FIG. 9 is a diagram illustrating the operation of the phase difference signal output unit in the pulse width measurement mode. Note that FIG. 9 illustrates the components related to the operation, and the other components are not shown.

In the pulse width measurement mode, the selector 15 selects the clock signal RFCK2 and outputs it as the signal SLQ1. The delay circuit 41 outputs the signal DLQ1 in which the signal SLQ1 (= RFCK2) is delayed. The phase difference detection unit 51 detects the phase difference between the clock signal RFCK2 and the signal DLQ1, and outputs a signal DT1 representing the detected phase difference. Based on the signal DT1, the control unit 52 generates the control signal CT1 so that the phase difference between the clock signal RFCK2 and the signal DLQ1 becomes zero. Since the frequency of the clock signal RFCK2 is twice the frequency of the reference clock signal RFCK, the delay time of the delay circuit 41 is a half cycle of the reference clock signal RFCK (when the duty of the reference clock signal RFCK is 50%, the reference clock signal RFCK Locked to the width of the high pulse).

As shown in FIG. 8, the measuring unit 30 sets a phase difference detection mode for detecting the phase difference between the reference clock signal RFCK and the input signal SG1 (S2).

FIG. 10 is a diagram illustrating the operation of the phase difference signal output unit in the phase difference detection mode. Note that FIG. 10 illustrates the components involved in the operation, and the other components are not shown.

The pulse signal generation unit 40 includes a delay circuit 41, a latch circuit 42, and a NOR circuit 43. In the phase difference detection mode, the selector 15 selects the input signal SG1 and outputs it as the signal SLQ1. The latch circuit 42 captures a high level at the rising edge of the signal SLQ1 (= SG1), changes the signal LQ1 from low level to high level, and changes the signal LQB1 (logical inversion signal of LQ1) from high level to low level. .. The delay circuit 41 delays the signal LQ1 by the delay time set by the control signal CT1 and outputs the signal DLQ1. The control signal CT1 maintains the value set in the pulse width measurement mode. The NOR circuit 43 outputs the NOR signal of the signal LQB1 and the signal DLQ1 as the pulse signal PSG1. The value set in the pulse width measurement mode is maintained for the control signal CT1, and the pulse width of the pulse signal PSG1 becomes the same as the pulse width of the reference clock signal RFCK. The integration processing unit 60 performs integration processing based on the pulse signal PSG1 and outputs a phase difference signal PH1.

As shown in FIG. 8, the measuring unit 30 A / D-converts the phase difference signal PH1 output in the phase difference detection mode into the phase difference data (S3). Next, the measuring unit 30 obtains the phase difference (time difference) of the transition timing between the reference clock signal RFCK and the input signal SG1 from the phase difference data by digital signal processing (S4).

4. Integral processing unit FIG. 11 is a detailed configuration example of the integral processing unit. The integrator processing unit 60 includes integrators 61 to 66 (a plurality of integrators, first to sixth integrators).

The clock signal generation unit 120 generates clock signals CKAI, CKBI, CKCI, CKAQ, CKBQ, and CKCQ and supplies them to the integrators 61, 62, 63, 64, 65, and 66. The clock signals CKAI, CKBI, and CKCI correspond to the clock signals CKI of FIG. 7, and the clock signals CKAQ, CKBQ, and CKCQ correspond to the clock signals CKQ of FIG. The integrators 61, 62, 63, 64, 65, 66 perform integration processing based on the supplied clock signal and pulse signal PSG1, and output integrated values PHAI1, PHBI1, PHCI1, PHAQ1, PHBQ1, and PHCQ1. The integrated values PHAI1, PHBI1, PHCI1, PHAQ1, PHBQ1, and PHCQ1 correspond to the phase difference signal PH1 in FIG.

FIG. 12 is a timing chart of the clock signal generated by the clock signal generation unit.

Clock signals Each of CKAI, CKBI, CKCI, CKAQ, CKBQ, and CKCQ is a combination of two clock signals whose phases are inverted (phases differ by 180 degrees). For example, the clock signal CKAI is composed of clock signals CKAI1 and CKAI2. The 12 clock signals are multi-phase clock signals that are out of phase by 30 degrees (= 360 degrees / 12) with respect to the reference clock signal RFCK.

Specifically, the clock signal CKAI1 has the same phase as the reference clock signal RFCK, and the clock signals CKBI1 and CKCI1 are delayed by 120 degrees and 240 degrees from the reference clock signal RFCK. The clock signals CKAQ1, CKBQ1, and CKCQ1 are 90 degrees out of phase with the clock signals CKAI1, CKBI1, and CKCI1. The phases of the clock signals CKAI2, CKBI2, CKCI2, CKAQ2, CKBQ2, and CKCQ2 are inverted with respect to the clock signals CKAI1, CKBI1, CKCI1, CKAQ1, CKBQ1, and CKCQ1 (the phases are 180 degrees different).

13 to 15 are diagrams showing the characteristics of the integrated value of the integral processing by the polymorphic clock. The phase difference on the horizontal axis is the phase difference between the reference clock signal RFCK and the input signal SG1. As described with reference to FIG. 12, the phases of the clock signals CKAI, CKBI, and CKCI are 0 degrees, 120 degrees, and 240 degrees with reference to the reference clock signal RFCK. Therefore, as shown in FIGS. 13 to 15, the characteristics of the integrated values PHBI1 and PHCI1 deviate from the characteristics of the integrated value PHAI1 by 120 degrees and 240 degrees. Similarly, the characteristics of the integrated values PHBQ1 and PHCQ1 deviate from the characteristics of the integrated value PHAQ1 by 120 degrees and 240 degrees.

The measuring unit 30 obtains the first phase difference from the integrated values PHAI1 and PHAQ1, obtains the second phase difference from the integrated values PHBI1 and PHBQ1, and obtains the third phase difference from the integrated values PHCI1 and PHCQ1. Then, the average value of the first to third phase differences is obtained as the phase difference between the input signal SG1 and the reference clock signal RFCK.

Ideally, the output phase difference having a characteristic linear with respect to the input phase difference can be obtained only with the set of the integrated values PHAI1 and PHAQ1. The input phase difference is the phase difference between the input reference clock signal RFCK and the input signal SG1, and the output phase difference is the phase difference based on the integration process. However, there is a possibility that the input phase difference and the output phase difference will not be linear due to the error of the integrator (for example, the full-scale error of the integrated value, the offset, etc.).

In this regard, in the present embodiment, a plurality of phase differences (first to third phase differences) are obtained by performing integration processing with polyphase clocks having different phases, and the plurality of phase differences are averaged. The non-linearity between the phase difference and the output phase difference can be averaged. For example, when the input phase difference is 180 degrees, the characteristic of the integrated value PHAI1 in FIG. 13 is a point that folds back at −VP. Non-linearity is likely to occur at the point where such characteristics are folded back. However, in FIGS. 14 and 15, the characteristics of the integrated values PHBI1 and PHCI1 at a phase difference of 180 degrees are linear. Therefore, the non-linearity can be reduced by averaging the first to third phase differences.

5. Measuring unit FIG. 16 is a detailed configuration example of the measuring unit. The measuring unit 30 includes a selector 31 (multiplexer), an A / D conversion circuit 32, and a processing unit 33 (digital signal processing unit, processing circuit, logic circuit).

Integral values PHAI1, PHAQ1, PHBI1, PHBQ1, PHCI1, and PHCQ1 are input to the selector 31 from the phase difference signal output unit 10. The selector 31 selects these signals one by one in a time division manner, and outputs the selected signal as a signal MXQ. The A / D conversion circuit 32 A / D-converts the integrated values PHAI1, PHAQ1, PHBI1, PHBQ1, PHCI1, and PHCHQ1 input as the signal MXQ into time divisions, and the A / D-converted integrated value (integrated data). Is output as data ADQ. The processing unit 33 obtains the time difference data TQ based on the data ADQ by digital signal processing.

Specifically, the processing unit 33 includes a phase difference calculation unit 34 and a correction processing unit 36. The correction processing unit 36 performs correction processing for correcting the variation correction of the integrator on the A / D converted integrated values PHAI1, PHAQ1, PHBI1, PHBQ1, PHCI1, and PHCQ1. This correction process will be described later in FIGS. 19 to 21. The phase difference calculation unit 34 obtains the first phase difference from the corrected integrated values PHAI1 and PHAQ1, obtains the second phase difference from the corrected integrated values PHBI1 and PHBQ1, and corrects the integrated value PHCI1. , The third phase difference is obtained from PHCQ1. The phase difference calculation unit 34 averages the first to third phase differences to obtain the phase difference between the input signal SG1 and the reference clock signal RFCK. The processing unit 33 outputs the time difference data TQ based on the phase difference. The method of converting the phase difference into the time difference is the same as the method described with reference to FIG. 2 and the like.

6. The integrator FIG. 17 is a detailed configuration example of the integrator. Further, FIG. 18 is a timing chart illustrating the operation of the integrator. Although the integrator 61 of FIG. 11 will be described here as an example, other integrators (integrators 62 to 66 of FIG. 11) have the same configuration.

As shown in FIG. 17, the integrator 61 includes an integrator signal generation unit GIS, a current generation unit IGEN, and an integrator unit CINT.

The integration signal generation unit GIS generates integration signals INCKA and INCKB from the pulse signal PSG1 and the clock signals CKAI (CKAI1, CKAI2). As shown in FIG. 18, the logical product of the pulse signal PSG1 and the clock signal CKAI1 is output as the integrated signal INCKA, and the logical product of the pulse signal PSG1 and the clock signal CKAI2 is output as the integrated signal INCKB.

The current generation unit IGEN generates currents IP and IN based on the integration signals INCKA and INCKB, and supplies the currents IP and IN to the input nodes NINP and NINN of the integration unit CINT. Specifically, when the integration signal INCKA is high level (active) and the integration signal INCKB is low level (inactive), the switch elements SWA1 and SWA2 are turned on, and the switch elements SWB1 and SWB2 are turned off. become. Then, a negative current having a constant current value is supplied to the node NINP as a current IP from the current source IBB, and a positive current having a constant current value is supplied to the node NINN as a current IN from the current source IBA, so that IP-IN <0. On the other hand, when the integration signal INCKA is low level (inactive) and the integration signal INCKB is high level (active), the switch elements SWA1 and SWA2 are turned off, and the switch elements SWB1 and SWB2 are turned on. Then, a positive current having a constant current value is supplied to the node NINP as a current IP from the current source IBA, and a negative current having a constant current value is supplied to the node NINN as a current IN from the current source IBB, and IP-IN> 0.

The integrating unit CINT integrates the differentially input currents IP and IN, and differentially outputs the integrated values as voltages VOUT and VOUTN. That is, charge-voltage conversion is performed to convert the electric charge supplied by the currents IP and IN into the voltages VOUTP and VOUTN. The integrator CINT performs inverting amplification that converts a negative input charge into a positive voltage. That is, when the integration signal INCKA is at a high level and the integration signal INCKB is at a low level, since IP-IN <0 as described above, the voltages VOUTP and VOUTN increase in the direction in which VOUTP-VOUTN increases as shown in FIG. Changes. On the other hand, when the integration signal INCKA is at a low level and the integration signal INCKB is at a high level, IP-IN> 0 as described above, so that the voltages VOUTP and VOUTN decrease in the direction in which VOUTP-VOUTN decreases as shown in FIG. Changes. In this way, the pulse signal PSG1 is converted into the integrated value PHAI1, and the characteristics of the integrated value PHAI1 shown in FIG. 13 are obtained.

In the integrating unit CINT, when the control signal APCK (clock signal) is low level (inactive) and the control signal XAPCK (clock signal) which is a logical inversion signal of the control signal APCK is high level (active), the switch element. SWP1 to SWP4 are turned off, and switch elements SWP5 to SWP8 are turned on. In this case, the capacitors CP1 to CP4 and the amplifier circuit AMP form a differential integrator circuit (differential charge-voltage conversion circuit), and the above-mentioned integration operation is performed. On the other hand, when the control signal APCK is at a high level (active) and the control signal XAPCK is at a low level (inactive), the switch elements SWP1 to SWP4 are turned on and the switch elements SWP5 to SWP8 are turned off. In this case, the input nodes NINP and NINN are set to the common voltage VCM, the input charge is reset, and the voltages VOUTP and VOUTN are reset to the common voltage VCM.

7. Correction of integrator variation FIG. 19 is a diagram illustrating variations in the characteristics of integrated values among integrators. FIG. 20 is an example of the characteristics of the output phase difference with respect to the input phase difference.

As shown in FIG. 19, it is assumed that the upper limit of the change range of the integrated value PHAQ1 is + VP and the lower limit is −VP. That is, it is assumed that the full scale (output full scale) of the integrated value PHAQ1 is 2VP. At this time, it is ideal that the integrated value PHAI1 is also the same full-scale 2VP as in the integrated value PHAI1'. In this ideal case, as shown in the characteristic CHA of FIG. 20, the output phase difference has a linear characteristic with respect to the input phase difference.

However, as shown in FIG. 19, the full scale of the integrated value PHAI1 may be 2VP'≠ 2VP. For example, in FIG. 17, the magnitude of the current output by the current sources IBA and IBB is large. The variation between the integrators causes a full-scale variation between the integrators. When such a full-scale variation occurs, the output position is relative to the input phase difference as shown in the characteristic CHA'in FIG. The phase difference has a non-linear characteristic.

Moreover, not only full-scale variation but also offset variation may occur. Due to the variation in offset, the output phase difference may have a non-linear characteristic with respect to the input phase difference.

FIG. 21 is a diagram illustrating variation correction of the integrator. Although the pulse signal PSG1 is shown in FIG. 21 for reference, the pulse signal PSG1 does not have to be supplied to the integrator at the time of variation correction.

As shown in FIG. 21, the circuit device 100 performs upper limit measurement, lower limit measurement, and offset measurement for each integrator. These measurements are performed before measuring the phase difference (time difference) between the reference clock signal RFCK and the input signal SG1. For example, this is performed when the power of the circuit device 100 is turned on.

At the time of upper limit measurement, the integration signal generation unit GIS outputs an integration signal INCKA that has the same pulse width as the pulse signal PSG1 and has a high level, and outputs a low-level integration signal INCKB. Since this corresponds to measuring the upper limit of the integrated value, for example, in FIG. 19, + VP'is obtained as the integrated value. At the time of lower limit measurement, the integration signal generation unit GIS outputs a low-level integration signal INCKA and outputs an integration signal INCKB that becomes a high level with the same pulse width as the pulse signal PSG1. Since this corresponds to measuring the lower limit of the integrated value, for example, in FIG. 19, -VP'is obtained as the integrated value. At the time of offset measurement, the integration signal generation unit GIS outputs low-level integration signals INCKA and INCKB. Since this corresponds to measuring the offset of the integrated value, for example, in FIG. 19, 0 is obtained as the integrated value.

The upper limit of the integrated value obtained in the above measurement is IMAX, the lower limit is IMIN, the offset is IOF, and the expected value of full scale is FLS. Further, the integrated value obtained when the time difference between the reference clock signal RFCK and the input signal SG1 is measured is defined as MES. The processing unit 33 of the measuring unit 30 obtains the corrected integrated value MES'by, for example, MES'= (FLS / (IMAX-IMIN)) × (MES-IOF). For example, in the example of FIG. 19, MES'= (VP / VP') × MES. Such correction is made for each integrator. Then, the phase difference is obtained based on the corrected integral value, and the time difference is obtained based on the phase difference.

The integrated value may be corrected by the measured values of the upper limit and the lower limit without performing the offset measurement. In this case, MES'= (FLS / (IMAX-IMIN)) × MES.

8. Example of application to PLL FIG. 22 is a configuration example of a circuit device when the method of this embodiment is applied to a PLL (Phase Locked Loop). The circuit device 100 of FIG. 22 includes a phase comparison unit 260 (phase comparison circuit), a processing unit 250 (processing circuit), a digitally controlled oscillator 230, and a frequency divider 240.

The phase comparison unit 260 includes the pulse signal generation unit 40, the integration processing unit 60, and the measurement unit 30 described with reference to FIGS. 1, 7, and the like. The reference clock signal CKIN and the frequency dividing clock signal CKDV are input to the phase comparison unit 260. The reference clock signal CKIN is input to the clock signal generation unit 120 as the master clock signal MCK of FIG. 7. Further, the frequency dividing clock signal CKDV is input to the pulse signal generation unit 40 as an input signal SG1. The phase comparison unit 260 detects the phase difference between the reference clock signal RFCK (CKIN) and the divided clock signal CKDV, and outputs the time difference data TQ corresponding to the phase difference.

The processing unit 250 generates oscillation control data CTD based on the time difference data TQ. The value of the oscillation control data CTD is controlled so that the phase difference between the reference clock signal RFCK (CKIN) and the frequency-divided clock signal CKDV becomes zero (approaches zero).

The digitally controlled oscillator 230 generates a clock signal CKOUT with an oscillation frequency corresponding to the oscillation control data CTD. For example, the digitally controlled oscillator 230 is an oscillator that oscillates the oscillator at an oscillation frequency corresponding to the oscillation control data CTD. For example, the digital control oscillator 230 includes a D / A conversion circuit that D / A-converts oscillation control data CTD, and a voltage-controlled oscillator that oscillates at an oscillation frequency corresponding to the output voltage (control voltage) of the D / A conversion circuit. ,including.

The frequency divider 240 divides the clock signal CKOUT generated by the digitally controlled oscillator 230 by a predetermined division ratio, and returns the divided clock signal CKDV to the phase comparison unit 260.

9. Physical quantity measuring device, electronic device, mobile body FIG. 23 is a configuration example of a physical quantity measuring device including the circuit device of the present embodiment. The physical quantity measuring device 200 includes a signal supply unit 210 (signal supply circuit), a circuit device 100, and a processing unit 220 (processing circuit, processing device). The present embodiment is not limited to the configuration shown in FIG. 23, and various modifications such as omitting a part of the component (for example, a signal supply unit) or adding another component can be performed. is there.

The physical quantity measuring device 200 of FIG. 23 is a device that measures various physical quantities based on the result of time digital conversion. For example, the physical quantity to be measured is, but is not limited to, time, distance, and the like.

The signal supply unit 210 receives the reference clock signal RFCK from the circuit device 100, and supplies the input signal SG1 to the circuit device 100. The reference clock signal RFCK is generated, for example, by the clock signal generation unit 120 of FIG. For example, when the physical quantity measuring device 200 is a distance measuring sensor, the signal supply unit 210 includes a light emitting unit, a light receiving unit, and a control unit. Then, the control unit generates a transmission signal based on the reference clock signal RFCK, and causes the light emitting unit to emit light by the transmission signal. Further, the control unit generates a received signal by waveform-forming the received signal from the light receiving unit, and supplies the received signal as an input signal SG1 to the circuit device 100.

The circuit device 100 measures the time difference between the transition timings of the reference clock signal RFCK and the input signal SG1, and outputs the time difference data TQ. The processing unit 220 performs various digital signal processing based on the time difference data TQ. For example, the processing unit 220 performs a process of converting the time difference data TQ into a physical quantity, and outputs the data of the physical quantity.

The configuration of the physical quantity measuring device including the circuit device of the present embodiment is not limited to FIG. 23. For example, the physical quantity measuring device may include the PLL of FIG. 22, and may include a physical quantity measuring circuit that operates based on the clock signal CKOUT output by the PLL to measure the physical quantity.

FIG. 24 is a configuration example of an electronic device including the circuit device of the present embodiment. The electronic device 300 includes a circuit device 100, an antenna ANT, a communication unit 510 (communication device), and a processing unit 520 (processing device). Further, the operation unit 530 (operation device), the display unit 540 (display device), and the storage unit 550 (memory) can be included. For example, a physical quantity measuring device is composed of a circuit device 100 and a processing unit 520. Alternatively, the circuit device 100 may include a PLL as shown in FIG. The electronic device 300 is not limited to the configuration shown in FIG. 24, and various modifications such as omitting some of these components (for example, antenna ANT, communication unit 510, etc.) or adding other components can be performed. It is possible.

As the electronic device 300 of FIG. 24, for example, an in-vehicle electronic device such as an ECU (Electronic Control Unit), an ultrasonic measuring device such as a medical or industrial ultrasonic inspection device, and radio waves or ultrasonic waves are used. You can imagine a radar. Further, as the electronic device 300, a game device, a video device such as a digital camera or a video camera, a mobile information terminal (mobile terminal) such as a smartphone, a mobile phone, a portable game device, a notebook PC or a tablet PC, and contents can be used. Various devices such as content providing terminals to be distributed or network-related devices such as base stations or routers can be assumed.

The communication unit 510 (wireless circuit) performs a process of receiving data from the outside or transmitting data to the outside via the antenna ANT. The processing unit 520 performs control processing of the electronic device 300 and various digital processes of data transmitted and received via the communication unit 510. For example, the circuit device 100 outputs the time difference data, and the processing unit 520 performs digital processing using the time difference data. Alternatively, the circuit device 100 may output a clock signal by the PLL, and each part of the electronic device 300 may operate based on the clock signal. The function of the processing unit 520 can be realized by a processor such as a microcomputer. The operation unit 530 is for the user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information, and can be realized by a display such as a liquid crystal or an organic EL. When a touch panel display is used as the operation unit 530, the touch panel display also has the functions of the operation unit 530 and the display unit 540. The storage unit 550 stores data, and its function can be realized by a semiconductor memory such as RAM or ROM, an HDD (hard disk drive), or the like.

FIG. 25 shows an example of a mobile body including the circuit device of the present embodiment. The circuit device 100 (physical quantity measuring device, PLL) of the present embodiment can be incorporated into various moving objects such as a car, an airplane, a motorcycle, a bicycle, or a ship. A moving body is a device / device that is provided with, for example, a drive mechanism such as an engine or a motor, a steering mechanism such as a handle or a rudder, and various electronic devices (vehicle-mounted devices), and moves on the ground, in the air, or on the sea. FIG. 25 schematically shows an automobile 206 as a specific example of a moving body. For example, the automobile 206 incorporates a physical quantity measuring device (not shown) having the circuit device 100 of the present embodiment. The control device 208 operates based on the physical quantity generated by this physical quantity measuring device. For example, the control device 208 may be an ECU that performs driving assist control or automatic driving control according to the distance between the automobile 206 and the object. Alternatively, the automobile 206 incorporates a circuit device 100 including a PLL as shown in FIG. The control device 208 performs various controls based on the clock signal output by the PLL. The device into which the circuit device and the physical quantity measuring device of the present embodiment are incorporated is not limited to such a control device 208, and can be incorporated into various devices (vehicle-mounted devices) provided in a moving body such as an automobile 206. Is.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present invention are possible. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present invention. Further, the configuration / operation of the circuit device, the physical quantity measuring device, the electronic device, the moving body, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

10 ... Phase difference signal output unit, 15 ... Selector, 20 ... Second phase difference signal output unit,
30 ... Measuring unit, 31 ... Selector, 32 ... A / D conversion circuit, 33 ... Processing unit,
34 ... Phase difference calculation unit, 36 ... Correction processing unit, 40 ... Pulse signal generation unit, 41 ... Delay circuit,
42 ... Latch circuit, 43 ... NOR circuit, 50 ... Delay control circuit, 51 ... Phase difference detector,
52 ... control unit, 60 ... integrator processing unit, 61-66 ... integrator,
70 ... 2nd pulse signal generation unit, 80 ... 2nd integration processing unit, 100 ... circuit device,
110 ... counter, 120 ... clock signal generator, 130 ... DLL circuit,
200 ... Physical quantity measuring device, 206 ... Automobile (moving body), 208 ... Control device,
210 ... Signal supply unit, 220 ... Processing unit, 230 ... Digitally controlled oscillator,
240 ... frequency divider, 250 ... processing unit, 260 ... phase comparison unit, 300 ... electronic equipment,
510 ... Communication unit, 520 ... Processing unit, 530 ... Operation unit, 540 ... Display unit, 550 ... Storage unit,
CKAI1 ... 1st clock signal (1st phase clock signal),
CKAQ1 ... Phase 2 clock signal, CKBI1 ... Second clock signal,
CKCI1 ... 3rd clock signal, PH1 ... phase difference signal, PH2 ... second phase difference signal,
PSG1 ... pulse signal, PSG2 ... second pulse signal, RFCK ... reference clock signal,
SG1 ... Input signal (first signal), SG2 ... Second signal, TDF ... Time difference,
TH ... pulse width, TPS ... pulse width, TQ ... time difference data

Claims (11)

A pulse signal generator that generates a pulse signal with a pulse width corresponding to the pulse width of the reference clock signal based on the input signal.
An integration processing unit that performs integration processing based on the reference clock signal and the pulse signal and generates a phase difference signal representing the phase difference between the reference clock signal and the input signal.
A circuit device characterized by including. In the circuit device according to claim 1,
Including delay control circuit
The pulse signal generator has a delay circuit and
The delay control circuit
A circuit device characterized in that the delay time of the delay circuit is set to a delay time corresponding to the pulse width of the reference clock signal. In the circuit device according to claim 2.
A circuit device characterized in that, in the pulse width measurement mode, the reference clock signal is output to the delay circuit, and in the phase difference detection mode, the pulse signal generation unit includes a selector that outputs the input signal. In the circuit device according to any one of claims 1 to 3.
when 2 or more integer and the n, based on the reference clock signal includes a clock signal generator for generating a first to clock signal of the n-th phases different from each other,
The integrator processing unit has first to nth integrators.
Wherein each of the integrators of the first to n-th circuit and wherein the TURMERIC line integration processing based on the clock signal and the common of said input signal of said first to n. In the circuit device according to claim 4,
A circuit device including a measuring unit for measuring the phase difference between the reference clock signal and the input signal based on the output signals of the first to nth integrators. In the circuit device according to claim 5,
The clock signal generator
When i was a an integer from 1 to n, the first to as the clock signal of the i of the n clock signals, the phase with respect to the reference clock signal (i-1) × Δθ different clock Generate a signal,
The i-th integrator of the first to nth integrators is
Integral processing based on the i-th clock signal and the pulse signal is performed.
The measuring unit
The first to nth phase differences are obtained based on the output signals of the first to nth integrators, and the first to nth phase differences are averaged to obtain the phase differences. Circuit equipment. In the circuit device according to any one of claims 1 to 3.
A clock signal generator that generates a first-phase clock signal and a second-phase clock signal that are 90 degrees out of phase with each other based on the reference clock signal.
The measuring unit that measures the phase difference and
Including
The integration processing unit
An integrator for the first phase that performs integration processing based on the clock signal of the first phase and the input signal, and an integrator for the second phase that performs integration processing based on the clock signal of the second phase and the input signal. And have
The measuring unit
In order to reduce at least one of the full-scale variation and the offset variation between the integrator for the first phase and the integrator for the second phase, the integrator for the first phase and the integrator for the second phase There line correction processing to correct the integral value integrator is output, the using the integral value after the correction processing, the circuit device characterized by measuring the phase difference. In the circuit device according to claim 7.
The measuring unit
A second selector that selects either the output signal of the integrator for the first phase or the output signal of the integrator for the second phase, and
The signal from the second selector is A / D converted, and the phase difference data which is the output signal of the integrator for the first phase and the output signal of the integrator for the second phase obtained by A / D conversion is obtained. The output A / D conversion circuit and
A processing unit that performs the correction process on the phase difference data and obtains the phase difference based on the phase difference data after the correction process.
A circuit device characterized by having. A physical quantity measuring device comprising the circuit device according to any one of claims 1 to 8. An electronic device comprising the circuit device according to any one of claims 1 to 8. A mobile body including the circuit device according to any one of claims 1 to 8.

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