SU1645952A1 - Device for linearization frequency sensor conversion characteristics - Google Patents

Abstract

The invention relates to information-measuring and computing devices. The purpose of the invention is to enhance the functionality by implementing the operation of extracting the square root of a square binomial by implementing the reversibility property of reciprocal functions. To achieve the goal, a frequency converter is entered into the device — a code, the bottom is not a speaker, two pulse drivers, a short-circuit trigger, three AND elements, an OR element, and a reversible counter. I il. g (/)

Description

The invention relates to information-measuring and computing devices and can be used to linearize the measurement paths of frequency sensors with a characteristic of the form of:

- “l

+ kx2,

(ABOUT

Where

Ј „, Ј„ - current and initial values of the frequency of electrical oscillations at the output of the sensor;

k is the coefficient of sensitivity of the sensor according to the measured value x. . The linearization of the measuring path of the sensor with the characteristic described by the expression (1) is carried out using the device

the inverse transformation to (1):

2

X b,

where (4kfM) 2;

(2)

- conversion constants.

The purpose of the invention is to expand the functionality by implementing the operation of extracting a square root from a square binomial. The drawing shows the block diagram of the device.

The device contains a frequency converter 1 - code, one-shot 2, shapers 3 and 4 pulses (rear edge isolation circuits), RS-flip-flop 5, element SHI 6, second code input 7 of the device, reversible counter 8, elements 9 and 10, first code

F

four

cn with

g

device input 1 1, binary frequency multiplier 12, AND elements 13 and 14, OR element 15, odd-numbered block 16, decoder 17 corrections, accumulating adder 18, result counter 19 and digital display unit 20.

The device works as follows.

Linearization is preceded by preparation at inputs 7 and 11 of the reversible counter 8 and the binary multiplier 12 frequencies code equivalents NB and YD, respectively, of the quantities -b and -Ja1, proportional to the calibration constants of the frequency sensor used (NB v (-b); IDl.4a).

When the power is turned on, the output of one vibrator a 2 triggers a pulse Reset, tipping the converter 1 frequency - code, RS-flip-flop 5 (via the element OR 6), block 16 forming odd numbers, accumulating adder 18 and counter 19 of the result and recording the NQ code and Ne coefficients, $ a and -b, prepared at inputs 11 and 7, respectively, into a binary multiplier 12 frequency and a reversible counter 8. The high potential arising at the zero output of the RS flip-flop 5 after its zeroing opens elements And 9 and 13, and a low potential of the single arm of the RS flip-flop 5 zak digs elements And 10 and 14, included at the inputs of the reversible counter 8 and the block 16 forming odd numbers. After the end of the pulses, Reset 1 starts the frequency converter - the code, on the information output of which a burst of N is formed (where & T is the duration of the measurement interval, usually taken equal to 1 s), which are fed to the input of the binary frequency multiplier 12 of the binary frequency multiplier I2, in accordance with its conversion function, a packet of pulses is formed in the amount of Ni-NeN, 4af x which through the open element AND 13 and the element OR 15 enters the input of the odd-numbered block 16 Iselle, is yuschiys digital input squarer comprising in its composition as correction decoder 17 and an accumulator 18. At the carry output of the accumulator

0

five

0

five

0

five

0

five

18, which is the output of the digital quad, forms the square of the input number N5-4afj (pulses

xt t c2 ±. -

N

which, through the open element I 9, arrive at the summing input of the reversible counter 8, where they are added to the previously entered additional code N "A / (- b). As a result, by the end of the conversion of the frequency converter 1 — the code in the reversible counter 8, the difference code N-j-af Ј-b is formed. From the trailing edge of the measurement interval pulse А Т, the shaper of 4 pulses is triggered, the output pulse of which sets the RS-flip-flop 5 into one state. In this case, the low potential of the zero shoulder of the RS flip-flop 5 locks the elements 9 and 13, and the high potential of the single shoulder of the RS flip-flop 5 opens the elements 10 and 14. The pulses of a stable frequency produced by the quartz generator from the output of the converter 1 through the open element I 14 the element OR 15 in the quantity begins to arrive at the input of the digital Quad (input of the block 16), and from the output of the element 14 to the input of the result counter 19.

The pulses in the amount of Nq., Formed at the output of the quad (output of accumulating adder 18), go in this case through the open element 10 to the subtracting input of the reversing counter 8, which contains the difference code N - Ne af b. Element And 10 remains open until the reverse counter 8 is zeroed, after which the pulse at the output of the counter 8 borrowed, passed through the element OR 6, switches the single output of the RS flip-flop to the zero state, which locks And 10 and 14 elements. The subtracting input of counter 8 is equal to N N. N. The moment of zeroing of counter 8 corresponds to the equality N5 Nj-N, whence N. N N N5, or which is the same (taking into account proportional coupling) x - 4af - tf.

The number of pulses NJ-x recorded at this time in counter 19 of the result corresponds to the value of the measured parameter x.

Next, the pulse shaper (highlight of the leading edge of the pulse) is triggered at the single output of the RS flip-flop 5. The output pulse of the shaper 3 triggers a single EI 2, generating a reset pulse, with which a new linearization cycle begins.

The device can be implemented using an industrial frequency meter, for example, 43-33 (block 1) and an K 155 series average integration chip.

Claims (1)

Invention Formula A device for linearizing the conversion characteristics of frequency sensors, containing a binary frequency multiplier, the setup input of which is connected to the first code input of the device, and the output to the first input of the first AND element, the output of which is connected to the first input of the first OR element, whose output is connected to the input of the forming unit odd numbers, the outputs of the group of younger bits of which are connected to the inputs of the correction decoder, the output of which is connected to the transfer input of the accumulating adder, informational inputs Which are connected to the inputs of the group of higher bits of the odd-numbered block, and the result counter, the output of which is connected to the input of the digital display unit, differs in that with the extension circuit of the functionality due to the square root extraction operation He entered the frequency converter - code, RS-trigger, one-shot, three elements AND, the second element OR, two impulse generator and reversible 0 five 0 five 0 five 0 the counter, the information input and output of the frequency converter - the code are connected respectively to the input of the device frequency setting and the information input of the binary frequency multiplier, and the outputs of the pulses of the reference frequency and the measurement interval are connected respectively to the first input of the second element And and to the input of the first pulse shaper, the output of the last of which is connected to the S-input of the RS flip-flop, the R-input of which is connected to the output of the second element OR, the single output to the second input of the second element AND, the first input The third element And through the second pulse shaper - to the input of the one-oscillator, the output of which is connected to the reset inputs of the frequency converter - the code, the binary frequency multiplier, the odd-number formation unit, the accumulating adder and the result counter, as well as the first input of the second element OR and the input of the information input of the reversible counter, the setup input and the output of which are connected to the second code input of the device and the second input of the second OR element, respectively, and the subtracting and summing inputs are Linked to the outputs of the third and fourth And elements, respectively, the combined first and second inputs of which are connected to the transfer output of the accumulating adder, the zero output of the RS flip-flop is connected to the second inputs of the first and fourth elements And, the output of the second element And is connected to the second input of the first element OR and counting input counter result. r