CN106850115B - A kind of Multi-channel data acquisition synchronization system and method - Google Patents
A kind of Multi-channel data acquisition synchronization system and method Download PDFInfo
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- CN106850115B CN106850115B CN201710129590.1A CN201710129590A CN106850115B CN 106850115 B CN106850115 B CN 106850115B CN 201710129590 A CN201710129590 A CN 201710129590A CN 106850115 B CN106850115 B CN 106850115B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The present invention provides a kind of Multi-channel data acquisition synchronization system, the Multi-channel data acquisition synchronization system includes GPS time service module, ARM bottom plate, intelligence sample plate and computer, the serial data and second pulse signal that the GPS time service module sends GPS absolute time are to the ARM bottom plate, the ARM bottom plate receives serial data and second pulse signal and sends intelligence sample plate to after carrying out multichannel fractionation, the intelligence sample plate parsing, record and acquisition data, and transfer data to the computer, the computer receives, it stores and reads the data of intelligence sample plate transmission and draw waveform graph, circuit data is analyzed according to waveform graph.Circuit data acquisition is carried out using Multi-channel data acquisition synchronization system of the present invention, without signal interference between each acquisition channel, each interchannel is provided simultaneously with uniform time reference, and the data precision of acquisition is higher.
Description
Technical field
The present invention relates to extra-high voltage grid measuring device field more particularly to a kind of Multi-channel data acquisition synchronization system and
Method.
Background technique
Currently, in the acquisition of the multi-channel high-speed data of extra-high voltage grid or other power grids, in order to record one simultaneously
The multi-channel data in place analyzes fault point information, needs to acquire multiple devices on-line monitoring data, this is needed in different location
Data acquisition equipment have unified time reference, the circuit data that the synchronization accuracy of multiple devices acquires if not high
Do not have reference analysis value.
Meanwhile having the characteristics that electric current is big, the duration is short in the fault waveform of extra-high voltage grid or other power grids, this
Kind of high frequency, high current data can be generated between each channel of collected data it is serious interfere with each other, such as adopted in 3 channel datas
It concentrates, there is input in one of channel, even if other two channels do not have signal input, also has and very big seals in current perturbation
And voltage, the stability of the crosstalk strong influence instrument work between channel and the accuracy of measurement.
Summary of the invention
In view of this, the embodiment provides a kind of multi-channel datas applied to the acquisition of multi-channel circuit data
Acquire synchronization system.
The present invention provides a kind of Multi-channel data acquisition synchronization system, and the Multi-channel data acquisition synchronization system includes
GPS time service module, ARM bottom plate, intelligence sample plate and computer, the GPS time service module are connect with ARM bottom plate, the bottom ARM
Plate is connect with intelligence sample plate, and the intelligence sample plate is connect with computer, and the GPS time service module receives GPS satellite signal
And the serial data and second pulse signal for sending GPS absolute time, to the ARM bottom plate, the ARM bottom plate receives GPS time service mould
The Serial Port Information and second pulse signal that block is sent, and Serial Port Information and second pulse signal are sent to intelligence sample plate, the letter
Breath sampling plate has multiple, these intelligence sample plates share an ARM bottom plate, the pulse per second (PPS) of the GPS of the GPS time service module sending
Signal and rs 232 serial interface signal are sent to each intelligence sample plate, each intelligence sample plate phase after carrying out multichannel fractionation on ARM bottom plate
Mutually isolation, the intelligence sample plate parsing GPS time service data, record parse the time of GPS time service data and simultaneously Acquisition Circuit
Wave data, each intelligence sample plate detect in its received circuit waveform data whether have overvoltage data, these information
Simultaneously to computer transmitting line waveform number when collection plate at least one of them intelligence sample plate has detected overvoltage data
According to the data transmitted with time data, the computer reception, storage and reading network interface and draw waveform graph.
Further, the intelligence sample plate is equipped with serial ports, FPGA processor, sample circuit, storage unit, network and connects
Mouth, independent current source, the FPGA processor connect with serial ports, sample circuit, storage unit, network interface and independent current source respectively
It connects, the independent current source is connect with ARM bottom plate, the operation power of the independent current source offer intelligence sample plate, at the FPGA
Reception and processing that device carries out data and signal are managed, the serial ports receives the GPS Serial Port Information that ARM bottom plate is sent, and GPS is gone here and there
Message breath is sent to FPGA processor, and GPS second pulse signal is described by being sent to after ARM bottom plate progress multichannel fractionation
FPGA processor, the FPGA processor receives GPS Serial Port Information and second pulse signal carries out the time service of GPS absolute time, described
Interim elapsed time clock and certainly punctual two clocks of elapsed time clock are set in FPGA processor, wherein described in interim elapsed time clock record
FPGA processor receives GPS Serial Port Information to the time data of information successfully resolved, and the certainly punctual elapsed time clock records automorph
When time data, the sample circuit Acquisition Circuit Wave data, the FPGA processor is absolute by circuit waveform data and GPS
Time data and it is automorph when time data saved together to storage unit.
Further, the storage unit includes the first storage unit and the second storage unit, first storage unit
It is interim to save circuit waveform data, GPS absolute time data and certainly punctual chronometric data, when the FPGA processor detects institute
It states when being stored with overvoltage data in the first storage unit, the FPGA processor grabs circuit from first storage unit
Wave data, the time service of GPS absolute time and from punctual chronometric data, and by circuit waveform data, GPS absolute time data and from
Punctual chronometric data is sent in computer by network interface, and the connection of the network interface and computer is unsmooth or transmission is lost
When losing, circuit waveform data, GPS absolute time data and certainly punctual chronometric data are sent to second and deposited by the FPGA processor
It is stored in storage unit, after the success of the connection network of network interface and computer, the FPGA processor is single from the second storage again
In member data are sent to computer through network interface.
Further, first storage unit is DDR cache unit, and second storage unit is TF storage unit.
Further, the GPS time service module can export a whole pulse per second (PPS) PPS in the positive second, and whole pulse per second (PPS) synchronizes essence
It spends up to 100ns.
The embodiment of the present invention also provides a kind of multi-channel data acquisition synchronous method, it is characterised in that: described includes more
Channel data acquires synchronous method following steps:
S1: intelligence sample plate and time service module booting, the sample circuit Acquisition Circuit Wave data, at the FPGA
Reason device is set as automatic time service, and double elapsed time clocks are arranged；Interim elapsed time clock and certainly punctual elapsed time clock, wherein interim timing
Clock is used to record FPGA processor and receives whole second pulse signal to the time interval of parsing GPS absolute time, counts from punctual
Shi Shizhong is counted for system from punctual；
S2: time service starts, and receives GPS second pulse signal and serial data；
The enabled beginning function of time service is set in FPGA processor, when time service starts, in unlatching pulse per second (PPS) interruption and serial ports
Disconnected, FPGA processor receives second pulse signal after unlatching is interrupted in pulse per second (PPS), and FPGA processor receives GPS module after serial ports interrupts
Serial data.
S3: monitoring second pulse signal；
The received pulse per second (PPS) rising edge signal of the FPGA processor monitoring institute；
S4: judge whether PPS second pulse signal has rising edge signal；
When the FPGA processor detects PPS pulse per second (PPS) rising edge signal, into next step, if the FPGA processor
PPS pulse per second (PPS) rising edge signal is not detected, then repeatedly step S3；
S5: interim elapsed time clock Timer1 timing starts；
Interim elapsed time clock is reset and starts timing by FPGA processor；
S6: parsing received serial data and judges whether serial data is effective；
The FPGA processor parses serial data, if time data successfully resolved, enters in next step, if
Serial data parsing failure, return step S2；
S7: it reads corresponding GPS absolute time and judges whether time service succeeds；
If the time that interim elapsed time clock is counted less than 1 second, indicates GPS absolute time time service success, into next step, such as
The time that the interim elapsed time clock of fruit is counted is greater than 1 second, then shows that time service fails, return step S2；
S8: from punctual elapsed time clock work；
By data write-in between the timing of interim elapsed time clock institute from punctual elapsed time clock, from punctual elapsed time clock in write-in data
On the basis of continue to count, into next step；
S9: it is confirmed whether to need time service again；
After since the punctual elapsed time clock timing, when being less than GPS time service interval time numerical value from punctual elapsed time clock numerical value,
The enabled beginning function of time service, not time service again, into next step are not triggered then；If being awarded from punctual elapsed time clock numerical value greater than GPS
When interval time numerical value then trigger that time service is enabled to start function, return step S2；
S10: time data are synchronously written 34 circuit waveform data of the first storage unit；
The sample circuit continued synchronization Acquisition Circuit Wave data, and circuit waveform data are stored in the first storage list
Member, FPGA processor by GPS absolute time and it is automorph when the time the first storage unit is written, waveform time of origin in sampled data
It adds equal to GPS time service absolute time from the punctual elapsed time clock time；
S11: detection circuit Wave data；
The FPGA processor monitoring is stored in the circuit waveform data of the first storage unit, when the FPGA processor is examined
It measures when being stored with overvoltage data in first storage unit, into next step, first storage unit is not detected
In when being stored with overvoltage data, save full some cycles data, successively the earliest circuit waveform data of erasing time；
S12: data storage and transmission；
The FPGA processor grabs corresponding circuit waveform data and time data from the first storage unit, and passes through
Network interface is sent in computer, is carried out in next step, when the connection of network interface and computer is unsmooth or transmission failure, institute
It states FPGA processor then to store voltage data and time data transmission into the second storage unit, the network interface and calculating
After the connection network success of machine, then from the second storage unit voltage data and time data are sent to calculating through network interface
Machine；
S13: data are interpreted and analysis；
The computer receives, stores and reads the data of network interface transmission and draws waveform graph, according to waveform
Curve graph analyzes circuit data.
Further, when the interim elapsed time clock and certainly punctual elapsed time clock are with 100MHz frequency meter.
Further, the GPS time service time interval is 5 seconds.
A kind of Multi-channel data acquisition synchronization system of the invention, by setting to intelligence sample plate every erecting, Mei Gexin
The independent current source for ceasing sampling plate is mutually isolated, solves the problems, such as that multi-channel data signal interferes with each other, each independent acquisition
Channel using GPS time service adds the method from punctual timing to synchronize each channel time benchmark, using double buffering elapsed time clock mode,
It ensure that pulse per second (PPS) and serial ports receive the validity of absolute time while multichannel isolated from power, solve single by GPS
It is possible that pulse per second (PPS) Loss and single certainly punctual elapsed time clock may be in time service stages and data recording stage mistake
The collision problem of the reading data, update that occur in journey improves synchronism and stability between more instruments.
Detailed description of the invention
Fig. 1 is an a kind of schematic diagram of Multi-channel data acquisition synchronization system of the present invention.
Fig. 2 is a schematic diagram of the intelligence sample plate of Fig. 1.
Fig. 3 is an a kind of flow chart of multi-channel data acquisition synchronous method of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is further described.
Referring to FIG. 1, the embodiment provides a kind of GPS time service multi-channel datas using double buffering timer
Acquire synchronization system, including GPS time service module 10, ARM bottom plate 20, intelligence sample plate 30 and computer 40, the GPS time service mould
Block 10 is connect with ARM bottom plate 20, and the ARM bottom plate 20 is connect with intelligence sample plate 30, the intelligence sample plate 30 and computer
40 connections, the GPS time service module 10 receive GPS satellite signal and send the serial data and pulse per second (PPS) letter of GPS absolute time
Number the ARM bottom plate 20 is given, the GPS serial data is GPS absolute time data, and the second pulse signal is received for judging
GPS serial data whether whole time second issue, the ARM bottom plate 20 receive the Serial Port Information that GPS time service module 10 is sent and
Second pulse signal, and Serial Port Information and second pulse signal are sent to intelligence sample plate 30, the intelligence sample plate 30 have it is multiple,
These intelligence sample plates 30 share an ARM bottom plate 20, the second pulse signal and string of the GPS that the GPS time service module 10 issues
Message number is sent to each intelligence sample plate 30 after carrying out multichannel fractionation on ARM bottom plate 20, and each intelligence sample plate 30 is mutually
Isolation, to reduce the interference in signal acquisition process, the intelligence sample plate 30 parses GPS time service data, record parsing GPS is awarded
When data time, and simultaneously Acquisition Circuit Wave data.
The intelligence sample plate 30 is equipped with serial ports 31, FPGA processor 32, sample circuit 33, storage unit 34, network and connects
Mouthful 35, independent current source 36, the FPGA processor 32 respectively with serial ports 31, elapsed time clock sample circuit 33, storage unit 34, net
Network interface 35, independent current source 36 connect, and the independent current source 36 is connect with ARM bottom plate 20, and the independent current source 36 provides information
The operation power of sampling plate 30, the FPGA processor 32 carry out the reception and processing of data and signal, and the serial ports 31 receives
The GPS Serial Port Information that ARM bottom plate 20 is sent, and GPS Serial Port Information is sent to FPGA processor 32, GPS second pulse signal is logical
It crosses after the ARM bottom plate 20 carries out multichannel fractionation and is sent to the FPGA processor 32, the FPGA processor 32 is receiving
GPS Serial Port Information and second pulse signal carry out the time service of GPS absolute time, the interim elapsed time clock of setting in the FPGA processor 32
(not shown) and certainly punctual elapsed time clock (not shown) doubleclocking, connect wherein interim elapsed time clock records the FPGA processor 32
Receive time of the GPS Serial Port Information to successfully resolved, time data when the certainly punctual elapsed time clock records automorph, the sampling electricity
33 Acquisition Circuit Wave data of road, the FPGA processor 32 is by circuit waveform data and GPS absolute time data and automorph
When time data saved together to storage unit 34, the storage unit 34 includes that the first storage unit 341 and the second storage are single
Member 342, first storage unit 341 temporarily save circuit waveform data, GPS absolute time data and certainly punctual timing number
According to when the FPGA processor 32, which detects, is stored with overvoltage data in first storage unit 341, at the FPGA
Reason device 32 grabs circuit waveform data, GPS absolute time data and certainly punctual timing number from first storage unit 341
According to, and computer is sent to by network interface 35 by circuit waveform data, GPS absolute time data and from punctual chronometric data
In 40, the respective independent detection circuit waveform data of multiple intelligence sample plates 30 but mutually output trigger signal, at least one FPGA
When processor 32 detects overvoltage data, the FPGA processor 32 of multiple block message collection plates 30 is sent out to network interface 35 simultaneously
Wave data and time data are sent, if the connection of network interface 35 and computer 40 is unsmooth or transmission fails, the FPGA processing
Circuit waveform data, the time service of GPS absolute time and certainly punctual chronometric data are sent in the second storage unit 342 and are deposited by device 32
Storage, the network interface 35 is with after the connection network success of computer 40, and the FPGA processor 32 is again from the second storage unit
Data are sent to computer 40 through network interface 35 in 342, the computer 40 receives, storage and reading network interface 35 pass
The data sent simultaneously draw waveform graph, are analyzed according to waveform graph.
In the present embodiment, first storage unit 341 is DDR cache unit, and second storage unit 342 is TF
Storage unit.
In the present embodiment, the GPS time service module 10 is Gstar series GPS module, product type: GS-216.GPS
Time service module can export a whole pulse per second (PPS) PPS in the positive second, and the synchronization accuracy of pulse per second (PPS) is up to 100ns, while its serial ports can be defeated
The whole number of seconds value of absolute time out.Format is as follows:
$GPRMC,161229.487,A,3723.2475,N,12158,3416,W,0.13,309.62,120598,,*10
| Title | Example | Unit | Description |
| Message code | $GPRMC | — | RMC specification comes back |
| The standard setting time | 161229.487 | — | The constantly every minute seconds seconds second |
| Positioning states | A | — | A=accurate data V=data are unreliable |
| Latitude | 3723.2475 | — | Degree degree divides points points points points |
| The Northern Hemisphere or Southern Hemisphere indicator | N | — | Northern (N) hemisphere or south (S) hemisphere |
| Longitude | 12158.3416 | — | Du Dudu divides points points points points |
| The Eastern Hemisphere or the Western Hemisphere indicator | W | — | Eastern (E) hemisphere or west (W) hemisphere |
| Ground speed | 0.13 | Section | 0.0 to 1851.8 section |
| Direction over the ground | 309.62 | Degree | Actual value |
| Date | 120598 | — | Everyday month in and month out every year |
| Magnetic pole variable | — | Degree | Eastern (E) hemisphere or west (W) hemisphere |
| Check code | *10 | — | — |
| <CR><LF> | — | — | Message terminal |
When the FPGA processor 32, which receives GPS serial data, carries out data parsing, the data format of reference GPS,
There are multiple commas in serial data (i.e. absolute time data) information of GPS, for separating different information, first, in accordance with data
Format obtains starting character, judges whether correctly, obtains positioning states according still further to data format, A is judged whether it is, according still further to data
Format obtain " year ", " moon ", " day ", " when ", " divide ", " second " information, judge " year " value whether be greater than 2000, in judgement " moon "
Value whether be less than or equal to 12, whether be less than or equal to 31 in the value of judgement " day ", then judge " when " value it is whether small be equal to 24,
Whether it is less than or equal to 60 in the value of judgement " dividing ", whether is less than or equal to 60 in the value of judgement " second ", if all of above judgement is equal
Correctly, then illustrating the GPS time data obtained is effectively that serial data receives successfully, otherwise illustrates the GPS time number obtained
According to being invalid, serial data reception failure.GPS serial data is obtained in the present embodiment and is received, and serial data is successfully then set
Success Flag position RxdRecieve=true is received, serial data reception failure is then arranged serial data and receives Success Flag position
RxdRecieve=false.
A kind of multi-channel data acquisition synchronous method, comprising the following steps:
S1: intelligence sample plate 30 and time service module 10 are switched on, the 33 Acquisition Circuit Wave data of sample circuit, will be described
FPGA processor 32 is set as automatic time service, and double elapsed time clocks are arranged；When interim elapsed time clock Timer1 and certainly punctual timing
Clock Timer2.
Wherein interim elapsed time clock Timer1 receives whole second pulse signal to successfully solving for recording FPGA processor 32
The time interval for analysing GPS absolute time, from punctual elapsed time clock Timer2, for being counted from punctual for system.
S2: time service starts, and receives GPS second pulse signal and serial data.
The enabled beginning function TEenable=1 of time service is set in FPGA processor 32, and as TEenable=1, time service makes
It can start, open pulse per second (PPS) interruption and serial ports interrupts, FPGA processor 32 receives second pulse signal, string after unlatching is interrupted in pulse per second (PPS)
FPGA processor 32 receives the serial data of GPS module after mouth interrupts.
S3: monitoring second pulse signal.
The received pulse per second (PPS) rising edge signal of the monitoring of FPGA processor 32 institute.
S4: judge whether PPS second pulse signal has rising edge signal.
When the FPGA processor 32 detects PPS pulse per second (PPS) rising edge signal, into next step, if the FPGA is handled
PPS pulse per second (PPS) rising edge signal is not detected in device 32, then repeatedly step S3.
S5: interim elapsed time clock Timer1 timing starts.
Interim elapsed time clock Timer1 is reset and is started timing by FPGA processor,
When interim elapsed time clock Timer1 and certainly punctual elapsed time clock Timer2 are in the present embodiment with 100MHz frequency meter,
Time precision is theoretically up to 0.1 microsecond.
S6: parsing received serial data, and judges whether serial data is effective.
The FPGA processor 32 parses serial data, if time data successfully resolved, enters in next step,
If serial data parsing failure, return step S2.
S7: corresponding GPS absolute time is read, and judges whether time service succeeds.
If the time that interim elapsed time clock Timer1 is counted less than 1 second, indicates GPS absolute time time service success, under
One step shows that time service fails, return step S2 if the time that interim elapsed time clock Timer1 is counted is greater than 1 second.
S8: from punctual elapsed time clock work.
By data write-in between the timing of interim elapsed time clock Timer1 institute from punctual elapsed time clock Timer2, from when punctual timing
Clock Timer2 continues to count on the basis of data are written, into next step.
S9: it is confirmed whether to need time service again.
After since the punctual elapsed time clock Timer2 timing, when being less than GPS time service from punctual elapsed time clock Timer2 numerical value
Interval time numerical value does not trigger the enabled beginning function of time service then, at this time TEenable=0, not time service again, into next step；
Function time service enables is triggered if being greater than GPS time service interval time numerical value since punctual elapsed time clock Timer2 numerical value, at this time
TEenable=1, return step S2.
The time interval of GPS time service in the present embodiment is 5s, when being greater than 5s from the punctual elapsed time clock Timer2 time, is then weighed
New time service.
S10: time data are synchronously written 34 circuit waveform data of the first storage unit.
The 33 continued synchronization Acquisition Circuit Wave data of sample circuit, and circuit waveform data are stored in the first storage
Unit 34, FPGA processor 32 by GPS absolute time and it is automorph when the time the first storage unit 34 is written, waveform in sampled data
Time of origin is equal to GPS time service absolute time and adds from the punctual elapsed time clock time.
S11: detection circuit Wave data.
The FPGA processor monitoring is stored in the circuit waveform data of the first storage unit 34, when the FPGA processor
32 detect when being stored with overvoltage data in first storage unit 341, into next step.Described first is not detected to deposit
When being stored with overvoltage data in storage unit 341, full some cycles data are saved, successively the earliest circuit waveform number of erasing time
According to.
S12: data storage and transmission；
The FPGA processor 32 grabs corresponding circuit waveform data and time data from the first storage unit 341,
And be sent in computer 40 by network interface 35, it carries out in next step.
When the connection of network interface 35 and computer 40 is unsmooth or transmission failure, the FPGA processor 32 is then by voltage
Data and time data transmission are stored into the second storage unit 342, the connection network of the network interface 35 and computer 40
After success, then from the second storage unit 342 voltage data and time data are sent to computer 40 through network interface 35.
S13: data are interpreted and analysis；
The computer 40 receives, stores and read the data of the transmission of network interface 35 and draws waveform graph, according to
Waveform graph analyzes circuit data.
Actual acquired data result verification, the present invention applies on the overvoltage Transient Data Acquisition Systems of triple channel, between GPS time service
Every time 10S, three-phase sampling plate uses same trigger signal verification time synchronism, realizes that effect is as follows:
Computer combines from punctual gate time mode every phase GPS absolute time and draws waveform graph respectively, shows
A, B, C three-phase waveform are aligned in time, and waveform degree of overlapping is good, and there are difference, but failure in the time of every phase start recording data
Point waveform is overlapped, and obtains waveform as follows after the waveform of waveform catastrophe point key point is amplified:
A phase absolute time: 43 divide the 29 seconds trigger point time: 912954 microseconds when 12
B phase absolute time: 43 divide the 29 seconds trigger point time: 913380 microseconds when 12
C phase absolute time: 43 divide the 29 seconds trigger point time: 912577 microseconds when 12
Wherein, the trigger point time refers to that acquisition system judges false voltage (overvoltage) the start recording moment, and waveform is dashed forward
The waveform of height key point amplifies 7 times, obtains the time error in three-phase channel:
The time error of C phase and B phase is -85562 microsecond of 85580 microsecond=18 microseconds
The time error of A phase and B phase is -85562 microsecond of 85585 microsecond=23 microseconds
The time error of A phase and C phase is -85580 microsecond of 85585 microsecond=5 microseconds -
From experimental result it can be seen that, within 10S from time keeping error within 25 microseconds, three-phase multichannel collecting system
Synchronous error is within 30 microseconds.
Synchronization accuracy between each acquisition channel of device experimental verification in kind can guarantee to reach 30 at any time micro-
Within second (10 seconds time service periods).Guarantee synchronism error between the same more acquisition channels of instrument less than 30 microseconds,
The synchronism error between more instruments can be guaranteed less than 30 microseconds.
Herein, the nouns of locality such as related front, rear, top, and bottom are to be located in figure with components in attached drawing and zero
Part mutual position defines, only for the purpose of expressing the technical solution clearly and conveniently.It should be appreciated that the noun of locality
Use should not limit the claimed range of the application.
In the absence of conflict, the feature in embodiment and embodiment herein-above set forth can be combined with each other.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of Multi-channel data acquisition synchronization system, it is characterised in that: the Multi-channel data acquisition synchronization system includes GPS
Time service module, ARM bottom plate, intelligence sample plate and computer, the GPS time service module are connect with ARM bottom plate, the ARM bottom plate
It is connect with intelligence sample plate, the intelligence sample plate is connect with computer, and the GPS time service module receives GPS satellite signal simultaneously
For the serial data and second pulse signal for sending GPS absolute time to the ARM bottom plate, the ARM bottom plate receives GPS time service module
The Serial Port Information and second pulse signal of transmission, and Serial Port Information and second pulse signal are sent to intelligence sample plate, the information
Sampling plate has multiple, these intelligence sample plates share an ARM bottom plate, the pulse per second (PPS) letter for the GPS that the GPS time service module issues
Number and rs 232 serial interface signal multichannel fractionation is carried out on ARM bottom plate after be sent to each intelligence sample plate, each intelligence sample plate is mutual
Isolation, the intelligence sample plate parsing GPS time service data, record parse the time of GPS time service data and simultaneously Acquisition Circuit wave
Graphic data, each intelligence sample plate detect in its received circuit waveform data whether have overvoltage data, these information are adopted
Simultaneously to computer transmitting line Wave data when collection plate at least one of them intelligence sample plate has detected overvoltage data
With time data, the computer receives, stores and reads the data of network interface transmission and draws waveform graph；
The intelligence sample plate is equipped with serial ports, FPGA processor, sample circuit, storage unit, network interface, independent current source, institute
It states FPGA processor to connect with serial ports, sample circuit, storage unit, network interface and independent current source respectively, the independent current source
It is connect with ARM bottom plate, the independent current source provides the operation power of intelligence sample plate, and the FPGA processor carries out data and letter
Number reception and processing, the serial ports receives the GPS Serial Port Information that ARM bottom plate is sent, and GPS Serial Port Information is sent to FPGA
Processor, GPS second pulse signal is sent to the FPGA processor after carrying out multichannel fractionation by the ARM bottom plate, described
FPGA processor receives GPS Serial Port Information and second pulse signal carries out the time service of GPS absolute time, sets and faces in the FPGA processor
When elapsed time clock and from punctual two clocks of elapsed time clock, wherein interim elapsed time clock, which records the FPGA processor, receives GPS
Time data of the Serial Port Information to information successfully resolved, time data when the certainly punctual elapsed time clock records automorph are described to adopt
Sample circuit Acquisition Circuit Wave data, the FPGA processor is by circuit waveform data and GPS absolute time data and automorph
When time data saved together to storage unit.
2. Multi-channel data acquisition synchronization system as described in claim 1, it is characterised in that: the storage unit includes first
Storage unit and the second storage unit, first storage unit temporarily save circuit waveform data, GPS absolute time data and
From punctual chronometric data, when the FPGA processor, which detects, is stored with overvoltage data in first storage unit, institute
It states FPGA processor and grabs circuit waveform data, the time service of GPS absolute time and certainly punctual timing from first storage unit
Data, and computer is sent to by network interface by circuit waveform data, GPS absolute time data and from punctual chronometric data
In, the connection of the network interface and computer it is unsmooth or transmission failure when, the FPGA processor by circuit waveform data,
GPS absolute time data and being sent in the second storage unit from punctual chronometric data stores, to network interface and computer
After connecting network success, the FPGA processor sends data to computer through network interface from the second storage unit again.
3. Multi-channel data acquisition synchronization system as claimed in claim 2, it is characterised in that: first storage unit is
DDR cache unit, second storage unit are TF storage units.
4. Multi-channel data acquisition synchronization system as claimed in claim 2, it is characterised in that: the GPS time service module can be
The positive second exports a whole pulse per second (PPS) PPS, and the synchronization accuracy of whole pulse per second (PPS) is up to 100ns.
5. a kind of multi-channel data acquisition side of synchronization for applying Multi-channel data acquisition synchronization system as claimed in claim 2
Method, it is characterised in that: the multi-channel data acquisition synchronous method the following steps are included:
S1: intelligence sample plate and time service module booting, the sample circuit Acquisition Circuit Wave data, by the FPGA processor
It is set as automatic time service, and double elapsed time clocks is set；Interim elapsed time clock and certainly punctual elapsed time clock, wherein interim elapsed time clock
The time interval for receiving whole second pulse signal to parsing GPS absolute time for recording FPGA processor, from when punctual timing
Clock is counted for system from punctual；
S2: time service starts, and receives GPS second pulse signal and serial data；
The enabled beginning function of time service is set in FPGA processor, and when time service starts, unlatching pulse per second (PPS) interruption and serial ports are interrupted, the second
FPGA processor receives second pulse signal after pulse-break is opened, and FPGA processor receives the serial ports of GPS module after serial ports interrupts
Data；
S3: monitoring second pulse signal；
The received pulse per second (PPS) rising edge signal of the FPGA processor monitoring institute；
S4: judge whether PPS second pulse signal has rising edge signal；
When the FPGA processor detects PPS pulse per second (PPS) rising edge signal, into next step, if the FPGA processor is not examined
PPS pulse per second (PPS) rising edge signal is measured, then repeatedly step S3；
S5: interim elapsed time clock Timer1 timing starts；
Interim elapsed time clock is reset and starts timing by FPGA processor；
S6: parsing received serial data and judges whether serial data is effective；
The FPGA processor parses serial data, if time data successfully resolved, enters in next step, if serial ports
Data parsing failure, return step S2；
S7: it reads corresponding GPS absolute time and judges whether time service succeeds；
If the time that interim elapsed time clock is counted less than 1 second, indicates GPS absolute time time service success, into next step, if faced
When time for being counted of elapsed time clock be greater than 1 second, then show that time service fails, return step S2；
S8: from punctual elapsed time clock work；
By data write-in between the timing of interim elapsed time clock institute from punctual elapsed time clock, from base of the elapsed time clock in write-in data of keeping time
Continue to count on plinth, into next step；
S9: it is confirmed whether to need time service again；
After since the punctual elapsed time clock timing, when being less than GPS time service interval time numerical value from punctual elapsed time clock numerical value, then not
Trigger the enabled beginning function of time service, not time service again, into next step；If being greater than between GPS time service from punctual elapsed time clock numerical value
The enabled beginning function of time service, return step S2 are then triggered every time numerical value；
S10: time data are synchronously written the first storage unit circuit Wave data；
The sample circuit continued synchronization Acquisition Circuit Wave data, and circuit waveform data are stored in the first storage unit,
FPGA processor by GPS absolute time and it is automorph when the time the first storage unit is written, waveform time of origin etc. in sampled data
It adds in GPS time service absolute time from the punctual elapsed time clock time；
S11: detection circuit Wave data；
The FPGA processor monitoring is stored in the circuit waveform data of the first storage unit, when the FPGA processor detects
When being stored with overvoltage data in first storage unit, into next step, it is not detected in first storage unit and deposits
When containing overvoltage data, full some cycles data are saved, successively the earliest circuit waveform data of erasing time；
S12: data storage and transmission；
The FPGA processor grabs corresponding circuit waveform data and time data from the first storage unit, and passes through network
Interface is sent in computer, is carried out in next step, described when the connection of network interface and computer is unsmooth or transmission failure
FPGA processor then stores voltage data and time data transmission into the second storage unit, the network interface and computer
The success of connection network after, then from the second storage unit send voltage data and time data to calculating through network interface
Machine；
S13: data are interpreted and analysis；
The computer receives, stores and reads the data of network interface transmission and draws waveform graph, according to wavy curve
Figure analyzes circuit data.
6. multi-channel data acquisition synchronous method as claimed in claim 5, it is characterised in that: the interim elapsed time clock and from
When punctual elapsed time clock is with 100MHz frequency meter.
7. multi-channel data acquisition synchronous method as claimed in claim 5, it is characterised in that: the GPS time service time interval
It is 5 seconds.
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| CN107966723B (en) * | 2017-11-22 | 2019-10-08 | 中国人民解放军国防科技大学 | Multi-rate multi-channel time synchronization high-speed data recording system |
| CN108696345A (en) * | 2018-05-10 | 2018-10-23 | 安徽雷索信息科技有限公司 | A kind of multi-channel high-speed data loading method and its system |
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| CN109462452B (en) * | 2018-10-26 | 2020-07-31 | 科大智能电气技术有限公司 | Method for improving sampling synchronization precision of transient recording type fault indicator |
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| CN109917637B (en) * | 2019-03-13 | 2020-10-09 | 清华四川能源互联网研究院 | High-precision time service method for data acquisition card |
| CN110609208B (en) * | 2019-09-15 | 2022-07-15 | 杭州拓深科技有限公司 | Portable fault wave recording monitor and wave recording monitoring method thereof |
| CN111130674B (en) * | 2019-09-29 | 2021-04-13 | 北京嘀嘀无限科技发展有限公司 | Synchronous signal acquisition method for automobile electronic control unit, electronic equipment, server and storage medium |
| CN112486009B (en) * | 2020-11-20 | 2022-07-19 | 山东山大电力技术股份有限公司 | Time service signal abnormal waveform recording analyzer and method |
| CN113358917B (en) * | 2021-06-02 | 2022-11-22 | 北京计算机技术及应用研究所 | Pulse wave height acquisition implementation method based on FPGA |
| CN113985205A (en) * | 2021-10-27 | 2022-01-28 | 重庆邮电大学 | Power distribution network overvoltage acquisition method based on Beidou time service and edge calculation |
| CN114892834B (en) * | 2022-05-19 | 2023-09-29 | 长沙同强电子科技有限公司 | Positive electrode grouping layout method of electroosmosis pulse anti-seepage dehumidification system |
| CN115037403B (en) * | 2022-08-10 | 2022-11-22 | 中国电子科技集团公司第十研究所 | Multi-ARM-FPGA combined simulation time synchronization method |
| CN117745472B (en) * | 2023-12-21 | 2024-06-25 | 江苏省工程勘测研究院有限责任公司 | River management method and system based on lightweight sensing model |
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