CN106569013A - Power-grid overvoltage monitoring method and system - Google Patents

Abstract

The power grid overvoltage monitoring method and system provided by the present invention have good real-time response characteristics and high sampling rate characteristics, can record the entire process for a long time, and can simultaneously record the data of the three periods before the trigger, the trigger period and the two periods after the departure, Excellent protection of the record of overvoltage waveform; and the use of real-time compression can greatly reduce the data volume of the collected waveform data, which is convenient for storage, solves the contradiction between high sampling rate and recording time, and can accurately and stably capture overvoltage waveform.

Description

A monitoring method and system for grid overvoltage

technical field

The present invention relates to the field of grid overvoltage measurement, and more specifically, to a monitoring method and system for grid overvoltage.

Background technique

Various overvoltages often occur in the power grid system, such as lightning overvoltage, operating overvoltage, linear resonance overvoltage, ferromagnetic resonance overvoltage, arc grounding overvoltage, etc. The waveform, amplitude and duration of various overvoltages The times are all different, and the range of variation is also very large. When the overvoltage amplitude is very high, it will cause insulation breakdown. The amplitude is slightly small but the action time is long. Breakdown may also occur. The amplitude is small but it will also promote insulation aging under multiple actions. Operation experience and research show that overvoltage is often the direct cause of insulation damage accidents in power systems, especially in 10KV and 35KV distribution networks, where internal overvoltages are more complex and last longer, and the proportion of such accidents is greater. With the rapid construction and development of ultra-high voltage and large power grids, people pay more and more attention to the influence of overvoltage on the safe operation of power grids.

Although a large number of overvoltage protection devices such as lightning arresters are installed in the actual power grid system, when an overvoltage accident occurs, it is difficult to determine whether the cause of the accident is due to the overvoltage amplitude or steepness exceeding the bearing capacity of the equipment, or the equipment It is caused by the reduction of the insulation level of the protection device, or there is a problem with the protection device, which makes the analysis and judgment very difficult. Therefore, recording the transient voltage waveform of the complete accident process is an important basis for analyzing the cause of the accident.

Overvoltage monitoring requires the test system to have good frequency response characteristics and high sampling rate, and be able to record the whole process for a long time. At present, the fault recording device mainly records the fault recording based on the power frequency and its harmonics, which is not suitable for the overvoltage monitoring of the system.

Due to the contradiction between high sampling rate and long recording time, the existing overvoltage recorders cannot meet the voltage waveform recording requirements of overvoltage accident results. High sampling rate will shorten the recording length, and low sampling rate will shorten the recording time. Lengthen, but will lose the maximum peak value of fast pulse waveforms, such as lightning waves, resulting in inaccurate or even wrong conclusions when analyzing problems afterwards.

Contents of the invention

The overvoltage monitoring method and system proposed by the present invention realize long-term recording through data compression and complete sampling at a higher sampling speed, and monitor whether the current cycle is a trigger cycle in real time through three judging methods, and can record the trigger cycle at the same time All the data of the first three periods, the trigger period and the two periods after the trigger ensure the integrity of the waveform, thereby ensuring the accuracy of post-analysis problems.

According to one aspect of the present invention, a method for monitoring overvoltage of a power grid is provided, including:

Set the basic parameters of overvoltage monitoring;

Collect voltage data, compress and buffer the data, and extract data at a predetermined frequency for fast Fourier transform FFT;

Judging whether the current period of the voltage data is a triggering period through similar waveform judgment, amplitude trigger judgment or frequency drift judgment;

If the current cycle is a trigger cycle, the data of the current cycle, the data of the first three cycles of the current cycle and the data of the following two cycles are stored in the DDR synchronous dynamic random access memory, and sent to the host computer; and

If the current cycle is not a trigger cycle, the data of the next cycle is used to overwrite the initial cycle data cached in the DDR synchronous DRAM.

Preferably, the basic parameters include: data sampling rate F, minimum recording deviation Δy, maximum storage interval N, minimum storage frequency Fk, FFT frequency drift threshold Δf, FFT fundamental wave amplitude threshold Δg, and root mean square threshold Δrms.

Preferably, said compressing the data includes: recording the first sampling point Xi in the current period as a feature point, and then _judging whether the absolute value of the difference between the next _sampling point Xi ₊₁ and Xi is less than △y, if the difference is greater than or equal to △y, cache the value of Xi+ ₁ and use Xi ₊₁ as the new feature point for the next compression until the end of a cycle; if the difference is less than △ y, then add 1 to the value of the number of compression points a, when a is greater than or equal to the maximum storage interval N, cache the value of Xi+ ₁ and use Xi ₊₁ as the new feature point for the next compression until one cycle End.

Preferably, the determination of the similar waveform is: when performing data collection, calculate the root mean square of the value of each record point of the current cycle and the value of the corresponding record point of the previous cycle, if the value of the root mean square is greater than Root mean square threshold △rms, the current cycle is not similar to the waveform of the previous cycle, then the current cycle is the trigger cycle, and each cycle has 16 record points, which are the maximum value, minimum value and 14 points uniformly collected between the maximum and minimum values.

Preferably, the amplitude trigger judgment is: judge the data after FFT, if the fundamental amplitude component of the FFT data is greater than the FFT fundamental amplitude threshold Δg, then the current period is the trigger period .

Preferably, the frequency drift judgment is: judge the data after FFT, if the frequency deviation of the data after FFT is greater than the FFT frequency drift threshold Δf, then the current period is the trigger period.

Preferably, when the monitoring is started, the automatic time service of the local clock is performed by acquiring the second pulse of the GPS module, and the self-timekeeping operation is performed at a clock frequency of 100MHz.

Preferably, before data acquisition, the signal to be tested is isolated, and even-order harmonics and common-mode noise are suppressed.

Preferably, when the data of the trigger cycle and the data of the first three cycles of the trigger cycle and the data of the next two cycles are sent to the host computer waveform observation and processing device, the amount of data sent each time is set, and in multiple cycle mode send.

According to another aspect of the present invention, a grid overvoltage monitoring system is provided, including:

The host computer waveform observation and processing device is used for displaying, amplifying, analyzing, querying and saving historical data of overvoltage waveforms, and can actively trigger independent acquisition units for data acquisition;

Three independent acquisition units for acquiring, judging and storing overvoltage waveform signals; and

The main board supplies power for three independent acquisition systems, sends acquisition signals and connects to an external GPS module;

Among them, each independent acquisition system includes:

Signal conditioning acquisition circuit, used to realize the acquisition and conversion of overvoltage signals;

The FPGA acquisition board compresses the digital signal collected and converted by the signal conditioning acquisition circuit, extracts the digital signal synchronously for fast Fourier transform, and uses the embedded ARM processor to judge the trigger cycle; and

The DDR synchronous dynamic random access memory is used for buffering the compressed digital signal and storing the data of the trigger cycle, the data of the first three cycles of the trigger cycle and the data of the next two cycles.

Preferably, the system for overvoltage monitoring of the power grid further includes:

GPS module, connected to the main board, used for clock calibration and self-timekeeping of three independent acquisition systems;

SPI interface for communication between three independent acquisition systems and the main board; and

The system control board is used for parameter setting and restart of the FPGA acquisition board.

Preferably, each independent collection system also includes:

Network interface for data transmission between the independent acquisition system and the host computer waveform observation and processing software; and

Serial port, used to read the calibration data sent by the GPS module.

Preferably, the signal conditioning acquisition circuit includes:

A voltage follower is used to isolate the signal to be tested and the subsequent stage circuit, wherein the latter stage circuit is a single-ended to differential processor and an A/D acquisition circuit;

A single-ended-to-differential conversion processor for rejecting even-order harmonics and common-mode noise of the signal under test; and

The A/D acquisition circuit is used for acquiring and converting the processed signal to be tested to obtain voltage data.

Preferably, when any of the three independent acquisition systems determines that the current acquisition period is the trigger period, the FPGA acquisition board sends a trigger signal to the main board while the data is being stored, and the main board sends the acquisition signal after receiving the trigger signal To the other two independent acquisition systems, so that the three independent acquisition systems can simultaneously collect the signals of the current cycle.

Description of drawings

A more complete understanding of the exemplary embodiments of the present invention can be had by referring to the following drawings:

Fig. 1 is the flowchart of the voltage overvoltage monitoring method according to a preferred embodiment of the present invention;

Fig. 2 is a flow chart of a method for compressing data according to a preferred embodiment of the present invention;

3 is a structural diagram of a power grid overvoltage monitoring system according to a preferred embodiment of the present invention; and

Fig. 4 is a structural diagram of a grid overvoltage monitoring system according to a preferred embodiment of the present invention.

detailed description

Exemplary embodiments of the present invention will now be described with reference to the drawings; however, the present invention may be embodied in many different forms and are not limited to the embodiments described herein, which are provided for the purpose of exhaustively and completely disclosing the present invention. invention and fully convey the scope of the invention to those skilled in the art. The terms used in the exemplary embodiments shown in the drawings do not limit the present invention. In the figures, the same units/elements are given the same reference numerals.

Unless otherwise specified, the terms (including scientific and technical terms) used herein have the commonly understood meanings to those skilled in the art. In addition, it can be understood that terms defined by commonly used dictionaries should be understood to have consistent meanings in the context of their related fields, and should not be understood as idealized or overly formal meanings.

Fig. 1 is a flowchart of a grid overvoltage monitoring method according to a preferred embodiment of the present invention. As shown in FIG. 1 , the overvoltage monitoring method 100 starts from step 101 . In step 101, first set the basic parameters of monitoring, wherein the basic parameters include data sampling rate F, minimum recording deviation Δy, maximum storage interval N, minimum storage frequency Fk, FFT frequency drift threshold Δf, FFT Fundamental amplitude threshold △g and root mean square threshold △rms. At the same time, at the beginning of the test, the second pulse continuously sent by the GPS module is obtained through the serial port, and the local clock in the system performs automatic timing once through the pulse edge of the second pulse, and then realizes self-timekeeping operation with a clock frequency of 100MHz inside the FPGA.

In step 102, the voltage data is collected, and during the collection process, the data of each period is compressed, and the compressed data is cached in the DDR. Wherein, the compression processing flow is shown in FIG. 2 , and the process will be described in detail in FIG. 2 . In the process of data acquisition, the data is extracted at a predetermined frequency to perform fast Fourier transform FFT. Usually, the predetermined frequency is 6.4k, and the data after FFT processing will be judged by amplitude trigger or frequency drift to determine whether the current cycle is a trigger cycle. Preferably, every 20ms is a period. Preferably, before data acquisition, the signal to be tested is subjected to a signal conditioning operation, which mainly includes isolating the signal to be tested and the subsequent circuit, so as to ensure that certain negative effects of the signal to be tested will not affect the collected voltage data, for example, the signal to be tested even-order harmonics and common-mode noise in the signal to be tested, and furthermore, the even-order harmonics and common-mode noise in the signal to be tested are suppressed through a single-ended to differential processor to reduce interference and make the The test signal reaches the standard that can be collected by the A/D acquisition circuit.

In step 103, judge whether the current cycle of the voltage data is a trigger cycle through similar waveform judgment, amplitude trigger judgment or frequency drift judgment. If the current cycle is a trigger cycle, go to step 104; otherwise go to step 105. Wherein, the similar waveform is judged as, during the process of data collection, 16 record points in each cycle are collected and marked, which are respectively the maximum value and the minimum value in each cycle, and the average value between the maximum value and the minimum value. 14 points collected. When judging similar waveforms, calculate the root mean square of the value of each record point in the current cycle and the value of the corresponding record point in the previous cycle, if the value of the root mean square is greater than the preset root mean square threshold △ rms, it proves that the current cycle is the trigger cycle, and proceed to the next step.

Preferably, the amplitude trigger judgment is: judge the data after FFT, if the fundamental amplitude component of the FFT data is greater than the preset FFT fundamental amplitude threshold Δg, then the current The period is the trigger period, and proceed to the next step.

Preferably, the frequency drift judgment is: judge the data after FFT, if the frequency deviation of the data after FFT is greater than the preset FFT frequency drift threshold Δf, then the current cycle is the trigger cycle, and Proceed to the next step. It should be understood that when judging the trigger period, as long as any trigger condition among similar waveform judgment, amplitude trigger judgment and frequency drift judgment is met, the current period can be judged as the trigger period.

In step 104, the current cycle is judged as a trigger cycle, then the data of the current cycle, the data of the first three cycles of the current cycle and the data of the following two cycles are stored in the DDR synchronous dynamic random access memory, and are packaged and sent to the upper position machine for storage, analysis and other operations. Preferably, when performing data transmission with the host computer waveform observation and processing device, a network transmission thread is created in the embedded ARM processor of the FPGA acquisition board, and by setting the amount of data sent each time, it is carried out in a multiple cycle mode The sending of data and the process of network transmission are described in detail in FIG. 3 .

In step 105, when the current cycle is not a trigger cycle, the data of the next cycle is used to overwrite the first cycle data cached in the DDR synchronous dynamic random access memory. Fig. 2 is a flowchart of a method for compressing data according to a preferred embodiment of the present invention. Since this method needs to monitor for too long and the amount of data is too large, if the data of each cycle is completely stored, it will occupy too much storage space, and the speed of operation will also decrease at the same time, so the collected data needs to be Real-time compression, the compressed data can represent the complete periodic data content as much as possible, and can be sampled at a higher sampling speed under long-term recording. The compressing the data includes: recording the first sampling point Xi in the current period as a feature point, and then judging whether the absolute value of the difference between the next _sampling point Xi ₊₁ and Xi is less than _Δy , If the difference is greater than or equal to Δy, cache the value of Xi+ ₁ and use Xi ₊₁ as the new feature point for the next compression until the end of a cycle; if the difference is less than Δy, then Add 1 to the value a of the number of compression points. When a is greater than or equal to the maximum storage interval N, cache the value of Xi+ ₁ and use Xi ₊₁ as the new feature point for the next compression until the end of a cycle.

Fig. 3 is a flowchart of a method for judging a network transmission thread according to a preferred embodiment of the present invention. When carrying out network transmission, if the one-time transmission volume is too large, it is easy to cause the network to be stuck. If a small amount of data is sent once, the efficiency of transmission will be affected. Therefore, the present invention sets the amount of data sent each time when performing network transmission, and Sending in multiple loop mode realizes efficient and stable network transmission.

During the transmission process, the data transmission format is command word, byte number, time, packet mark, total number of data packets, data packet number, data, and actual data number. Firstly, a network transmission thread is created in the ARM processor to perform network operations. Then set the mark point_num, which is used to indicate the number of data points in one period; cmd is marked as the command word; use the array DmaBuf to store the collected waveform data, and BufLen is the actual data length; set trig_flag_glb as the data mark stored at the same trigger time, every A trigger moment stores 6 cycles of data; total marks the total number of packets that need to be sent for one cycle of data, packet_num marks the number of data packets actually sent; actual_length marks the number of bytes actually sent.

In the DDR memory, use the empty storage area to set up a buffer, and buffer the data that needs to be sent to the waveform observation and processing device of the host computer into the buffer. When performing network transmission, first determine whether there is still data in the buffer that needs to be sent. If If it does not exist, no operation will be performed. If it exists, the start time, trigger time and the same trigger time mark trig_flag_glb of the current cycle data will be sent to the waveform observation and processing device of the host computer first, which is used for the waveform observation and processing device of the host computer to judge the sent data The data recorded by the same trigger signal; when the host computer detects that the received time data is correct, it will return the instruction to allow data transmission, and the ARM processor will judge whether the data length BufLen stored in the DmaBuf array is greater than 1024, if so, send 1024 bytes per packet of data, that is, actual_length=1024, then send data to the host computer waveform observation and processing device according to the format cmd+total+packet_num+DmaBuf+actual_length, where the value of DmaBuf is 1204 bytes , and add one to packet_num, and subtract 1024 from the length of BufLen; if the length of BufLen is less than 1024, then actual_length=BufLen; send data according to the same command format, and fill the part less than 1024 with data 0x00; stop sending when packet_num==total , indicating that the data transmission of one cycle is completed, and the next cycle starts to send the data of the next cycle. If packet drop occurs, wait until the ARM processor finishes sending the data of this cycle, the waveform observation and processing device of the host computer will send back the packet number of the dropped data, and the ARM processor can resend.

Fig. 4 is a structural diagram of a grid overvoltage monitoring system according to a preferred embodiment of the present invention. As shown in FIG. 4 , the overvoltage monitoring system 400 mainly includes a host computer waveform observation and processing device 401 , an independent acquisition unit 402 and a main board 403 . Among them, the upper computer waveform observation and processing device 401 is mainly used for displaying, amplifying, analyzing, querying and saving historical data of the overvoltage waveform, and can actively trigger an independent acquisition unit for data acquisition.

Preferably, the independent acquisition unit 402 should have three identical units in the system in practical applications, and only a structural diagram of an independent acquisition unit 402 is given in FIG. Acquisition unit shall prevail. The independent acquisition unit 402 mainly includes a signal conditioning acquisition circuit 4021 for acquiring overvoltage signals, converting the acquired voltage signals, and outputting digital signals to the FPGA acquisition board 4022 .

Preferably, after receiving the digital signal output by the signal conditioning acquisition circuit 4021 in the FPGA acquisition board 4022, the digital signal is compressed and processed, and the compressed signal is cached in the DDR synchronous dynamic random access memory 4023, and at the same time the frequency is set in advance. The digital signal is extracted for fast Fourier transform, and the ARM processor embedded in the FPGA acquisition board 4022 is used to judge the trigger cycle. The judgment includes similar waveform judgment, amplitude trigger judgment and frequency drift judgment. It should be understood that, in practical applications, any one of the three independent acquisition systems determines that the current acquisition cycle is the trigger cycle, and while storing data, the FPGA acquisition board 4022 sends a trigger signal to the main board 403, and the main board receives After the trigger signal is received, the acquisition signal is sent to the other two independent acquisition systems, so that the three independent acquisition systems can simultaneously acquire the signals of the current cycle.

Preferably, the signal conditioning acquisition circuit 4021 mainly includes three parts, namely a voltage follower, a single-end to differential conversion processor, and an A/D acquisition circuit. Preferably, since the negative feedback terminal of the voltage follower is connected with a resistance of 0Ω, the output voltage of the voltage follower is close to the input voltage range, and the signal terminal to be tested is in a high-impedance state, and the subsequent circuit is in a low-impedance state. The front and back stage circuits play the role of "isolation". Among them, the latter stage circuit mainly refers to the single-ended to differential processor and the A/D acquisition circuit. Preferably, the AD8138 amplifier used by the single-ended-to-differential processor can provide output gain and phase matching balance by using its internal feedback characteristics, thereby suppressing even-order harmonics, while using a high-speed 12-bit A/A with a maximum frequency of 20MHz The D chip AD9224 suppresses the common mode noise of the signal to be tested and further reduces interference. Preferably, the A/D acquisition circuit mainly adopts the AD9224 chip, with a maximum sampling rate of up to 40MHz and a signal-to-noise ratio of up to 68.3dB. It has a built-in high-performance sample-and-hold amplifier and reference voltage source, adopts a differential pipeline architecture, and has built-in output error correction logic to ensure no missing codes in the entire operating temperature range and realize high-speed data acquisition.

Preferably, the DDR synchronous dynamic random access memory 4023 is used for buffering the compressed digital signal and storing the data of the trigger period, the data of the first three periods of the trigger period and the data of the subsequent two periods. Taking the judgment of similar waveforms as an example, when the DDR synchronous DRAM 4023 is caching, it will buffer the data of three cycles, waiting for the judgment result of the current cycle by the FPGA acquisition board 4022, if the waveform of the current cycle is the same as the waveform of the previous cycle If it is a similar waveform, the first cached cycle data will be cleared to store the data of the current cycle. If the waveform of the current cycle is not similar to the waveform of the previous cycle, the data of the current cycle and the first three The data of one cycle and the data of the next two cycles are stored. When the data of the next cycle needs to be cached, the cache starts from the next empty byte of the storage location.

Preferably, the independent acquisition unit 402 also includes a network interface 4024 for data transmission between the independent acquisition system 402 and the host computer waveform observation and processing device 401 . The network interface 4024 mainly uses the TCP/IP protocol for network transmission.

Preferably, the independent acquisition unit 402 also includes a serial port 4025 for reading the calibration data sent by the GPS module 404 .

Preferably, the mainboard 403 supplies power for the independent acquisition system 402, and after receiving the trigger signal sent by the independent acquisition system 402, sends acquisition signals to the other two independent acquisition systems 402, and at the same time connects the GPS module 404 externally to receive the signal sent by the GPS module 404. Clock calibration data.

Preferably, the overvoltage monitoring system 400 also includes a GPS module 404, connected to the mainboard, used for clock calibration and self-timekeeping of the independent acquisition system 402; SPI interface 405, used for communication between the independent acquisition system 402 and the mainboard 403 and the system control board 406, which is used for parameter setting and the restart of the FPGA acquisition board 4021.

The invention has been described with reference to a small number of embodiments. However, it is clear to a person skilled in the art that other embodiments than the invention disclosed above are equally within the scope of the invention, as defined by the appended patent claims.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise therein. All references to "a/the/the [means, component, etc.]" are openly construed to mean at least one instance of said means, component, etc., unless expressly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

Claims (14)

1. a kind of monitoring method of power network overvoltage, including：

The basic parameter of setting over-voltage monitoring；

Collection voltages data are simultaneously compressed and cache, and carry out fast Fourier change with predetermined decimation in frequency data to data Change FFT；

Judged by similar waveform, amplitude triggering judges or frequency drift judges, whether the current period for judging voltage data is The triggering cycle；

If current period is the triggering cycle, by the data in the data of current period and first three cycle of current period with after In continuing the data Cun Chudao DDR synchronous DRAMs in two cycles, and it is sent to host computer；And

If current period is not the triggering cycle, using the data of next cycle to delaying in DDR synchronous DRAMs The cycle data for most starting deposited is covered.

2. method according to claim 1, it is characterised in that the basic parameter includes：Data sampling rate F, most short biography Record deviation △ y, maximum storage interval N, minimum storing frequencies Fk, FFT frequency drift threshold value △ f, FFT fundamental voltage amplitude threshold value △ g And root mean square threshold value △ rms.

3. method according to claim 1, it is characterised in that it is described data are compressed including：By in current period First sampled point X_iCharacteristic point is recorded as, next sampled point X is then judged_i+1With X_iBetween difference absolute value it is whether little In △ y, if the difference is more than or equal to △ y, X is cached_i+1Value and with X_i+1Next second compression is carried out for new characteristic point, Until a cycle terminates；If the difference is less than △ y, the value of quantity a of compression point adds 1, when a is deposited more than or equal to maximum During the N of storage interval, X is cached_i+1Value and with X_i+1Next second compression is carried out for new characteristic point, until a cycle terminates.

4. method according to claim 2, it is characterised in that the similar waveform is judged as：When data acquisition is carried out, The root mean square of the value of the measuring point of each measuring point and corresponding upper a cycle of current period is calculated, if described square The value of root is more than root mean square threshold value △ rms, then the waveform of current period and upper a cycle is dissimilar, then current period is triggering There are 16 measuring points in cycle, wherein each cycle, the maximum, minimum of a value and maximum respectively in each cycle with most 14 points of uniform collection between little value.

5. method according to claim 2, it is characterised in that the amplitude triggering is judged as：Data after to carrying out FFT Judged, if the fundamental voltage amplitude component for carrying out the data after FFT is more than FFT fundamental voltage amplitude threshold value △ g, current period To trigger the cycle.

6. method according to claim 2, it is characterised in that the frequency drift is judged as：Data after to carrying out FFT Judged, if the frequency departure for carrying out the data after FFT is more than FFT frequency drift threshold value △ f, current period is tactile The cycle of sending out.

7. method according to claim 1, it is characterised in that when monitoring is started, by the pulse per second (PPS) for obtaining GPS module The automatic time service of local clock is carried out, and is carried out from punctual operation with the clock frequency of 100MHz.

8. method according to claim 1, it is characterised in that before signals collecting is carried out, carry out to measured signal every From, suppress even-order harmonics and common-mode noise operation.

9. method according to claim 1, it is characterised in that by the data in triggering cycle and triggering cycle first three When the data is activation in the data in individual cycle and follow-up two cycles is to host computer, the data volume for sending every time is set, and with multiple Circulation pattern sends.

10. a kind of monitoring system of power network overvoltage, including：

Host computer waveform observation processing meanss, for carry out the display of over-voltage waveform, amplification, analysis, the inquiry of historical data with And preserve, and can actively trigger independent acquisition unit and carry out data acquisition；

Three road independent acquisition units, for gathering, judging and storing over-voltage waveform signal；And

Mainboard, is three road independent acquisition system power supplies, sends collection signal and external GPS module；

Wherein, include per road independent acquisition system：

Signal condition Acquisition Circuit, for realizing the collection and conversion of overvoltage signal；

FPGA collection plates, the data signal for gathering to signal condition Acquisition Circuit and changing is compressed, synchronous to extract numeral letter Fast Fourier Transform (FFT) number is carried out, and the judgement in triggering cycle is carried out using embedded arm processor；And

DDR synchronous DRAMs, for being compressed the caching and the data in triggering cycle of rear data signal and touching The data and the data storage in follow-up two cycles in first three cycle in the cycle of sending out.

11. systems according to claim 10, it is characterised in that described that the system that electrical network carries out over-voltage monitoring is also wrapped Include：

GPS module, is connected with mainboard, clock alignment for three road independent acquisition systems and from punctual；

SPI interface, for the communication between three road independent acquisition systems and mainboard；And

System control panel, for restarting for parameter setting and FPGA collection plates.

12. systems according to claim 10, it is characterised in that described also to include per road independent acquisition system：

Network interface, processes software and carries out data transmission for independent acquisition system and host computer waveform observation；And

Serial ports, for reading the calibration data of GPS module transmission.

13. systems according to claim 10, it is characterised in that the signal condition Acquisition Circuit includes：

Voltage follower, for isolating measured signal and late-class circuit, wherein the late-class circuit is single-ended transfer difference processor With A/D Acquisition Circuits；

Single-ended transfer difference processor, for suppressing the even-order harmonics and common-mode noise of measured signal；And

A/D Acquisition Circuits, for the measured signal after process to be acquired and changed.

14. systems according to claim 10, it is characterised in that when arbitrarily independently adopting all the way in three road independent acquisition systems Collecting system judges that current collection period is the triggering cycle, and while data storage is carried out, FPGA collection plates to mainboard sends Trigger, mainboard is received after trigger, sends collection signal to another two-way independent acquisition system, makes three road independent acquisitions System is acquired to the signal of current period simultaneously.