CN117116311A - Multichannel trigger readout circuit with time interval measurement function - Google Patents
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Abstract
The invention discloses a multichannel trigger readout circuit with a time interval measurement function. The circuit comprises: a plurality of time measurement modules, a multiplexer; the time measurement module is connected with the working clock and is used for measuring the time stamp information of the trigger signal; the multiplexer is connected with a plurality of time measurement modules and is used for fusing and reading out a plurality of time stamp information to the data bus. The invention solves the problem that data is easy to lose in the high-speed sampling of the nuclear event by the parallel sampling of the multiple channels, solves the problem of sparseness and randomization of the reading result of the timestamp information by adding the token ring manager, and solves the problem of low time precision by adding the clock phase shift unit.
Description
Technical Field
The invention relates to the technical field of high-integration read-out electronics signal acquisition and transmission of a nuclear detector, in particular to a multichannel trigger read-out circuit with a time interval measurement function.
Background
The heavy ion accelerator is a device for generating heavy ion beams by using an artificial technology method, and has important and wide application in the aspects of industrial and agricultural production, medical and health, national defense construction and the like. Large heavy ion comprehensive research devices, such as German FAIR, french SPIRAL-II, american FRIB, china HIAF and the like, are currently being upgraded and built internationally. The strong-current heavy ion accelerator-radioactive secondary beam separation line (HIAF-HFRS) in the construction of China is a new-generation radioactive beam line with higher beam energy and intensity; when the beam inflow jet intensity reaches 109pps, the large area particle discrimination position TPC detector operating at the defocus plane on the beam line will be subjected to high particle counts (greater than 100 kHz), thus placing higher demands on the front-end readout electronics.
With the continuous development of technology, the requirements of the fields of nuclear experiments, nuclear medicine and the like on a high-integration nuclear detector readout electronics signal acquisition system are higher and higher. Conventional discrete component designs have limitations in meeting this requirement, while ASIC chips can provide higher integration and better performance. In order to realize a high-speed, high-integration and high-precision front-end readout electronic system, some time data readout architectures with data buffer units inside are gradually proposed and implemented in a front-end readout ASIC (Application Specific Integrated Circuit) chip. The chip outputs the time stamp information of the core event, so that the influence caused by a subsequent processing circuit (such as an FPGA) and the wiring delay can be effectively reduced.
In the research and practice of the prior art, the trigger readout circuit integrated in the ASIC chip at present has the problems that sampling data is easy to lose, the time accuracy is not high and the like in the high-speed sampling process of the nuclear event.
Disclosure of Invention
In order to solve at least one technical problem, the invention provides a multi-channel trigger readout circuit with a time interval measurement function, so as to solve the problems of data loss and low time precision when the time interval measurement is performed on a trigger signal.
There is provided a multi-channel trigger readout circuit with time interval measurement function, comprising: a plurality of time measurement modules, a multiplexer;
the time measuring module is connected with the working clock and is used for measuring the time stamp information of the trigger signal;
the multiplexer is connected with a plurality of the time measurement modules and used for fusing and reading out a plurality of the time stamp information to the data bus.
Preferably, the time measurement module includes: FIFO memory, time interval measurement unit;
the time interval measuring unit is connected with the working clock and the FIFO memory and is used for measuring the time stamp information of the trigger signal and transmitting the time stamp information to the FIFO memory;
the FIFO memory is connected with the multiplexer and is used for transmitting the time stamp information to the multiplexer.
Preferably, the method further comprises: a plurality of AND gate and poll modules;
the polling module is connected with each FIFO memory and is used for polling each FIFO memory when at least one FIFO memory stores the timestamp information;
the first input end of each AND gate is connected with the polling module, the second input end is respectively connected with the E pin of each FIFO memory after the inversion, and the output end is connected with the multiplexer and the R pin of the FIFO memory and used for controlling the multiplexer to read the polled timestamp information.
Preferably, the polling module includes: a NAND gate, token ring manager;
the input ends of the NAND gate are respectively connected with the E pin of each FIFO memory, the output end of the NAND gate is connected with the token ring manager, and the NAND gate is used for detecting whether at least one FIFO memory stores the timestamp information; if yes, the token ring manager polls each time detection module; if not, the token ring manager stops polling at the current time detection module.
Preferably, the device further comprises a clock phase shift unit;
the clock phase shift unit is connected with the working clock and a plurality of time interval measuring units and used for acquiring a plurality of phase shift clock signals and transmitting each phase shift clock signal to the plurality of time interval measuring units;
the time interval measuring unit obtains a coarse time stamp according to the signal period multiple relation between the trigger signal and the working clock;
and the time interval measuring unit obtains a fine time stamp according to jump positions of the trigger signals in the phase shift clock signals.
Preferably, the FIFO memory connected to the multiplexer comprises:
the FIFO memory receives framing commands from the edge detection unit, and frames the coarse time stamp, the fine time stamp, the channel number and the parity group into data packets;
the multiplexer reads the data packet out to the data bus.
Preferably, the time measurement module further comprises a metastable processing unit for reducing the metastable generation probability;
wherein the steady-state processing unit comprises two stages of registers.
Preferably, the plurality of phase-shifted clock signals are a phase-shifted clock signal, and a phase-shifted clock signal.
Preferably, the data packet size is 24 bits, wherein the channel number is 6 bits, the coarse timestamp is 13 bits, the fine timestamp is 4 bits, and the parity bit is 1bit.
Preferably, the clock phase shift unit includes: a plurality of inverters, a phase frequency detector and a charge pump;
the phase-shifting low-pass shaping module comprises a plurality of inverters, a voltage-controlled resistor and a capacitor, wherein the inverters are sequentially connected in series, and the voltage-controlled resistor and the capacitor are connected in series and connected in parallel to the output end of each inverter so as to form a phase-shifting low-pass shaping module;
the output ends of the phase frequency detector are respectively connected with the input ends of the charge pump, the output end of the charge pump is connected with the adjusting end of each voltage-controlled resistor, and the voltage-controlled resistor is used for comparing the working clock with the clock output by the phase-shifting low-pass shaping model, and adjusting the voltage-controlled resistors to obtain a plurality of phase-shifting clock signals.
The invention provides a multichannel trigger readout circuit with a time interval measurement function, which comprises: a plurality of time measurement modules, a multiplexer; the time measurement module is connected with the working clock and is used for measuring the time stamp information of the trigger signal; the multiplexer is connected with a plurality of time measurement modules and is used for fusing and reading out a plurality of time stamp information to the data bus. The sampling information is ensured not to be lost through multichannel high-speed parallel time interval measurement, a polling module is provided to solve the problems of randomness and sparsity of read data, and a clock phase shift unit is provided to solve the problem of insufficient time precision.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the embodiments of the present invention or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present invention or the background art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic structural diagram of a multi-channel trigger readout circuit with a time interval measurement function according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the connection of a FIFO memory, multiplexer, AND gate, NAND gate and token ring manager according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a multi-channel trigger readout circuit with time interval measurement according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of clock phase shift according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a fine measurement of a time interval measurement module according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a data format of a data packet according to an embodiment of the present invention;
FIG. 7 is a timing diagram of data output according to an embodiment of the present invention;
FIG. 8 is a block diagram of a test system according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a clock phase shift unit according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
At present, in the high-speed detection of a core event, a plurality of time data reading architectures with data caching units inside are gradually proposed and realized in a front-end reading ASIC chip, and in order to solve the problems that timestamp data are easy to lose and time precision is not high enough in the telling and sampling of the core event, the invention provides a multi-channel triggering reading circuit with a time interval measurement function.
A multi-channel trigger readout circuit with time interval measurement function, referring to fig. 1, comprising: a plurality of time measurement modules, a multiplexer;
the time measurement module is connected with the working clock and is used for measuring the time stamp information of the trigger signal;
the multiplexer is connected with a plurality of time measurement modules and is used for fusing and reading out a plurality of time stamp information to the data bus.
It should be noted that Ch1, ch2, ch3, ch4 and Ch5 in fig. 1 respectively represent time measurement modules, and 5 time measurement modules are only one specific embodiment provided by the present invention.
In this embodiment, the working clock frequency is 128MHz, and one working clock period is about 8ns, so that the minimum measurement accuracy of the time measurement module is 8ns, a sampling signal is obtained by sampling a trigger signal, the sampling signal is pulse-filled with the working clock signal, then how many periods the sampling signal occupies the working clock signal is calculated, and a specific detection time interval is obtained, for example, the sampling signal a occupies the working clock signal of 3 periods, and then the time interval of the trigger signal is 24ns.
In order to reduce the problem of losing the detection time of the core event, a multi-channel parallel high-speed sampling mode is adopted to ensure that the detection time of the core event is not lost.
In this embodiment, the trigger signal is detected in parallel at a high speed by using the detection of multiple time detection modules, and then the detection results of all the time detection modules are combined into one piece of time stamp information by the multiplexer, and the time stamp information is read out to the data bus. In this embodiment, as long as one of Ch1, ch2, ch3, ch4, and Ch5 detects the time stamp information of the trigger signal, the multiplexer can read out the time stamp information and generate the time stamp information to the data bus, thereby solving the problem that the single channel acquisition signal is easy to be lost.
Preferably, the time measurement module includes: FIFO memory, time interval measurement unit;
the time interval measuring unit is connected with the working clock and the FIFO memory and is used for measuring the time stamp information of the trigger signal and transmitting the time stamp information to the FIFO memory;
the FIFO memory is connected to the multiplexer for transmitting the time stamp information to the multiplexer.
FIFO memory refers to First-In-First-Out (FIFO) memory, also known as a queue. It is a common data structure used to store and read data in a particular order in a computer system. FIFO memories are often used in the context of buffered data transfer, task scheduling, and process management. It can ensure that the processing is performed according to the sequence of data entry, and follows the principle of first-in first-out, so that the processing of the data has consistency.
In this embodiment, the time detection unit measures the trigger signal to obtain the time stamp information, the detected time stamp information is stored in the buffer of the FIFO memory, the multiplexer is connected to the FIFO memory in each time measurement module, so as to directly read the stored time stamp information from the buffer of the FIFO memory, and combines the read plurality of time stamp information into one time stamp to be output to the data bus, for example, time a reads time stamp a, time b reads time stamp b, time c reads time stamp c, and the data bus reads result "time stamp information a-empty-time stamp information b-empty-time stamp information c".
Preferably, the method further comprises: a plurality of AND gate and poll modules;
the polling module is connected with each FIFO memory and is used for polling each FIFO memory when at least one FIFO memory stores time stamp information;
the first input end of each AND gate is connected with the polling module, the second input end is respectively connected with the E pin of each FIFO memory after the inversion, and the output end is connected with the multiplexer and the R pin of the FIFO memory and used for controlling the multiplexer to read the polled timestamp information.
It should be noted that the FIFO memory has an F pin, an E pin, a W pin, and an R pin. The F pin is a full pointer, which indicates that the queue is full and new data cannot be written; the E pin is a null pointer, which indicates that the queue is null and no readable data exists; the W pin is a write pointer, representing the position where the next data is to be written into the queue; the E pin is a read pointer indicating the location of the next data to be read.
When the multiplexer directly reads the time stamp information from the FIFO memory, there are problems of rarefaction and randomization of the data bus read-out result, for example, the data bus read-out result a "time stamp information a-empty-time stamp information b-empty-time stamp information c", and if the arrival time interval of the two trigger signals is too large, the 'empty' reading is too frequent, which is not only unfavorable for the subsequent data processing due to the data redundancy, but also increases unnecessary energy consumption.
In this embodiment, the polling module is connected to each FIFO memory, the first input end of each and gate is connected to the polling module, the second input end is connected to the E pin of each inverted FIFO memory, and the output end is connected to the multiplexer and the R pin of the FIFO memory, so that when at least one FIFO memory stores time stamp information, each FIFO memory is polled, and the position information of the polled time stamp information is transmitted to the multiplexer, and the multiplexer reads the time stamp information stored in the buffer of the FIFO memory through the position information. The data bus reading result B 'timestamp information a-timestamp information B-timestamp information c' is obtained through processing of a plurality of AND gates and polling modules, so that the reading result is more simplified, the data reading de-sparsification and de-randomization are realized, the use efficiency of the multiplexer is further improved, and the energy consumption is saved.
Preferably, the polling module includes: a NAND gate, token ring manager;
the input ends of the NAND gate are respectively connected with the E pin of each FIFO memory, the output end of the NAND gate is connected with the token ring manager, and the NAND gate is used for detecting whether at least one FIFO memory stores time stamp information; if yes, the token ring manager polls each time detection module; if not, the token ring manager stops polling at the current time detection module.
In this embodiment, referring to fig. 2, mux is a multiplexer, and data bus is a data bus. The E pins of each FIFO memory are respectively connected with a plurality of input ends of a NAND gate, and the number of the input ends of the NAND gate is consistent with that of the time measurement modules. When all the FIFO memories do not store the time stamp information, the E pins of all the FIFO memories output high level, namely the NAND gate input is high level, the NAND gate output is low level to control the token ring manager to stop polling at the current time detection module until at least one FIFO memory stores the time stamp information, and the NAND gate outputs high level to control the token ring manager to continue polling work.
Preferably, the device further comprises a clock phase shift unit;
the clock phase shift unit is connected with the working clock and a plurality of time interval measuring units and is used for acquiring a plurality of phase shift clock signals and transmitting each phase shift clock signal to the plurality of time interval measuring units;
the time interval measuring unit obtains a coarse time stamp according to the signal period multiple relation between the trigger signal and the working clock;
and the time interval measuring unit obtains a fine time stamp according to jump positions of the trigger signal in the plurality of phase-shift clock signals.
In this embodiment, the working clock frequency is 128MHz, one working clock period is about 8ns, the minimum measurement precision of the time measurement module is 8ns, and the precision cannot meet the core event of high-speed sampling, so a time interval measurement method of "coarse measurement" combined with "fine measurement" is provided, wherein the "coarse measurement" is an electronic counting method, i.e. pulse filling is performed on a trigger signal through a working clock signal, then how many cycles the trigger signal occupies the working clock signal are calculated, for example, the trigger signal a occupies 3 cycles of the working clock signal, and then the time interval of the trigger signal is 24ns, thereby obtaining a coarse timestamp. The fine measurement obtains a plurality of phase shift clock signals of the working clock through a clock phase shift unit, and a fine time stamp is obtained according to jump positions of the trigger signal in the plurality of phase shift clock signals. A more accurate time stamped signal can be obtained by combining the coarse time stamp with the fine time stamp.
Preferably, the FIFO memory is connected to the multiplexer comprising:
the FIFO memory receives framing commands from the edge detection unit, and frames the coarse time stamp, the fine time stamp, the channel number and the parity check bit group into data packets;
the multiplexer reads out the data packets to the data bus.
In this embodiment, referring to fig. 3, in order to better maintain the consistency and integrity of data in the multiplexing transmission process, one path of the trigger signal passes through the time measurement module to obtain a fine time stamp and a coarse time stamp, and the other path passes through the edge detection unit to generate a framing command, the FIFO memory receives the framing command from the edge detection unit, frames the coarse time stamp, the fine time stamp, the channel number and the parity bit group into a data packet, and then the data packet is transmitted to the data bus in parallel through the multiplexer, and the time detection module corresponding to the coarse time stamp and the fine time stamp in the data packet can be known through the channel number in the data packet.
Preferably, the time measurement module further comprises a metastable processing unit for reducing the metastable generation probability;
wherein the steady-state processing unit comprises two stages of registers.
Metastable state refers to an unstable state of a signal during sampling, such as abrupt changes in amplitude, frequency, or phase of the signal, waveform distortions, and the like. This unsteady state phenomenon may cause the sampling result to be inconsistent or distorted with the original signal. The setup time refers to the time required for a signal to transition from an unsteady state to a steady state. The setup time depends on the characteristics of the signal and the response speed of the sampling system. In general, a shorter setup time can ensure more accurate sampling results. The hold time refers to the maximum time that the sampling system can hold an effective sample of the steady state signal at the steady state signal. The hold time is limited by the nature of the sampling system itself and the storage medium. Generally, the longer the hold time, the more signal information can be collected, but the system cost and complexity are increased.
In this embodiment, the probability of occurrence of a metastable state in the signal acquisition process is reduced by a two-stage register composed of two flip-flops, which are connected in series. The first flip-flop is called a master flip-flop, and the second flip-flop is called a slave flip-flop, and stores the time stamp information in the FIFO memory on the rising edge or the falling edge of the clock signal and outputs it to the slave flip-flop, which holds the output of the master flip-flop after receiving it and outputs it through the output port on the next clock cycle. The metastability problem is not completely avoided and the present embodiment allows the circuit to meet the setup time and hold time by means of two stages of registers.
Preferably, referring to fig. 4, the plurality of phase-shifted clock signals are a 0 ° phase-shifted clock signal, a 90 ° phase-shifted clock signal, a 180 ° phase-shifted clock signal, and a 270 ° phase-shifted clock signal.
In this embodiment, under the condition of ensuring that the metastable state probability is the lowest, the adopted plurality of phase shift clock signals CLK0 are 0 ° phase shift clock signals, CLK1 are 90 ° phase shift clock signals, CLK2 are 180 ° phase shift clock signals and CLK3 are 270 ° phase shift clock signals, so that the time resolution precision of the working clock can be improved by 4 times, that is, the measurement precision with the precision of 2ns can be realized. Referring to fig. 5, trigger is a trigger signal, and CLK0 is "1", CLK1 is "1", CLK2 is "0", and CLK3 is "0", so that the output code is "1100" at this time, which means that the fine measurement time is 4ns at this time, and the final measurement result at this time is "16ns+4ns" assuming that the coarse measurement time is 16ns at this time. The phase shift clock measurement results are shown in table 1 below, where the output code is shifted left as the measured signal phase increases. Since the measured signal fine measurement data is to be effectively stored without being covered by resampling, the fine measurement data is latched at the second rising edge of the 270 ° phase clock after the measured signal transitions, and the encoded output result is "1111".
TABLE 1
Preferably, the packet size is 24 bits, with the channel number accounting for 6 bits, the coarse timestamp accounting for 13 bits, the fine timestamp accounting for 4 bits, and the parity accounting for 1bit.
In this embodiment, referring to fig. 6, CH num represents a channel number, TC represents a thin timestamp, time Stamp represents a thick timestamp, and P represents a parity bit. The data structure with the data packet size of 24 bits is adopted, wherein the channel number occupies 6 bits, the coarse time stamp occupies 13 bits, the fine time stamp occupies 4 bits, and the parity check bit occupies 1bit to transmit the time stamp information. Referring to fig. 7, in order to improve data transmission efficiency, 24bit data packets are framed into 4 6bit packets and transmitted to a data bus in parallel.
When the multi-channel trigger readout circuit with time interval measurement function is integrated in an ASIC chip and applied to nuclear event detection, referring to fig. 8, the detection system is composed of four parts: the system comprises a detector, a test board, an FPGA development board and an upper computer, wherein the test board consists of an analog front-end circuit, a multichannel trigger readout circuit, a power supply unit and a high-precision ADC. The test board collects the energy path information and the time path information of the detector signals, then transmits the information to the FPGA development board through the high-speed interface, and uploads the information to the upper computer for data analysis after being processed by the FPGA. Storing the time stamp information of the detected signal by a multi-channel internal buffer unit, and carrying out logic processing and framing; simultaneously storing the energy information of the detected signals, and converting the random input signals into periodic reading; thereby reducing the complexity of back-end ADC (Analog-to-Digital Converter) and FPGA (Field Programmable Gate Array) processing and reducing system dead time.
Preferably, the clock phase shift unit includes: a plurality of inverters, a phase frequency detector and a charge pump;
the phase-shifting low-pass shaping module comprises a plurality of inverters, a voltage-controlled resistor and a capacitor, wherein the inverters are sequentially connected in series, and the voltage-controlled resistor and the capacitor are connected in series and connected to the output end of each inverter in parallel and are used for forming a phase-shifting low-pass shaping module;
the output ends of the phase frequency detector are respectively connected with the input ends of the charge pump, the output end of the charge pump is connected with the adjusting end of each voltage-controlled resistor, and the phase frequency detector is used for comparing the working clock with the clock output by the phase-shift low-pass shaping model, adjusting the voltage-controlled resistors and obtaining a plurality of phase-shift clock signals.
In this embodiment, referring to fig. 9, PFD is a phase frequency detector, CP is a charge pump, INV is an inverter, R is a voltage-controlled resistor, and C is a capacitor. The voltage-controlled resistor and the capacitor are connected in series and connected in parallel to the output end of each inverter in series through a plurality of inverters to form a 90-degree phase shift low-pass shaping model. The two 90-degree phase shift low-pass shaping models are connected in series to form a 180-degree phase shift low-pass shaping model. The output ends of the phase frequency detector are respectively connected with the input ends of the charge pump, and the output end of the charge pump is connected with the regulating end of each voltage-controlled resistor. The phase frequency detector compares the input clock with the 180 DEG phase shifted inverted output, and then adjusts the voltage controlled resistor through the charge pump to obtain the corresponding phase delay.
The invention provides a multichannel trigger readout circuit with a time interval measurement function, which comprises: a plurality of time measurement modules, a multiplexer; the time measurement module is connected with the working clock and is used for measuring the time stamp information of the trigger signal; the multiplexer is connected with a plurality of time measurement modules and is used for fusing and reading out a plurality of time stamp information to the data bus. The sampling information is ensured not to be lost through multichannel high-speed parallel time interval measurement, a polling module is provided to solve the problems of randomness and sparsity of read data, and a clock phase shift unit is provided to solve the problem of insufficient time precision.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A multi-channel trigger readout circuit with time interval measurement function, comprising: a plurality of time measurement modules, a multiplexer;
the time measuring modules are connected with the same working clock and are used for measuring time stamp information of the trigger signals;
the multiplexer is connected with a plurality of the time measurement modules and used for fusing and reading out a plurality of the time stamp information to the data bus.
2. The multi-channel trigger readout circuit with time interval measurement function of claim 1, wherein the time measurement module comprises: FIFO memory, time interval measurement unit;
the time interval measuring unit is connected with the working clock and the FIFO memory and is used for measuring the time stamp information of the trigger signal and transmitting the time stamp information to the FIFO memory;
the FIFO memory is connected with the multiplexer and is used for transmitting the time stamp information to the multiplexer.
3. A multi-channel trigger readout circuit with time interval measurement function according to claim 2, further comprising: a plurality of AND gate and poll modules;
the polling module is connected with each FIFO memory and is used for polling each FIFO memory when at least one FIFO memory stores the timestamp information;
the first input end of each AND gate is connected with the polling module, the second input end of each AND gate is respectively connected with the E pin of each FIFO memory after being inverted, and the output end of each AND gate is connected with the multiplexer and the R pin of the FIFO memory and is used for controlling the multiplexer to read the polled timestamp information.
4. A multi-channel trigger readout circuit with time interval measurement according to claim 3, wherein the polling module comprises: a NAND gate, token ring manager;
the input ends of the NAND gate are respectively connected with the E pin of each FIFO memory, the output end of the NAND gate is connected with the token ring manager, and the NAND gate is used for detecting whether at least one FIFO memory stores the timestamp information; if yes, the token ring manager polls each time detection module; if not, the token ring manager stops polling at the current time detection module.
5. The multi-channel trigger readout circuit with time interval measurement function according to claim 2, further comprising a clock phase shift unit;
the clock phase shift unit is connected with the working clock and a plurality of time interval measuring units and used for acquiring a plurality of phase shift clock signals and transmitting each phase shift clock signal to the plurality of time interval measuring units;
the time interval measuring unit obtains a coarse time stamp according to the signal period multiple relation between the trigger signal and the working clock;
and the time interval measuring unit obtains a fine time stamp according to jump positions of the trigger signals in the phase shift clock signals.
6. The multi-channel trigger readout circuit with time interval measurement function of claim 5, wherein the FIFO memory is connected to the multiplexer comprising:
the FIFO memory receives framing commands from the edge detection unit, and frames the coarse time stamp, the fine time stamp, the channel number and the parity group into data packets;
the multiplexer reads the data packet out to the data bus.
7. The multi-channel trigger readout circuit with time interval measurement function according to claim 5, wherein the time measurement module further comprises a metastable processing unit for reducing a metastable generation probability;
wherein the steady-state processing unit comprises two stages of registers.
8. The multi-channel trigger readout circuit with time interval measurement according to claim 5, wherein the plurality of phase-shifted clock signals are a 0 ° phase-shifted clock signal, a 90 ° phase-shifted clock signal, a 180 ° phase-shifted clock signal, and a 270 ° phase-shifted clock signal.
9. The multi-channel trigger readout circuit with time interval measurement according to claim 6, wherein the packet size is 24 bits, wherein the channel number is 6 bits, the coarse timestamp is 13 bits, the fine timestamp is 4 bits, and the parity bit is 1bit.
10. The multi-channel trigger readout circuit with time interval measurement function according to claim 5, wherein the clock phase shift unit comprises: a plurality of inverters, a phase frequency detector and a charge pump;
the phase-shifting low-pass shaping module comprises a plurality of inverters, a voltage-controlled resistor and a capacitor, wherein the inverters are sequentially connected in series, and the voltage-controlled resistor and the capacitor are connected in series and connected in parallel to the output end of each inverter so as to form a phase-shifting low-pass shaping module;
the output ends of the phase frequency detector are respectively connected with the input ends of the charge pump, the output end of the charge pump is connected with the adjusting end of each voltage-controlled resistor, and the voltage-controlled resistor is used for comparing the working clock with the clock output by the phase-shifting low-pass shaping model, and adjusting the voltage-controlled resistors to obtain a plurality of phase-shifting clock signals.
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| CN118473552A (en) * | 2024-07-09 | 2024-08-09 | 深圳市华茂欧特科技有限公司 | Method, device, equipment and medium for measuring data transmission duration of communication system |
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