CN106773613A - Time-to-digit converter and Method Of Time Measurement - Google Patents

Abstract

A kind of time-to-digit converter and Method Of Time Measurement are provided.Time-to-digit converter includes：Unordered signal generation unit, for generating multiple unordered clock signals；Multiple unordered clock signals, for receiving multiple unordered clock signals and input signal to be measured, are sampled, and export corresponding actual samples result by sampling unit using input signal to be measured；Decoding unit, for receiving actual samples result, and time difference of the certain edges thereof of the selected clock signal in the certain edges thereof edge and multiple unordered clock signals of input signal to be measured between is determined according to actual samples result and the timing information related to the sequential of multiple unordered clock signals, to obtain the thin time result of input signal to be measured；And thick time counting unit, for receiving selected clock signal and input signal to be measured, and input signal to be measured is counted using selected clock signal as counting clock, to obtain the thick time result of input signal to be measured.The temporal resolution of the TDC is high.

Description

Time-to-digit converter and Method Of Time Measurement

Technical field

The present invention relates to circuit field, in particular it relates to a kind of time-to-digit converter and Method Of Time Measurement.

Background technology

High-precision time-to-digit converter (Time-to-Digital Converters, TDC) technology is widely used in The fields such as time and frequency measurement, satellite navigation, radar fix, laser ranging, medical treatment, nuclear physics and particle physics detection.The time of TDC Resolution ratio largely affects the advanced degree in these fields.With medical whole body Positron emission tomography technology (PET) system As a example by system, compared to PET of the tradition without TDC, temporal resolution for 600ps based on the flight time (Time of flight, TOF) signal noise ratio (snr) of image of the PET (referred to as TOF-PET) of technology can improve 2.1 times, and temporal resolution is the TOF- of 100ps The signal noise ratio (snr) of image of PET can improve 5.2 times.

The method that thick time measurement is combined with fine measurement is widely used in TDC at present.Thick time measurement is profit Input signal to be measured is counted with counting clock, when the high level for calculating input signal to be measured according to count results continues Between.Measured by above-mentioned thick Method Of Time Measurement and deposited between the high level lasting time and the high level lasting time of reality that obtain In error, the edge (mainly being illustrated by taking rising edge as an example herein) and the side of counting clock of error amount and input signal to be measured Time difference correlation between.The time difference can be measured by fine measurement method.

At present the most frequently used fine measurement method be based on FPGA (Field Programmable Gate Array, FPGA) the time-sensitive target of internal additions carry chain.The principle of time-sensitive target is to input letter to be measured using addition carry chain Number multiple time delay is carried out, all time delayed signals are latched using counting clock, and " 1111 ... obtained according to latch 1110000 ... 00 " position that 1-0 has a common boundary in sequence is calculated between the rising edge and the rising edge of counting clock of input signal to be measured Time difference.In order to correctly determine the position of 1-0 boundaries, it is necessary to keep the phase of time delayed signal orderly.For example, addition carry chain In the output of n-th adder time delayed signal the rising edge of time delayed signal that should be exported than (n-1)th adder of rising edge Delayed a period of time.Each time delayed signal received by latch units is needed to keep above-mentioned orderly phase relation, and this may be needed To be controlled by extra hardware resource.If the phase relation of time delayed signal is disturbed, the precision of time measurement can be received To influence.Further, since there is the addition carry chain of some BIN larger (100ps or so) wide in FPGA inside, therefore when limiting Between interpolation method temporal resolution.Method at present mostly using customization ripple (Wave Union) is wide to eliminate these larger BIN Influence, but the FPGA internal resources of consumption are more, and produce " bubble " phenomenon to be difficult to due to register metastable state phenomenon Solve.

Accordingly, it is desirable to provide a kind of improved time measurement technology, to solve at least in part present in prior art Above mentioned problem.

The content of the invention

In order to solve problems of the prior art at least in part, according to an aspect of the present invention, there is provided a kind of Time-to-digit converter.The time-to-digit converter includes：Unordered signal generation unit, for generating multiple unordered clock letters Number；Sampling unit, is connected with unordered signal generation unit, for receiving multiple unordered clock signals and input signal to be measured, Multiple unordered clock signals are sampled using input signal to be measured, and exports corresponding actual samples result；Decoding is single Unit, is connected with sampling unit, for receiving actual samples result, and believes according to actual samples result and with multiple unordered clocks Number the related timing information of sequential determine the certain edges thereof of input signal to be measured along with multiple unordered clock signals in it is selected Time difference of the certain edges thereof of clock signal between, to obtain the thin time result of input signal to be measured；And thick time counting Unit, is connected with unordered signal generation unit, for receiving selected clock signal and input signal to be measured, and is believed with selected clock Number input signal to be measured is counted as counting clock, to obtain the thick time result of input signal to be measured.

Exemplarily, sampling unit is additionally operable to receive calibration signal, using calibration signal to multiple unordered clock signals Sampled, and exported corresponding calibration sampled result；Time-to-digit converter also includes：Sequential cell, with sampling unit and Decoding unit is connected, for receiving calibration sampled result, according to calibration sampled result determine multiple unordered clock signals when Sequence, and decoding unit is arrived into the timing information output related to the sequential of multiple unordered clock signals.

Exemplarily, time-to-digit converter also includes：Clock Managing Unit, for generating calibration signal.

Exemplarily, time-to-digit converter also includes：Selector, is connected with Clock Managing Unit and sampling unit, uses In reception input signal to be measured and the calibration signal of Clock Managing Unit output, and select input signal to be measured and calibration signal One of be input to sampling unit.

Exemplarily, unordered signal generation unit includes：Clock Managing Unit, for using phaselocked loop generation at least one Initial clock signal；And delay unit, it is connected with Clock Managing Unit, for prolonging at least one initial clock signal When, at least one initial clock signal is converted into multiple unordered clock signals.

Exemplarily, delay unit includes at least one in following item：At least one adder set, multiple gates Circuit and a plurality of delay line.

Exemplarily, at least one adder set is used to receive at least one initial clock signal correspondingly, its In, each adder set is used to constitute an addition carry chain, and the initial clock signal that will be received is used as corresponding addition The defeated of predetermined number is selected in the lowest order input signal of carry chain, and the output signal exported from corresponding addition carry chain Go out signal to be exported to sampling unit as at least a portion of multiple unordered clock signals.

Exemplarily, delay unit also includes：In certain number of look-up table unit, with least one adder set Certain number of adder set is connected correspondingly；Wherein, at least one adder set is via certain number of lookup Table unit exports to sampling unit the certain number of unordered clock signal in multiple unordered clock signals, and by residue Unordered clock signal be directly output to sampling unit.

Exemplarily, each logic gates in multiple logic gates is used to receive at least one initial clock signal One of, and initial clock signal to being received enters line delay, wherein, at least part of gate electricity in multiple logic gates The delay time on road is different from each other, wherein, logic gates and the sampling unit of the predetermined number in multiple logic gates connect Connect, the logic gates of predetermined number is used for the clock signal after the time delay of predetermined number as multiple unordered clock signals Export to sampling unit.

Exemplarily, the number of at least one initial clock signal is more than 1, and a plurality of delay line is used near correspondingly A few initial clock signal is transferred to sampling unit from Clock Managing Unit, wherein, at least partly prolonging in a plurality of delay line When line delay time it is different from each other.

Exemplarily, the number of at least one initial clock signal is more than 1, the cycle phase of at least one initial clock signal Together, and the uniform phase of at least one initial clock signal is distributed in the range of 0 to 180 °.

Exemplarily, unordered signal generation unit includes：Clock Managing Unit, for multiple unordered using phaselocked loop generation Clock signal.

Exemplarily, sampling unit includes：Multiple registers, for receiving multiple unordered clock letters correspondingly Number, the multiple unordered clock signals of signal latch are enabled come to multiple unordered clocks as latch by using input signal to be measured Signal is sampled.

Exemplarily, time-to-digit converter also includes：Output unit, connects with decoding unit and thick time counting unit Connect, for exporting thick time result and thin time result.

According to a further aspect of the invention, there is provided a kind of Method Of Time Measurement, including：The multiple unordered clock signals of generation； Multiple unordered clock signals are sampled using input signal to be measured, to obtain actual samples result；According to actual samples Result and the timing information related to the sequential of multiple unordered clock signals determine the first certain edges thereof edge of input signal to be measured And the time difference between the first certain edges thereof edge of the selected clock signal in multiple unordered clock signals, to obtain input to be measured The thin time result of signal；And input signal to be measured is counted using selected clock signal as counting clock, to obtain Obtain the thick time result of input signal to be measured.

Exemplarily, according to actual samples result and the timing information related to the sequential of multiple unordered clock signals Determine the first certain edges thereof of input signal to be measured along with multiple unordered clock signals in selected clock signal it is first specific Before time difference between edge, Method Of Time Measurement also includes：Multiple unordered clock signals are carried out using calibration signal Sampling, to obtain calibration sampled result；And according to the sequential of the calibration multiple unordered clock signals of sampled result determination, to obtain Obtain the timing information related to the sequential of multiple unordered clock signals.

Exemplarily, calibration signal include the sampling period be equal to the integral multiple in the cycle of multiple unordered clock signals with it is pre- First sampled signal of interval sum of fixing time and sampling period unrelated with the cycle of the unordered clock signals of multiple second adopt Sample signal, calibration sampled result is sampled obtained the to multiple unordered clock signals using the first sampled signal One sampled result and multiple unordered clock signals are sampled the second obtained sampled result using the second sampled signal, The sequential for determining multiple unordered clock signals according to calibration sampled result includes：One of multiple unordered clock signals of selection are made On the basis of signal；Value according to reference signal in the first sampled result estimates the appearance position on the second certain edges thereof edge of reference signal Put, it is determined that being cycle initial position in the nearest sampling location occurred behind position on the second certain edges thereof edge, and determine with the cycle Original position is the reference cycle for starting point, the cycle that the duration the is equal to multiple unordered clock signals time period；Statistics The appearance ratio of every kind of value of reference signal in second sampled result, to determine the high level and/or low level of reference signal The shared time in the reference cycle；Value and benchmark letter according to reference signal in the first sampled result at cycle initial position Number high level and/or the low level shared time in the reference cycle determine the sequential of reference signal；For it is multiple unordered when Each clock signal in clock signal, in addition to reference signal, the clock signal is believed with benchmark in the second sampled result of statistics Number every kind of combination value appearance ratio；And according at least to the clock signal in the first sampled result and reference signal in week Every kind of appearance ratio for combining value of the clock signal and reference signal in the value of phase original position and the second sampled result Example, determines the sequential of the clock signal.

Exemplarily, for multiple unordered clock signals in, each clock signal in addition to reference signal, at least According in the clock signal in the first sampled result and value and the second sampled result of the reference signal at cycle initial position The appearance ratio of every kind of combination value of the clock signal and reference signal, determining the sequential of the clock signal includes：For many Any clock signal for treating sequencing in individual unordered clock signal, according to treated in the second sampled result the clock signal of sequencing with The appearance ratio-dependent of every kind of combination value of reference signal treats that the clock signal of sequencing combines value with the every kind of of reference signal The shared time in the reference cycle；If treating that the clock signal of sequencing includes four kinds of different groups from the combination value of reference signal Conjunction value and every kind of combination value shared time in the reference cycle are more than predetermined time interval, then according to the first sampled result In treat to treat the clock of sequencing in the clock signal of sequencing and value, the second sampled result of the reference signal at cycle initial position The combination value of signal and reference signal determines the sequential of the clock signal for treating sequencing；If treating the clock signal and benchmark of sequencing The combination value of signal includes four kinds of different combination values and the value of the reference signal for being included and in the second certain edges thereof Any one in consistent two kinds combination values of the level occurred after in the reference cycle the shared time less than or equal to predetermined Time interval, then select the first auxiliary signal from the clock signal of sequencing, according to the first auxiliary signal, treats the clock of sequencing The distributed wave situation of the clock signal of sequencing is treated in the combination value determination of signal and reference signal, and according to treating the clock of sequencing Treat the clock signal and reference signal of sequencing at cycle initial position in distributed wave situation, first sampled result of signal Treat that the clock signal of sequencing and the combination value of reference signal determine to treat the clock signal of sequencing in value, the second sampled result Sequential, wherein, the first auxiliary signal includes four kinds of different combination values, every kind of combination values from the combination value of reference signal In the reference cycle the shared time more than the first auxiliary signal in predetermined time interval and the first sampled result in cycle starting Value at position is consistent along the level of preceding appearance with the second certain edges thereof；If treating the clock signal and reference signal of sequencing Combination value includes three kinds of different combination values, wherein, the clock signal of sequencing is treated in three kinds of different combination values Specific value only occurs once, then the second auxiliary signal is selected from the clock signal of sequencing, and according to the second sampled result In the combination value of the second auxiliary signal and the clock signal for treating sequencing determine the sequential of the clock signal for treating sequencing, wherein, the The combination value of two auxiliary signals and reference signal include four kinds of different combination values and the second auxiliary signal with it is undetermined Treat that the specific value of the clock signal of sequencing occurs twice in the combination value of the clock signal of sequence.

Exemplarily, calibration signal include the sampling period be equal to the integral multiple in the cycle of multiple unordered clock signals with it is pre- First sampled signal of interval sum of fixing time and sampling period unrelated with the cycle of the unordered clock signals of multiple second adopt Sample signal, calibration sampled result is sampled obtained the to multiple unordered clock signals using the first sampled signal One sampled result and multiple unordered clock signals are sampled the second obtained sampled result using the second sampled signal, The sequential for determining multiple unordered clock signals according to calibration sampled result includes：One of multiple unordered clock signals of selection are made On the basis of signal；Following ordering operation is repeated untill the sequential of multiple unordered clock signals is determined：According to first The value of reference signal estimates the appearance position on the second certain edges thereof edge of reference signal in sampled result, it is determined that in the second certain edges thereof Edge occur position behind nearest sampling location be cycle initial position, and determine with cycle initial position as starting point, hold The time period that the continuous time is equal to the cycle of multiple unordered clock signals is the reference cycle；For in multiple unordered clock signals , the pre-conditioned clock signal for treating sequencing is met, according to treating that the clock signal of sequencing believes with benchmark in the second sampled result Number every kind of combination value appearance ratio-dependent treat the clock signal of sequencing combined with the every kind of of reference signal value reference The shared time in cycle, and according to treating the clock signal of sequencing with reference signal at cycle initial position in the first sampled result Value, the second sampled result in treat that the clock signal of sequencing and the combination value of reference signal determine to treat the clock signal of sequencing Sequential, wherein, it is pre-conditioned including treating that the clock signal of sequencing includes four kinds of different groups from the combination value of reference signal Conjunction value and every kind of combination value shared time in the reference cycle are more than preset time period, preset time period and the scheduled time Interval is related；One of clock signal of sequencing in the multiple unordered clock signals of selection is used as new reference signal；And The sequential of multiple unordered clock signals is corrected based on unified cycle initial position.

Time-to-digit converter and Method Of Time Measurement according to embodiments of the present invention, due to utilizing unordered clock signal To carry out the fine measurement of input signal to be measured, therefore larger BIN presence wide can be avoided so that time-to-digit converter There can be temporal resolution very high.Additionally, the hardware resource required for above-mentioned time-to-digit converter is few, production cost It is low.

A series of concept of simplification is introduced in the content of the invention, these concepts will enter one in specific embodiment part Step is described in detail.Present invention part be not meant to attempt the key feature for limiting technical scheme required for protection and Essential features, the protection domain for attempting to determine technical scheme required for protection is not meant that more.

Below in conjunction with accompanying drawing, advantages and features of the invention are described in detail.

Brief description of the drawings

Drawings below of the invention is in this as a part of the invention for understanding the present invention.Shown in the drawings of this hair Bright implementation method and its description, for explaining principle of the invention.In the accompanying drawings,

Fig. 1 shows the schematic block diagram of time-to-digit converter according to an embodiment of the invention；

Fig. 2 shows the schematic block diagram of time-to-digit converter in accordance with another embodiment of the present invention；

Fig. 3 shows the schematic block diagram of time-to-digit converter in accordance with another embodiment of the present invention；

Fig. 4 shows the structural representation of delay unit according to an embodiment of the invention and sampling unit；

Fig. 5 shows the exemplary timing chart of the unordered clock signal of multiple according to an embodiment of the invention；

Fig. 6 show it is according to an embodiment of the invention, multiple unordered clock signals are entered using the first sampled signal The schematic diagram of the obtained sampled result of row sampling；

Fig. 7 shows two kinds of distributed wave situations of the different clock signal of value at cycle initial position；

Fig. 8 shows that distribution situation according to an embodiment of the invention is the clock signal for treating sequencing of generic homogeneous distribution Schematic diagram；

Fig. 9 shows showing for the clock signal for treating sequencing that distribution situation according to an embodiment of the invention is special distribution It is intended to；

Figure 10 a and 10b are shown respectively two kinds of special distributions of the clock signal for treating sequencing according to embodiments of the present invention Schematic diagram；

Figure 11 shows the clock signal for treating sequencing that distribution situation according to an embodiment of the invention is integrated distribution Schematic diagram；

Figure 12 shows that the time resolution for time-to-digit converter according to an embodiment of the invention is surveyed The obtained Gaussian Profile result of examination；And

Figure 13 shows the indicative flowchart of Method Of Time Measurement according to an embodiment of the invention.

Specific embodiment

In the following description, there is provided substantial amounts of details is so as to thoroughly understand the present invention.However, this area skill Art personnel will be seen that, described below to only relate to presently preferred embodiments of the present invention, and the present invention can be without one or more so Details and be carried out.Additionally, in order to avoid obscuring with the present invention, for some technical characteristics well known in the art not It is described.

In order to solve the above problems, the present invention proposes a kind of time-to-digit converter and Method Of Time Measurement, and it passes through nothing The clock signal of sequence measures the thin temporal information of input signal to be measured.In time-to-digit converter according to embodiments of the present invention In Method Of Time Measurement, the phase without ensureing clock signal is orderly, it is possible to achieve the time finer than prior art surveys Amount.

Input signal to be measured as herein described can be any required electric signal for measuring its temporal information.For example, to be measured Input signal can be the electric signal that is exported of reading circuit of PET system.When the front end photon detector of PET system is detected During gamma photons, a pulse signal can be exported, the pulse signal is commonly referred to HIT.Input signal to be measured can be described Pulse signal.

Fig. 1 shows the schematic block diagram of time-to-digit converter according to an embodiment of the invention 100.As shown in figure 1, Time-to-digit converter 100 includes unordered signal generation unit 110, sampling unit 120, decoding unit 130 and thick time counting Unit 140.

Unordered signal generation unit 110 is used to generate multiple unordered clock signals.Unordered signal generation unit 110 is generated Multiple clock signal periods it is identical, but phase and dutycycle are incomplete same.The plurality of clock signal be it is unordered, they Rising edge or trailing edge (or saying high level region or low level region) be not distributed in an orderly manner, regularly, but dispersion Ground, be distributed in irregularities in the whole clock cycle (cycle of i.e. unordered clock signal).

Sampling unit 120 is connected with unordered signal generation unit 110, for receiving multiple unordered clock signals and to be measured Multiple unordered clock signals are sampled, and export corresponding actual samples knot by input signal using input signal to be measured Really.

Exemplarily, it is possible to use input signal to be measured is entered as enable signal is latched to multiple unordered clock signals Row is latched.When the edge (such as rising edge) of input signal to be measured is reached, multiple unordered clock signals are latched.Obtaining In the case of knowing the sequential of multiple unordered clock signals, multiple unordered clock signals are entered according to using input signal to be measured The obtained sampled result of row sampling can calculate the certain edges thereof of input signal to be measured along the clock signals unordered with multiple Time difference of the certain edges thereof between, you can to obtain the thin temporal information of input signal to be measured.

Decoding unit 130 is connected with sampling unit 120, for receiving actual samples result, and according to actual samples result And the timing information related to the sequential of multiple unordered clock signals determines the certain edges thereof edge of input signal to be measured and multiple nothings Time difference of the certain edges thereof of the selected clock signal in the clock signal of sequence between, to obtain the thin time of input signal to be measured As a result.

Exemplarily, time-to-digit converter 100 can also include single memory cell, believe with multiple unordered clocks Number the related timing information of sequential can store in the memory cell.Exemplarily, can include inside decoding unit 130 Memory cell, the timing information related to the sequential of multiple unordered clock signals can store the storage in decoding unit 130 In unit.Exemplarily, the timing information related to the sequential of multiple unordered clock signals can also be stored in following article institute In the sequential cell stated.After the sequential of the multiple unordered clock signals of sequential cell determination, sequencing look-up table can be set up, and The timing information related to the sequential of multiple unordered clock signals is stored in sequencing look-up table.

The selected clock signal can be any clock signal in multiple unordered clock signals, and it can arbitrarily be selected Select, the present invention is limited not to this.A clock signal can be arbitrarily selected from multiple unordered clock signals as thick Clock signal used by time counting, decoding unit 130 can only determine the certain edges thereof of input signal to be measured along with it is selected Time difference of the certain edges thereof of clock signal between.Certainly, decoding unit 130 can also determine the certain edges thereof of input signal to be measured Time difference of the certain edges thereof of edge and all unordered clock signals between.Above-mentioned certain edges thereof edge can be rising edge or decline Edge, the present invention is limited not to this.

Thick time counting unit 140 is connected with unordered signal generation unit 110, for receiving selected clock signal and to be measured Input signal, and input signal to be measured is counted using selected clock signal as counting clock, to obtain input to be measured The thick time result of signal.

The working method of thick time counting unit 140 is consistent with the thick time counting mode in routine techniques.Exemplarily, Thick time counting unit 140 can be counted using direct counting method to input signal to be measured.

Can be seen from the foregoing, thick time result is the input signal to be measured that acquisition is calculated using such as direct counting method High level lasting time preliminary measurement results.The preliminary measurement results continue with the actual high level of input signal to be measured There is certain error between time.Fine measurement is primarily to measure above-mentioned error much.Therefore, input signal to be measured Temporal information can include thick time result and the aspect of thin time result two.The thick time result and thin time result for being obtained can For transmission to being further processed in the processing unit in time-to-digit converter, it is also possible to which output to external equipment is with by outer Portion's equipment is further processed.

In the prior art, thick time measurement is that input signal to be measured is counted using counting clock, and the thin time surveys Amount is multiple time delayed signals of input signal to be measured to be latched using same counting clock determine input signal to be measured Edge and the edge (such as the rising edge of input signal to be measured and the rising edge of the counting clock) of the counting clock between Time difference.And it is according to embodiments of the present invention, fine measurement is that multiple unordered clock signals are entered using input signal to be measured Row sampling, to determine the edge of input signal to be measured and edge (such as rising edge of input signal to be measured of selected clock signal With the rising edge of selected clock signal) between time difference.Thick time measurement is to input letter to be measured using selected clock signal Number counted.It can be seen that, the time measurement mode of above-mentioned time-to-digit converter 100 and time measurement mode of the prior art It is different, the difference of especially fine measurement is very big.

Time-to-digit converter according to embodiments of the present invention, due to for carrying out the fine measurement of input signal to be measured Clock signal be unordered clock signal, its rising edge or trailing edge (or saying high level region or low level region) can appoint Meaning ground, dispersedly it is distributed in the whole clock cycle, therefore larger BIN presence wide can be avoided so that time figure is changed Device can have temporal resolution very high.Additionally, the placement-and-routing of circuit, response speed of device etc. can all prolong to signal When produce influence, therefore keep signal it is unordered than keep signal in order be easier realize.Due to the phase of clock signal need not be kept In order, therefore hardware resource required for above-mentioned time-to-digit converter is few, low production cost for position.

According to embodiments of the present invention, time-to-digit converter can also include output unit.Fig. 2 is shown according to of the invention another The schematic block diagram of the time-to-digit converter 200 of one embodiment.It should be understood that the time-to-digit converter 200 shown in Fig. 2 is only Limitation is exemplary rather than, the invention is not limited in the circuit structure shown in Fig. 2.

Unordered signal generation unit 210, sampling unit 220, decoding unit 230 and thick time counting unit shown in Fig. 2 Unordered signal generation unit 110, sampling unit 120, decoding unit 130 and thick time counting unit 140 shown in 240 and Fig. 1 Structure it is consistent with operation principle, repeat no more.As shown in Fig. 2 time-to-digit converter 200 can also include output unit 250。

Output unit 250 is connected with decoding unit 230 and thick time counting unit 240, for export thick time result and Thin time result.

Exemplarily, output unit 250 can include that FIFO (First Input First Output, FIFO) is single Unit and universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, UART) unit.

Thick time result and thin time result can together be exported external equipment by output unit 250, such as mobile whole End, personal computer or server etc., to facilitate temporal information of the external equipment to receiving to be further processed.

According to embodiments of the present invention, time-to-digit converter can also include sequential cell.With continued reference to Fig. 2, time number Word converter 200 can also include sequential cell 260.

Sampling unit 120 can be also used for receiving calibration signal, and multiple unordered clock signals are entered using calibration signal Row sampling, and export corresponding calibration sampled result.Sequential cell 260 is connected with sampling unit 220 and decoding unit 230, uses In calibration sampled result is received, the sequential of multiple unordered clock signals is determined according to calibration sampled result, and will be with multiple nothings Decoding unit 230 is arrived in the related timing information output of the sequential of the clock signal of sequence.

In order to measure the thin temporal information of input signal to be measured, it is necessary to know the sequential of multiple unordered clock signals. In one example, can be determined using sequential cell 260 multiple unordered in 200 first task of time-to-digit converter The sequential (being properly termed as sequencing) of clock signal.When measuring the temporal information of input signal to be measured every time afterwards, it is possible to use deposit The timing information related to the sequential of multiple unordered clock signals for having stored up.In another example, can measure every time Before the temporal information of input signal to be measured, the sequential of multiple unordered clock signals is determined using sequential cell 260.

The process of the sequential of multiple unordered clock signals is determined using sequential cell 260 can be considered as calibration process. In calibration process, sampling unit 220 is sampled using calibration signal to multiple unordered clock signals.Sequential cell 260 connects Receive the sampled result of sampling unit 220 and the sequential of multiple unordered clock signals is determined according to the sampled result.In actual survey During amount, sampling unit 220 is sampled using input signal to be measured to multiple unordered clock signals.Decoding unit 230 The sampled result of sampling unit 220 is received, and according to the sequential of the sampled result clock signal unordered with fixed multiple To determine the position at the edge of input signal to be measured, and it is possible thereby to determine the certain edges thereof of input signal to be measured along unordered with any Clock signal certain edges thereof along between time difference.

" sequencing " is just to determine the high level region and low level region of multiple unordered clock signals in a clock week Interim accurate location, or determine the standard of the rising edge and trailing edge of multiple unordered clock signals in a clock cycle True position.

Sequential cell 260 can set up sequencing look-up table (Look-Up-Table, LUT) to be used in decoding process. Following table 1 is exemplarily illustrated a kind of form of sequencing look-up table.As shown in table 1, can to record n unordered for sequencing look-up table Clock signal high level scope and low level scope.Certainly, the n high level scope and low level of unordered clock signal Scope is to start to calculate as time shaft starting point with a certain predetermined time.The predetermined time can be n unordered clock signal In a certain clock signal high level initial time.

The sequencing look-up table configuration of table 1.

In the case where sequencing look-up table is set up, " decoding " is exactly to be drawn to treat according to the sequencing look-up table of sequencer procedure generation Survey the accurate location of the rising edge and/or trailing edge of input signal in a clock cycle.For example, it is assumed that actual samples result It is " 10100011 ... 11000 " (n) to be decoded since lowest order, the 1st signal value is ' 0 ', it is assumed that searched according to sequencing The time range that table is obtained is I₁=(200,500), can similarly obtain the 2nd, corresponding to the 3rd to n-th signal value Time range, uses I respectively₂、I₃、……I_n-1、I_nRepresent, then the edge (rising edge or trailing edge) of input signal to be measured is in clock Position in cycle is carries out the result that intersection operation is obtained to above-mentioned each time range：I=I₁∩I₂∩I₃……∩ I_n-1∩I_n.It is alternatively possible to the midrange for taking I is in place as edge (the rising edge or trailing edge) institute of the input signal to be measured The final result put.

If it is appreciated that being that its high level initial time is looked into as sequencing for the selected clock signal of thick time measurement Look for the clock signal of the time shaft starting point of table, then calculate through the above way acquisition input signal to be measured certain edges thereof along (on Rise along or trailing edge) position in the clock cycle is the thin time result of input signal to be measured.If surveyed for the thick time The selected clock signal of amount is not clock signal of its high level initial time as the time shaft starting point of sequencing look-up table, then root Position of the edge of selected clock signal in the clock cycle can be determined according to sequencing look-up table, with reference to the to be measured defeated of calculating acquisition Entering position of the edge of signal in the clock cycle can equally determine that the certain edges thereof of input signal to be measured is believed along with selected clock Number time difference of the certain edges thereof between, you can obtain the thin time result of input signal to be measured.

According to embodiments of the present invention, unordered signal generation unit 110 (or 210) can include Clock Managing Unit and time delay Unit.Fig. 3 shows the schematic block diagram of time-to-digit converter in accordance with another embodiment of the present invention 300.Adopting shown in Fig. 3 Sample unit 320, decoding unit 330, thick time counting unit 340, output unit 350 and sequential cell 360 and adopting shown in Fig. 2 Structure and the work of sample unit 220, decoding unit 230, thick time counting unit 240, output unit 250 and sequential cell 260 Principle is consistent, repeats no more.The unordered signal generation unit of the time-to-digit converter 300 shown in Fig. 3 includes Clock management list Unit 312 and delay unit 314.

Clock Managing Unit 312 is used to generate at least one initial clock signal using phaselocked loop.Delay unit 314 and when Clock administrative unit 312 is connected, for entering line delay at least one initial clock signal, by least one initial clock signal Be converted to multiple unordered clock signals.

Clock Managing Unit 312 can utilize FPGA inside Clock management module (Digit Clock Manager, DCM) realize.The inside of Clock Managing Unit 312 includes phaselocked loop (Phase Locked Loop, PLL), and phaselocked loop can basis Need to produce the clock signal with various cycles (or saying frequency) and phase.

Delay unit 314 can be the various devices that can suitably enter line delay to clock signal.Exemplary rather than limit Property ground processed, delay unit 314 can make initial clock signal by modes such as buffer time delay, logic gate delay or circuit delay There is time delay inside delay unit 314.Delay unit 314 can also include adder, and the addition being made up of adder enters Position chain enters line delay to initial clock signal.

Delay unit 314 can be carried out not when line delay is entered to initial clock signal to different initial clock signals The time delay of same amount, (or high level region or low level area are said with the rising edge or trailing edge that make the clock signal after time delay as far as possible Domain) dispersedly it is distributed in the whole clock cycle.The phase of the clock signal that delay unit 314 is exported need not ensure certain Sequentially, therefore for the hardware and software design of delay unit 314 require all than relatively low.

Each initial clock signal can produce any number of unordered clock signal with time delay, of the invention to be carried out not to this Limitation.

Required unordered clock signal can be more easily generated using delay unit 314.

According to embodiments of the present invention, delay unit 314 can be including at least one in following item：At least one adder Set, multiple logic gates and a plurality of delay line.It is exemplary and without limitation, can be using adder, gate or prolonging When line etc. line delay is entered to initial clock signal.

According to embodiments of the present invention, at least one adder set is used to receive at least one initial clock correspondingly Signal, wherein, each adder set is used to constitute an addition carry chain, and the initial clock signal that will be received is used as correspondingly Addition carry chain lowest order input signal, and select predetermined number in the output signal exported from corresponding addition carry chain Purpose output signal is exported to sampling unit as at least a portion of multiple unordered clock signals.

Fig. 4 shows the structural representation of delay unit according to an embodiment of the invention and sampling unit.Shown in Fig. 4 Example in, the initial clock signal that Clock Managing Unit 312 is generated be 4 tunnels, i.e. clk1, clk2, clk3, clk4.Time delay The unordered clock signal that unit 314 is exported is 96 tunnels.As shown in figure 4, delay unit 314 includes 4 adder set.Often Individual adder set includes 40 adders, the addition carry chain of composition one 40.Sampling unit 320 includes 96 deposits Device.The structure of delay unit and sampling unit shown in Fig. 4 is only exemplary rather than limitation.For example, the addition in delay unit 314 The number of the adder in the number of device set, each adder set, the number of the clock signal of output to sampling unit 320 And the number of the corresponding register in sampling unit 320 can be any setting, it is not limited to showing shown in Fig. 4 Example.

Delay unit 314 can realize a kind of new temporal interpolation mode with sampling unit 320.As shown in figure 4, time delay list Unit 314 can produce the unordered synperiodic square-wave signal in 96 tunnels, and it can will be used for the clock for counting in thick time counting unit 340 Cycle is divided into 96*2 parts.96 registers are enabled in sampling unit 320 by input signal to be measured or calibration signal to come to square wave Signal is latched.

As shown in figure 4, four frequencies that clk1, clk2, clk3 and clk4 are PLL to be produced are 1GHz, phase is respectively 0 °, 45 °, 90 ° and 135 ° of initial clock signal, they are input into the addition carry chain of four 40 as lowest order addition respectively One input of device.Illustrated by taking clk1 as an example below.When clk1 is low level 0, the output of corresponding addition carry chain Sum0~Sum39 is 1；When clk1 saltus steps are high level 1, output Sum0~Sum39 will successively be changed into 0.Therefore, Sum0~ Sum39 is the square-wave signal that frequency is 1GHz.24 road signals can be chosen from Sum0~Sum39 and is incorporated into sampling unit In 320, latched (sample) by the register in sampling unit 320.In calibration phase, latch and enable signal signal It is calibration signal.In actual measuring phases, it is input signal to be measured to latch and enable signal signal.Clk2, clk3, clk4 are held Row same operation, you can obtain the clock signal and its sampled result of 96 same cycles, out of phase.

According to embodiments of the present invention, delay unit 314 can also include：Certain number of look-up table unit, with least one Certain number of adder set in individual adder set is connected correspondingly；Wherein, at least one adder set warp By certain number of look-up table unit by the certain number of unordered clock signal in multiple unordered clock signals export to Sampling unit 320, and remaining unordered clock signal is directly output to sampling unit 320.

When building time-to-digit converter in FPGA, autoplacement can be carried out using Quartus Prime compilers Wiring.Placement-and-routing can cause the transmission route of clock signal to have differences.It is defeated in the clock signal for exporting adder set During entering each register to sampling unit 320, some clock signals can be made to be posted via the input of look-up table (LUT) unit Storage.LUT units can further result in clock signal and time delay occurs.By different paths and different LUT units, clock The time delay situation of signal is also different.Between the input of addition carry chain output end to register, some clock signals are passed through The buffering of LUT units, some are then directly connected into register.The time delay that LUT units bring, adds the difference of path delay, The phase difference between each road clock signal can be widened.

According to embodiments of the present invention, each logic gates in multiple logic gates is initial for receiving at least one One of clock signal, and initial clock signal to being received enters line delay, wherein, it is at least part of in multiple logic gates The delay time of logic gates is different from each other, wherein, the logic gates of the predetermined number in multiple logic gates with adopt Sample unit 320 is connected, and the logic gates of predetermined number is used for the clock signal after the time delay of predetermined number as multiple nothings The clock signal of sequence is exported to sampling unit.

The adder in above-mentioned at least one adder set can be replaced using logic gates.Logic gates has Delay function, acts on similar with adder.Exemplarily, Clock Managing Unit 312 can generate the multiple with out of phase Initial clock signal, and it is separately input to Different Logic gate circuit.Exemplarily, Clock Managing Unit 312 can also give birth to Into an initial clock signal, and it is entered into Different Logic gate circuit.Exemplarily, it is pre- with what sampling unit 320 was connected Fixed number purpose logic gates can be some or all in multiple logic gates.

According to embodiments of the present invention, the number of at least one initial clock signal is more than 1, and a plurality of delay line is used for one a pair Answer ground that at least one initial clock signal is transferred into sampling unit 320 from Clock Managing Unit 312, wherein, a plurality of delay line In at least part of delay line delay time it is different from each other.

Line delay merely can be entered to initial clock signal using the different a plurality of delay line of delay time, it is many to obtain Individual unordered clock signal.For example, at least partly the length of delay line can be with different from each other, to cause its delay time each other not Together.

According to embodiments of the present invention, the number of at least one initial clock signal is more than 1, at least one initial clock signal Cycle phase it is same, and the uniform phase of at least one initial clock signal is distributed in the range of 0 to 180 °.

With reference to Fig. 4, initial clock signal has 4 tunnels, i.e. clk1, clk2, clk3, clk4.Clk1, clk2, clk3 and The phase of clk4 is respectively 0 °, 45 °, 90 ° and 135 °, is distributed in 0 to 180 ° this four uniform phases of initial clock signal In the range of.It is exemplary and without limitation, two phase intervals of adjacent initial clock signal for arranging in order etc. can be made In or be substantially equal to 180 °/n, n is the number of initial clock signal, the phase of initial clock signal is tried one's best uniformly Ground distribution.There is the multichannel initial clock signal of phase difference by introducing, it is ensured that the final multiple unordered clock for obtaining The edge of signal is distributed more to disperse and uniform within a clock cycle, is not in BIN very big situations wide.

According to embodiments of the present invention, unordered signal generation unit 110 (or 210) can include Clock Managing Unit, be used for Using the multiple unordered clock signals of phaselocked loop generation.

Exemplarily, it is possible to use the PLL in FPGA directly generates multiple unordered clock signals.PLL can be according to need The clock signal of various cycles, phase is generated, therefore the multiple that cycle phase is same, phase is different can be directly generated using PLL Signal is used as required unordered clock signal.

It is appreciated that the mode of the multiple unordered clock signals of above-mentioned generation is only exemplary rather than limitation of the present invention, It is multiple unordered that those skilled in the art are contemplated that other are generated using suitable hardware and/or software by reading herein The mode of clock signal, it all should fall into protection scope of the present invention.

According to embodiments of the present invention, time-to-digit converter 100 (200,300) can also include：Clock Managing Unit, uses In generation calibration signal.

Exemplarily, calibration signal can include that the sampling period has certain pass with the cycle of multiple unordered clock signals The sampled signal of system and the sampling period sampled signal completely irrelevant with the cycle of multiple unordered clock signals.That is, Calibration signal can also be the clock signal with some cycles, therefore can be generated using Clock Managing Unit.For generating The Clock Managing Unit of calibration signal can with it is above-mentioned be same list for generating the Clock Managing Unit 312 of initial clock signal Unit.

Exemplarily, time-to-digit converter also includes selector.Referring back to Fig. 3, time-to-digit converter 300 may be used also With including selector 370.Selector 370 is connected with Clock Managing Unit 312 and sampling unit 320, for receiving input to be measured Signal and the calibration signal of the output of Clock Managing Unit 312, and select to be input to one of input signal to be measured and calibration signal Sampling unit 320.Selector 370 is controlled to be sampled which signal input to sampling unit 320 by control signal.Although Show that thick time counting unit 340 is connected with selector 370 in Fig. 3, input signal to be measured is input into the thick time via selector 370 Counting unit 340, but it is understood that, input signal to be measured can also directly input thick time counting unit 340.

According to embodiments of the present invention, sampling unit 120 (220,320) can include multiple registers, and multiple registers are used In multiple unordered clock signals are received correspondingly, by multiple as enable signal latch is latched using input signal to be measured Unordered clock signal is sampled come the clock signals unordered to multiple.

The structure and working principle of the register in sampling unit is described by reference to Fig. 4 above, be will not be repeated here. It should be noted that in the actually temporal information of measurement input signal to be measured, signal latch is enabled as latch using input signal to be measured Multiple unordered clock signals, and in a calibration process, it is necessary to unordered as enable signal latch multiple is latched using calibration signal Clock signal.

The sequencer procedure of above-mentioned sequential cell 260 (or 360) is described with reference to Fig. 5 to Figure 11.Below in relation to sequencing In the description of process, the example of the unordered clock signal in 96 tunnels shown in Fig. 4 is continued to use.

Fig. 5 shows the exemplary timing chart of the unordered clock signal of multiple according to an embodiment of the invention.In Fig. 5 In, line segment 510 and 520 represents the original position and end position of clock cycle T respectively, and line segment 530 represents certain once Sampling location.Fig. 5 is illustrated that the timing diagram of the unordered clock signal in 96 tunnels.Sampled when using calibration signal or input signal to be measured When, a sampled result can be obtained at the moment corresponding to line segment 530, as shown in Figure 5.

Two examples of the sequencer procedure of sequential cell 260 are described below.

First example

According to embodiments of the present invention, calibration signal can include that the sampling period is equal to the cycle of multiple unordered clock signals Integral multiple and predetermined time interval sum the first sampled signal and the cycle of sampling period and multiple unordered clock signals The second unrelated sampled signal, calibration sampled result can be entered using the first sampled signal to multiple unordered clock signals Row obtained the first sampled result of sampling and being sampled to multiple unordered clock signals using the second sampled signal is obtained The second sampled result, sequential cell 260 (or 360) can determine in the following manner multiple unordered clock signals when Sequence：One of multiple unordered clock signals of selection are used as reference signal；Value according to reference signal in the first sampled result is estimated The appearance position on the certain edges thereof edge of reference signal is counted, it is determined that being week in the nearest sampling location occurred behind position on certain edges thereof edge Phase original position, and determine that with cycle initial position as the starting point, duration is equal to the cycle of multiple unordered clock signals Time period be the reference cycle；The appearance ratio of every kind of value of reference signal in the second sampled result is counted, to determine benchmark The high level and/or low level of signal shared time in the reference cycle；According to reference signal in the first sampled result in the cycle The value of original position and the high level of reference signal and/or the low level shared time in the reference cycle determine reference signal Sequential；Each clock signal in for multiple unordered clock signals, in addition to reference signal, the sampling knot of statistics second The appearance ratio of every kind of combination value of the clock signal and reference signal in fruit；And in multiple unordered clock signals , each clock signal in addition to reference signal, exist according at least to the clock signal in the first sampled result and reference signal Every kind of appearance for combining value of the clock signal and reference signal in value and the second sampled result at cycle initial position Ratio, determines the sequential of the clock signal.

In order to realize sequencing, time-to-digit converter 100 (200,300) can implement following steps：Selection benchmark Signal, sampled using the first sampled signal, sampled using the second sampled signal, one by one signal carry out sequencing.Specifically It is described as follows：

(1) reference signal, is selected

It is exemplary and without limitation, when using adder realize delay unit 314 when, sequential cell 260 (or 360) can Using the selection clock signal corresponding with the lowest order output signal in addition carry chain from multiple unordered clock signals as Reference signal.After selected reference signal, can be believed as multiple unordered clocks using the high level original position of reference signal Number an original position for whole clock cycle, i.e. the position of t=0.The high level original position of reference signal can basis First sampled result determines that it will be described below.Follow-up sequencing step for convenience, reference signal preferably chooses duty Than the clock signal close to 50%.

(2), sampled using the first sampled signal

In one example, multiple unordered clock signals can be sampled using 49M clocks.49M clocks are frequencies Rate is the clock of 49MHz, and its clock cycle is 10⁶/49ps.49M clocks can be counted, and every by 490027 Sampled once during the clock cycle.Time interval (i.e. sampling period) between double sampling is fixed value, size is 490027 × 10⁶/49ps。

Continue to use above-mentioned example, it is assumed that unordered signal generation unit 110 (or 210) generates multiple nothings using the clock of 1GHz The clock signal of sequence, then the cycle of multiple unordered clock signals is 1000ps.The sampling period of the first sampled signal and multiple There is following relation between the cycle of unordered clock signal：

Understood with reference to formula (1), when being sampled to multiple unordered clock signals using the first sampled signal, the sampling period 10⁶× 490027/49ps be 10000551 times of the cycle 1000ps of unordered clock signal with 20.4ps sums, 20.4ps is It is predetermined time interval as herein described.Thus, it is supposed that 1st 10ps in cycle of the 1st sampling positioned at clock signal X Place, then the 2nd sampling will be located at the 10000552nd 30.4ps in cycle of clock signal X, and third time sampling will be located at At 2001103rd 50.8ps in cycle of clock signal X, the rest may be inferred.It should be appreciated that every 49 times continuous sampled results Can represent obtained sampled result of being sampled within the same complete 1000ps cycles, thus double sampling time Interval can be considered as 20.4ps.In a calibration process, a large amount of (such as number of times is more than 1000 times) sampling can be carried out, according to adopting Sample result estimates high level original position of the reference signal within a certain cycle.By adopting recently behind the high level original position Sample position is approximately cycle initial position, and selects 49 sampled results calculated since the cycle initial position as utilization First sampled signal is sampled obtained sampled result in a cycle of unordered clock signal.Further, it is also possible to Be equal to the time period in cycle of multiple unordered clock signals as reference using cycle initial position as the starting point, duration Cycle.

Fig. 6 show it is according to an embodiment of the invention, multiple unordered clock signals are entered using the first sampled signal The schematic diagram of the obtained sampled result of row sampling.In figure 6, two line segments more long represent the actual of reference cycle respectively The end cycle position of cycle initial position and reality, shorter line segment represents sampling location.

The sampling location that sampling sequence number as shown in Figure 6 is 1 can be approximately the cycle initial position in reference cycle, this It is the purpose sampled using the sampled signal with Fixed Time Interval.In fact, sampling sequence number is 1 sample bits Put closely actual cycle initial position, sampling sequence number is the 49 closely actual end cycle position in sampling location Put.Due to being approximation, so certain error can be caused, this be discussed below.It is multiple after determining cycle initial position Value of the unordered clock signal at cycle initial position is that can determine that.It should be noted that in Fig. 6 to Figure 11, being identified Cycle initial position is actual cycle initial position.

If it is understood that value of each road clock signal at cycle initial position determines that it is with reference to week Substantially distributed wave in phase is assured that, as shown in Figure 7.Fig. 7 shows two kinds of value differences at cycle initial position Clock signal distributed wave situation.If it is appreciated that value of certain clock signal at cycle initial position is low electricity Flat, then its distributed wave should be similar to the upper waveform shown in Fig. 7, i.e., in a reference cycle, the pars intermedia of clock signal It is divided into high level region, both sides are low level region.Equally, if value of certain clock signal at cycle initial position is height Level, then its distributed wave should be similar to the lower waveform shown in Fig. 7, i.e., in a reference cycle, the centre of clock signal Part is low level region, and both sides are high level region.

(3), sampled using the second sampled signal

In this step, it is possible to use statistic law sampling method, that is, utilize and (or said with cycle of multiple unordered clock signals Frequency) completely irrelevant clock largely sampled.As long as sampling number is enough, sampled signal can be believed in unordered clock Number a cycle in present be uniformly distributed.In order to realize statistic sampling, it is possible to use the second sampled signal is carried out largely (for example 5000 times) sampling.In one example, 9.992038M clocks (frequency is 9.992038MHz) can be used unordered to multiple Clock signal is sampled.With 49M clocks similarly, when carrying out statistic sampling using 9.992038M clocks, it is also possible to clock Cycle is counted, in the post-sampling by the clock cycle several times once.

It is analyzed by the second sampled result for obtaining, when can obtain in 96 tunnel clock signals two or more The appearance ratio of any combination value of clock signal, and then any combination value shared time in the reference cycle can be obtained. For example, if it is desired to which it is the time interval of " 11 " to obtain reference signal with the combination value of the 10th road signal, it is only necessary to counted Occur the number of times of reference signal=' 1 ' and the sampled result of the 10th road signal=' 1 ' in second sampled result, be designated as F11, then base The combination value " 11 " of calibration signal and the 10th road signal shared time t in the reference cycle can be expressed as following formula：

In formula (2), N is the number of all sampled results in the second sampled result, and T is multiple unordered clock signals Cycle.

(4), signal carries out sequencing one by one

Sequencing is carried out to reference signal first.As described above, it is determined that during cycle initial position, it is thus necessary to determine that benchmark is believed Number high level original position.Certainly, the low level original position of reference signal can also be considered as cycle initial position, in order to retouch State conveniently, be only described as an example with its high level original position herein.Exemplarily, can be from the first sampled result Find out and represent reference signal and be changed into value at two adjacent sample positions of high level, the two values difference from low level It is ' 0 ' and ' 1 '.Can determine the high level original position of reference signal between the two sampling locations.Then, can be by institute The value found out is considered as cycle initial position for ' 1 ' sampling location.Further, it is also possible to the cycle initial position is considered as into benchmark Position of the rising edge of signal in the reference cycle.

Then, the appearance ratio of every kind of value of reference signal in the second sampled result can be counted, to determine that benchmark is believed Number high level in the reference cycle the shared time.Value of the known reference at cycle initial position is ' 1 ' and base The high level of calibration signal shared time in the reference cycle, can easily determine the trailing edge of reference signal with reference to week Interim position.When it is determined that reference signal rising edge and trailing edge position when, the sequencing of reference signal is completed.

According to embodiments of the present invention, sequential cell 260 (or 360) is implemented for multiple unordered clocks in the following manner Each clock signal in signal, in addition to reference signal, according at least to the clock signal and benchmark in the first sampled result The clock signal combines value with the every kind of of reference signal in value and the second sampled result of the signal at cycle initial position Appearance ratio, the step of determine the sequential of the clock signal：Any in for multiple unordered clock signals treats sequencing Clock signal, the appearance ratio of the every kind of combination value according to the clock signal and reference signal that sequencing is treated in the second sampled result It is determined that treating that the clock signal of sequencing combines value shared time in the reference cycle with the every kind of of reference signal；If treating sequencing Clock signal includes four kinds of different combination values from the combination value of reference signal and every kind of combination value is in the reference cycle In the shared time be more than predetermined time interval, then according to treating the clock signal of sequencing with reference signal in week in the first sampled result Treat that the clock signal of sequencing and the combination value of reference signal determine in the value of phase original position, the second sampled result undetermined The sequential of the clock signal of sequence；If treating that the clock signal of sequencing includes four kinds of different combinations from the combination value of reference signal The value of value and the reference signal for the being included two kind combination values consistent with the level occurred after in the second certain edges thereof In any one in the reference cycle the shared time be less than or equal to predetermined time interval, then from the clock signal of sequencing select The first auxiliary signal is selected, according to the first auxiliary signal, to treat that the clock signal of sequencing and the combination value of reference signal determine undetermined The distributed wave situation of the clock signal of sequence, and distributed wave situation, the first sampled result according to the clock signal for treating sequencing In treat to treat the clock of sequencing in the clock signal of sequencing and value, the second sampled result of the reference signal at cycle initial position The combination value of signal and reference signal determines the sequential of the clock signal for treating sequencing, wherein, the first auxiliary signal is believed with benchmark Number combination value include four kinds of different combination values, every kind of combination values in the reference cycle the shared time more than pre- timing Between interval and the first sampled result in value of first auxiliary signal at cycle initial position with the second certain edges thereof along preceding The level of appearance is consistent；If treating that the clock signal of sequencing takes from the combination value of reference signal including three kinds of different combinations Value, wherein, treat that the specific value of the clock signal of sequencing only occurs once in three kinds of different combination values, then from sequencing Clock signal in select the second auxiliary signal, and according to the second auxiliary signal in the second sampled result and treat the clock letter of sequencing Number combination value determine the sequential of the clock signal for treating sequencing, wherein, the combination value of the second auxiliary signal and reference signal Sequencing is treated including four kinds of different combination values and in combination value of second auxiliary signal with the clock signal for treating sequencing Clock signal specific value occur twice.

When sequencing is carried out to other clock signals, can be according to their phase relations and reference signal between, by it Be divided three classes and carry out sequencing：Generic homogeneous distribution, special distribution and integrated distribution.

A (), generic homogeneous are distributed

Be uniformly distributed refer to the clock signal for treating sequencing rising edge and trailing edge be respectively distributed to reference signal height electricity Usually section and low level period.That is, distribution situation is the equally distributed clock signal for treating sequencing and reference signal Combination value includes four kinds of different combination values：" 11 ", " 10 ", " 01 " and " 00 ".Being uniformly distributed can be divided into generic homogeneous Two kinds of situations of distribution and special distribution.Generic homogeneous distribution refers to four kinds of combination values of the clock signal for treating sequencing with reference to week The interim shared time is all higher than predetermined time interval, and the predetermined time interval is 20.4ps in example mentioned above.

It should be appreciated that the clock signal for treating sequencing as herein described can include treating sequencing with the combination value of reference signal The value of clock signal preceding treating the clock signal of sequencing in rear and reference signal value in the value of preceding reference signal Value is in rear both of these case.That is, when the combination value of clock signal is described, each clock signal is not limited herein Value put in order, except particularly pointing out in this example.

Fig. 8 shows that distribution situation according to an embodiment of the invention is the clock signal for treating sequencing of generic homogeneous distribution Schematic diagram.As described above, it is determined that after cycle initial position, it may be determined that multiple unordered clock signals are from the cycle Value at beginning position.With reference to Fig. 8, treat that value of the clock signal of sequencing at cycle initial position is ' 0 '.

Furthermore, it is possible to treat that the clock signal of sequencing combines value with the various of reference signal in calculating the second sampled result Appearance ratio, that is, it is " 11 ", " 10 ", " 00 ", the appearance ratio of " 01 " these four situations to calculate combination value.According to every kind of combination The appearance ratio of value can determine the combination value in the reference cycle in shared time, i.e. Fig. 8 serial number 1,2,3,4 four Section time interval, calculation may be referred to formula (2).According to clock signal and reference signal that sequencing is treated in the first sampled result Value at cycle initial position can determine to treat the clock signal of sequencing and the substantially distributed wave of reference signal, with reference to " 11 ", " 10 ", " 00 ", " 01 " these four combination value shared times in the reference cycle, can easily try to achieve and treat sequencing Clock signal rising edge and position of the trailing edge in the reference cycle, complete corresponding sequencing look-up table.

(b), special distribution

Special distribution is the special circumstances in being uniformly distributed.Due to it is determined that during cycle initial position, will be in reference signal Certain edges thereof edge appearance position (such as high level original position mentioned above) behind nearest sampling location (such as Fig. 6 institutes The sampling sequence number for showing is 1 sampling location) it is approximately cycle initial position, and the sampling that will be obtained at the nearest sampling location Value of the result as each unordered clock signal at cycle initial position, it is thus possible to occur because clock signal is in reality Cycle initial position at value it is different from the value at the nearest sampling location caused by error.Fig. 9 shows basis The distribution situation of one embodiment of the invention is the schematic diagram of the clock signal for treating sequencing of special distribution.As shown in figure 9, undetermined Value of the clock signal of sequence at actual cycle initial position is ' 0 ', but it is at the sampling location that sampling sequence number is 1 Value is ' 1 '.Therefore, the sampling location that sampling sequence number is 1 being approximately into cycle initial position can cause the clock for treating sequencing to believe Number initial value misjudgment, in turn result in the whole distributed wave misjudgment of the clock signal for treating sequencing.

Waveform as shown in Figure 9 understands, in combination value " 11 " or " 10 " of reference signal and the clock signal for treating sequencing (value of reference signal preceding, after sequencing clock signal value after) less than or equal to predetermined time interval (for example In the case of 20.4ps), in fact it could happen that above-mentioned distributed wave misjudgment.Therefore, it can for such case to be referred to as special distribution Situation.In a word, if treat the clock signal of sequencing and the combination value of reference signal include four kinds of different combination values and Comprising reference signal value it is (as shown in Figure 9 with the level occurred afterwards along (rising edge as shown in Figure 9) in certain edges thereof High level) any one in consistent two kinds of combinations value (combination value " 11 " as shown in Figure 9 and " 10 ") be in the reference cycle In the shared time be less than or equal to predetermined time interval, it is determined that treat that the distributed wave of the clock signal of sequencing belongs to special point Cloth.

Although the characteristics of described above is special distribution, but the distributed wave for meeting These characteristics can not necessarily cause Distributed wave misjudgment.In fact, special distribution can be divided into two kinds of situations.Figure 10 a and 10b are shown respectively according to the present invention Two kinds of schematic diagrames of special distribution of the clock signal for treating sequencing of embodiment.

In Figure 10 a and Figure 10 b, the combination value " 10 " of reference signal and the clock signal for treating sequencing be (reference signal Value preceding, after sequencing clock signal value after) time interval be both less than predetermined time interval (such as 20.4ps), But only the distributed wave of Figure 10 a may cause distributed wave misjudgment due to approximate mistake.

In order to distinguish both of these case, the first auxiliary signal can be introduced, as as-shown-in figures 10 a and 10b.First auxiliary Signal has the characteristics that：Itself has completed sequencing；Reference signal combined with four kinds of the first auxiliary signal value " 11 ", " 10 ", " 01 " and " 00 " shared time in the reference cycle is both greater than predetermined time interval (such as 20.4ps)；First auxiliary letter Value (sampling sequence number as shown in Figure 6 is the sampled result at 1 sampling location) number at cycle initial position with spy Deckle is consistent along the level (low level as shown in Figure 9) occurred before (rising edge as shown in Figure 9).

Add after the first auxiliary signal, for reference signal, treat the clock signal of sequencing and the group of the first auxiliary signal For conjunction value, Figure 10 a have " 100 " appearance, and Figure 10 b have " 101 " to occur.It is possible thereby to complete two kinds of areas of special distribution Point.If treating that the distributed wave of the clock signal of sequencing belongs to that situation shown in Figure 10 a, can redefine and treat sequencing Value of the clock signal at cycle initial position, be for example originally ' 1 ' to be modified to ' 0 '.After then can be according to amendment Value of the clock signal for treating sequencing with value and the reference signal at cycle initial position at cycle initial position, the Treat that the sequential of the clock signal of sequencing is treated in the combination value determination of the clock signal and reference signal of sequencing in two sampled results.Such as Fruit treats that the distributed wave of the clock signal of sequencing belongs to that situation shown in Figure 10 b, then can use and be distributed with generic homogeneous The same mode determines to treat the sequential of the clock signal of sequencing.

(c), integrated distribution

Integrated distribution refers to when the high level that the rising edge and trailing edge of the clock signal of sequencing all fall in reference signal Section all fell in the low level period of reference signal.Figure 11 shows that distribution situation according to an embodiment of the invention is concentration point The schematic diagram of the clock signal for treating sequencing of cloth.

It can be seen from fig. 11 that reference signal and the combination value of the clock signal for treating sequencing only include three kinds it is different Combination value：" 10 ", " 11 ", " 00 " (value of reference signal preceding, after sequencing clock signal value after).This three In individual combination value, treat that the value ' 1 ' of the clock signal of sequencing is only occurred in that once.

It can be seen from fig. 11 that reference signal is divided into two with the combination value " 10 " of the clock signal for treating sequencing Part.In the case of not by auxiliary signal, this two sections of separate time intervals cannot be obtained.Therefore, it can introduce a tool There is the second auxiliary signal of following characteristics：Belong to and be uniformly distributed and itself has completed sequencing；Can by reference signal with treat The combination value " 11 " of the clock signal of sequencing is divided into two sections, i.e., t1 and t2 shown in Figure 11.When certain clock signal with it is undetermined Treat that the specific value (being ' 1 ' in the example shown in Figure 11) of the clock signal of sequencing occurs in the combination value of the clock signal of sequence When twice, it is believed that the combination value " 11 " of reference signal can be divided into two sections by the clock signal.For example shown in Figure 11 Example in, the second auxiliary signal (treats the clock of sequencing with the combination value of the clock signal for treating sequencing including " 10 " and " 11 " Preceding, the value of the second auxiliary signal is rear for the value of signal).

As can be seen from Figure 11, it is (auxiliary with combination value " 01 " and " 11 " of the clock signal for treating sequencing according to the second auxiliary signal The value of signal is helped preceding, after sequencing clock signal value after) the shared time in the reference cycle, it may be determined that t1 and The size of t2.Because the second auxiliary signal has completed sequencing, thus its leading edge position be it is known, can be by its rising edge Position is set to t0.Treat that the rising edge of the clock signal of sequencing is respectively with trailing edge position：T0-t1 and t0+t2.It is possible thereby to complete Into the sequencing of the clock signal for treating sequencing.

In a word, in signal sequencer procedure one by one, multiple unordered clock signals can be divided into three kinds of classifications and is determined Sequence.Due to being required for being uniformly distributed signal as auxiliary signal in the sequencer procedure of special distribution and integrated distribution signal, therefore If a clock signal includes four kinds of different combination value " 10 ", " 11 ", " 01 ", " 00 " from the combination value of reference signal And these four combination value shared times in the reference cycle are both greater than predetermined time interval (such as 20.4ps), then can be most Sequencing first is carried out to it, to be special distribution or integrated distribution signal provided auxiliary.

Second example

Exemplarily, calibration signal can include that the sampling period is equal to the integral multiple in the cycle of multiple unordered clock signals Unrelated with the cycle of multiple unordered clock signals with the first sampled signal of predetermined time interval sum and sampling period the Two sampled signals, calibration sampled result is sampled to multiple unordered clock signals using the first sampled signal and is obtained The first sampled result and multiple unordered clock signals are sampled the second obtained sampling using the second sampled signal As a result, sequential cell 260 (or 360) can in the following manner determine the sequential of multiple unordered clock signals：Selection is multiple One of unordered clock signal is used as reference signal；Following ordering operation is repeated until determining multiple unordered clock signals Sequential untill：Value according to reference signal in the first sampled result estimates the appearance position on the second certain edges thereof edge of reference signal Put, it is determined that being cycle initial position in the nearest sampling location occurred behind position on the second certain edges thereof edge, and determine with the cycle Original position is the reference cycle for starting point, the cycle that the duration the is equal to multiple unordered clock signals time period；For It is in multiple unordered clock signals, the pre-conditioned clock signal for treating sequencing is met, according to undetermined in the second sampled result The appearance ratio-dependent that the clock signal of sequence combines value with the every kind of of reference signal treats the clock signal and reference signal of sequencing Every kind of combination value in the reference cycle the shared time, and according to treating the clock signal and benchmark of sequencing in the first sampled result Signal treats the clock signal of sequencing and the combination value of reference signal in value, the second sampled result at cycle initial position It is determined that the sequential of the clock signal of sequencing is treated, wherein, the combination of the pre-conditioned clock signal including treating sequencing and reference signal Value includes four kinds of different combination values and every kind of combination value shared time in the reference cycle is more than preset time period, Preset time period is related to predetermined time interval；One of clock signal of sequencing in the multiple unordered clock signals of selection is made It is new reference signal；And the sequential of multiple unordered clock signals is corrected based on unified cycle initial position.

In this example, sequencer procedure can be made up of following steps：

1), selection all the way clock signal as reference signal.

2), the value according to reference signal in the first sampled result determines cycle initial position, and according to the first sampling knot Fruit obtains value of each road clock signal at cycle initial position.

3) reference signal, is obtained according to the second sampled result and combines value " 10 " with four kinds of the clock signal for treating sequencing Every kind of combination value in " 11 " " 01 " " 00 " shared time in the reference cycle, the four of serial number 1,2,3,4 as shown in Figure 8 Section time interval.If this four sections of time intervals are both greater than a certain preset time period, adopted according to the first sampled result and second Sample result, it is possible to it is determined that treating the sequential of the clock signal of sequencing.The sequential of the clock signal of sequencing is treated in determination in this step Mode with it is above-mentioned for distribution situation be generic homogeneous be distributed the clock signal for treating sequencing sequencer procedure it is similar, herein not Repeat again.Preset time period is related to predetermined time interval, and it can set as needed.For example, it is assumed that predetermined time interval It is 20.4ps, then preset time period can be twice of predetermined time interval or so, such as 45ps.

4) clock signal, is selected in the clock signal for completed sequencing as new reference signal, to continue To carrying out sequencing without the clock signal for completing sequencing.

5), repeat step 2), 3) and 4) until all of clock signal all completes sequencing.

6) the sequencing result for obtaining is processed based on unified cycle initial position,.Due in above-mentioned cyclic process In, reference signal changes, therefore the cycle initial position that is used of sequencing is probably different every time, it is therefore desirable to pair when The sequential of clock signal carries out unifying correction.It is appreciated that the reference signal used when each clock signal and itself sequencing it Between phase relation be fixed, the phase relation between its reference signal for being used and other reference signal is also Determine, so by the phase relation between clock signal, by timing corrections several times, all clocks may finally be believed Number sequential be adjusted to same period original position as starting point.

Compared with the method for sequencing in the first example, the method for sequencing in the second example is simpler and easy to implement.

Exemplarily, time-to-digit converter according to embodiments of the present invention can using any suitable hardware, software and/ Or firmware is realized.For example, time-to-digit converter can be realized using PFGA.

Exemplarily, the time resolution of built time-to-digit converter can in the following manner be tested.Example Such as, two time-to-digit converters of passage can be built, is sampled using same input signal to be measured.Due to input to be measured Signal reaches two path delay differences of time-to-digit converter, therefore two sampled results of time-to-digit converter are in solution The time value obtained after code should have fixed difference.In actual test, the difference is presented Gaussian Profile, the Gauss point The halfwidth (full width at half maximum, FWHM) of cloth is the temporal resolution of time-to-digit converter.Figure 12 show that the time resolution for time-to-digit converter according to an embodiment of the invention is tested what is obtained Gaussian Profile result.

It is 61.5ps or so by can be seen that FWHM values (i.e. time resolution) in Figure 12.The result with according to this hair The theoretical time certainty of measurement of the time-to-digit converter of bright embodiment also has certain gap, therefore continuation improvement is still present Space.

The complete job step of time-to-digit converter according to an embodiment of the invention is described below.

(1) after, system starts, sequencing is carried out first.

The sampling of time interval is fixed using 49M clocks, the unordered clock signal in 96 tunnels is approximately obtained at one Value at the cycle initial position in clock cycle.Then, carry out statistic law sampling using 9.992038M clocks, obtain 96 tunnels without The shared time interval within a clock cycle of any combinations value of the clock signal of sequence.By clock signal be divided three classes by Individual sequencing, and complete corresponding sequencing look-up table.

(2), time-to-digit converter enters working condition.

Input signal to be measured is input into thick time counting unit, thick time result is obtained.Input signal to be measured input is adopted Sample unit, latches the unordered clock signal in 96 tunnels.Latch result is decoded, thin time result is obtained.By thin time result After being combined with thick time result, exported to external equipment by output unit.

It is according to embodiments of the present invention compared to the current time-to-digit converter based on technologies such as " Wave union " Time-to-digit converter has advantages below：

(1)), temporal resolution is high, and can be adjusted flexibly.

Assuming that unordered signal generation unit generates the unordered clock signal in 96 tunnels, then the rising edge of these clock signals is with Along that can be 96*2=192 parts by a clock cycle T points, the clock cycle for using be 1000ps to drop.After tested, more than 95% BIN it is wide all in below 20ps, maximum BIN only 30ps or so wide, therefore time-to-digit converter possesses the time very high Resolution ratio.

Additionally, the temporal resolution of time-to-digit converter can be adjusted flexibly.For example, if necessary to the time higher point If resolution, the number of the clock signal that unordered signal generation unit is generated can be increased；Conversely, reducing generated clock The number of signal.It can be seen that, the mode of adjustment time resolution ratio is very convenient simple and direct.

(2), when time-to-digit converter is realized using FPGA, the FPGA internal resources for being consumed are less, at one Hundreds of passages can be realized inside fpga chip.

For example, can consuming, resource is more, design relative complex sequential cell and decoding unit is placed on FPGA and embeds The soft cores of NIOS II in perform.In this case, 10 logic array of resource average out to required for completing single channel TDC Block (Logic Array Block, LAB) left and right.If above-mentioned time-to-digit converter internally to be had thousands of available LAB FPGA in realize, then be capable of achieving more than 100 TDC of passage.

Although the resource for being consumed is less, the time resolution of time-to-digit converter according to embodiments of the present invention It is not low.From test link above, current time resolution has arrived at 60ps or so, and has larger carrying Rise space.

According to a further aspect of the invention, there is provided a kind of Method Of Time Measurement.Figure 13 is shown according to one embodiment of the invention Method Of Time Measurement 1300 indicative flowchart.As shown in figure 13, Method Of Time Measurement 1300 is comprised the following steps.

In step S1310, the multiple unordered clock signals of generation.

In step S1320, multiple unordered clock signals are sampled using input signal to be measured, actually to be adopted Sample result.

In step S1330, believed according to actual samples result and the sequential related to the sequential of multiple unordered clock signals Breath determines the first certain edges thereof of input signal to be measured along the first spy of the selected clock signal in the clock signals unordered with multiple Time difference of the deckle between, to obtain the thin time result of input signal to be measured.

In step S1340, input signal to be measured is counted using selected clock signal as counting clock, to obtain The thick time result of input signal to be measured.

According to embodiments of the present invention, before step S1330, Method Of Time Measurement 1300 can also include：Using calibration Signal is sampled to multiple unordered clock signals, to obtain calibration sampled result；And determined according to calibration sampled result The sequential of multiple unordered clock signals, to obtain the timing information related to the sequential of multiple unordered clock signals.

According to embodiments of the present invention, calibration signal includes that the sampling period is equal to the whole of the cycle of multiple unordered clock signals Several times are unrelated with the cycle of multiple unordered clock signals with the first sampled signal of predetermined time interval sum and sampling period The second sampled signal, calibration sampled result carries out sampling institute using the first sampled signal to multiple unordered clock signals The first sampled result for obtaining and multiple unordered clock signals are sampled obtained second using the second sampled signal Sampled result, the sequential for determining multiple unordered clock signals according to calibration sampled result includes：The multiple unordered clocks of selection One of signal is used as reference signal；Value according to reference signal in the first sampled result estimates the second certain edges thereof of reference signal The appearance position on edge, it is determined that be cycle initial position in the nearest sampling location occurred behind position on the second certain edges thereof edge, and It is determined that with cycle initial position as starting point, the duration be equal to multiple unordered clock signals cycle time period as reference Cycle；Count the appearance ratio of every kind of value of reference signal in the second sampled result, with determine reference signal high level and/ Or low level shared time in the reference cycle；According to value of the reference signal at cycle initial position in the first sampled result The shared time determines the sequential of reference signal in the reference cycle with the high level and/or low level of reference signal；For multiple Each clock signal in unordered clock signal, in addition to reference signal, the clock signal in the second sampled result of statistics With every kind of appearance ratio for combining value of reference signal；And for multiple unordered clock signals in, except reference signal Each clock signal in addition, according at least to the clock signal in the first sampled result and reference signal at cycle initial position Value and the second sampled result in the clock signal and reference signal every kind of combination value appearance ratio, determine the clock The sequential of signal.

According to embodiments of the present invention, for multiple unordered clock signals in, each clock in addition to reference signal Signal, value and second according at least to the clock signal in the first sampled result with reference signal at cycle initial position are adopted The appearance ratio of every kind of combination value of the clock signal and reference signal, determines the sequential bag of the clock signal in sample result Include：For any clock signal for treating sequencing in multiple unordered clock signals, sequencing is treated according in the second sampled result Clock signal treats that the clock signal of sequencing is every with reference signal with every kind of appearance ratio-dependent for combining value of reference signal Plant combination value shared time in the reference cycle；If treating that the clock signal of sequencing includes four with the combination value of reference signal Kind different combination values and every kind of combination value shared time in the reference cycle are more than predetermined time interval, then according to the Treat to be treated in value, the second sampled result of the clock signal of sequencing with reference signal at cycle initial position in one sampled result The clock signal of sequencing and the combination value of reference signal determine the sequential of the clock signal for treating sequencing；If treating the clock of sequencing The combination value of signal and reference signal include four kinds of different combination values and the value of the reference signal for being included and Any one in consistent two kinds combination values of the level that second certain edges thereof occurs after the shared time in the reference cycle is less than Or equal to predetermined time interval, then the first auxiliary signal is selected from the clock signal of sequencing, according to the first auxiliary signal, treat The clock signal of sequencing treats the distributed wave situation of the clock signal of sequencing with the combination value determination of reference signal, and according to treating Treat the clock signal and reference signal of sequencing from the cycle in distributed wave situation, first sampled result of the clock signal of sequencing Treat that the clock signal of sequencing and the combination value of reference signal determine to treat sequencing in value, the second sampled result at beginning position The sequential of clock signal, wherein, the combination value of the first auxiliary signal and reference signal includes four kinds of different combination values, every Kind of combination value in the reference cycle the shared time more than the first auxiliary signal in predetermined time interval and the first sampled result Value at cycle initial position is consistent along the level of preceding appearance with the second certain edges thereof；If treat the clock signal of sequencing with The combination value of reference signal includes three kinds of different combination values, wherein, treat sequencing in three kinds of different combination values The specific value of clock signal only occurs once, then the second auxiliary signal is selected from the clock signal of sequencing, and according to In two sampled results the combination value of the second auxiliary signal and the clock signal whne sequencing determine whne sequencing clock signal when Sequence, wherein, the second auxiliary signal includes four kinds of different combination values and in the second auxiliary from the combination value of reference signal Treat that the specific value of the clock signal of sequencing occurs twice in signal and the combination value of the clock signal for treating sequencing.

According to embodiments of the present invention, calibration signal includes that the sampling period is equal to the whole of the cycle of multiple unordered clock signals Several times are unrelated with the cycle of multiple unordered clock signals with the first sampled signal of predetermined time interval sum and sampling period The second sampled signal, calibration sampled result carries out sampling institute using the first sampled signal to multiple unordered clock signals The first sampled result for obtaining and multiple unordered clock signals are sampled obtained second using the second sampled signal Sampled result, the sequential for determining multiple unordered clock signals according to calibration sampled result includes：The multiple unordered clocks of selection One of signal is used as reference signal；Following ordering operation is repeated until the sequential for determining multiple unordered clock signals is Only：Value according to reference signal in the first sampled result estimates the appearance position on the second certain edges thereof edge of reference signal, it is determined that It is cycle initial position in the nearest sampling location occurred behind position on the second certain edges thereof edge, and determines with cycle initial position For starting point, the cycle that the duration the is equal to multiple unordered clock signals time period is the reference cycle；It is unordered for multiple Clock signal in, the pre-conditioned clock signal for treating sequencing is met, according to the clock that sequencing is treated in the second sampled result Signal and every kind of appearance ratio-dependent for combining value of reference signal treat every kind of group of the clock signal of sequencing and reference signal Conjunction value shared time in the reference cycle, and according to treating the clock signal of sequencing with reference signal in week in the first sampled result Treat that the clock signal of sequencing and the combination value of reference signal determine in the value of phase original position, the second sampled result undetermined The sequential of the clock signal of sequence, wherein, it is pre-conditioned including treating that the clock signal of sequencing includes with the combination value of reference signal Four kinds of different combination values and every kind of combination value shared time in the reference cycle are more than preset time period, Preset Time Section is related to predetermined time interval；One of clock signal of sequencing in the multiple unordered clock signals of selection is used as new base Calibration signal；And the sequential of multiple unordered clock signals is corrected based on unified cycle initial position.

Above combined accompanying drawing 1 to 12 describe the structure of each unit in time-to-digit converter, operation principle and Advantage, those skilled in the art are according to the description above with respect to time-to-digit converter and accompanying drawing 1 to 12, it is to be understood that herein Implementation method and its advantage of disclosed Method Of Time Measurement 1300 etc., for sake of simplicity, being repeated not to this herein.

It should be noted that above-described embodiment the present invention will be described rather than limiting the invention, and ability Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims, Any reference symbol being located between bracket should not be configured to limitations on claims.Word "comprising" is not excluded the presence of not Element listed in the claims or step.Word "a" or "an" before element is not excluded the presence of as multiple Element.The present invention can come real by means of the hardware for including some different elements and by means of properly programmed computer It is existing.If in the unit claim for listing equipment for drying, several in these devices can be by same hardware branch To embody.The use of word first, second, and third does not indicate that any order.These words can be explained and run after fame Claim.For example, " the first certain edges thereof edge " as herein described and " the second certain edges thereof edge " are only used for distinguishing two purposes at edge, " the One certain edges thereof edge " and " the second certain edges thereof edge " can be the edges (be for example rising edge or be trailing edge) of same type, Can also be different types of edge (such as one is rising edge, and one is trailing edge).

The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art Member is it is understood that the invention is not limited in above-described embodiment, teaching of the invention can also be made more kinds of Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Those of ordinary skill in the art are it is to be appreciated that the list of each example described with reference to the embodiments described herein Unit and algorithm steps, can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually Performed with hardware or software mode, depending on the application-specific and design constraint of technical scheme.Professional and technical personnel Described function, but this realization can be realized it is not considered that exceeding using distinct methods to each specific application The scope of the present invention.

In several embodiments provided herein, it should be understood that disclosed apparatus and method, can be by it Its mode is realized.For example, device embodiment described above is only schematical, for example, the division of the unit, only Only a kind of division of logic function, can there is other dividing mode when actually realizing, such as multiple units or component can be tied Another equipment is closed or is desirably integrated into, or some features can be ignored, or do not perform.

Claims (19)

1. a kind of time-to-digit converter, including：

Unordered signal generation unit, for generating multiple unordered clock signals；

Sampling unit, is connected with the unordered signal generation unit, for receiving the multiple unordered clock signal and to be measured Input signal, is sampled, and export corresponding reality using the input signal to be measured to the multiple unordered clock signal Border sampled result；

Decoding unit, is connected with the sampling unit, for receiving the actual samples result, and according to the actual samples knot Fruit and the timing information related to the sequential of the multiple unordered clock signal determine the certain edges thereof of the input signal to be measured Time difference of the certain edges thereof of the selected clock signal in edge and the multiple unordered clock signal between, to obtain described treating Survey the thin time result of input signal；And

Thick time counting unit, is connected with the unordered signal generation unit, for receiving the selected clock signal and described Input signal to be measured, and the input signal to be measured is counted using the selected clock signal as counting clock, with Obtain the thick time result of the input signal to be measured.

2. time-to-digit converter according to claim 1, it is characterised in that the sampling unit is additionally operable to receive calibration Signal, is sampled using the calibration signal to the multiple unordered clock signal, and exports corresponding calibration sampling knot Really；

The time-to-digit converter also includes：

Sequential cell, is connected with the sampling unit and the decoding unit, for receiving the calibration sampled result, according to institute State calibration sampled result and determine the sequential of the multiple unordered clock signal, and by with the multiple unordered clock signal The decoding unit is arrived in the related timing information output of sequential.

3. time-to-digit converter according to claim 2, it is characterised in that the time-to-digit converter also includes：

Clock Managing Unit, for generating the calibration signal.

4. time-to-digit converter according to claim 3, it is characterised in that the time-to-digit converter also includes：

Selector, is connected with the Clock Managing Unit and the sampling unit, for receiving the input signal to be measured and institute The calibration signal of Clock Managing Unit output is stated, and selects that one of the input signal to be measured and the calibration signal is defeated Enter to the sampling unit.

5. time-to-digit converter according to claim 1, it is characterised in that the unordered signal generation unit includes：

Clock Managing Unit, for generating at least one initial clock signal using phaselocked loop；And

Delay unit, is connected with the Clock Managing Unit, for entering line delay at least one initial clock signal, with At least one initial clock signal is converted into the multiple unordered clock signal.

6. time-to-digit converter according to claim 5, it is characterised in that the delay unit is included in following item At least one：At least one adder set, multiple logic gates and a plurality of delay line.

7. time-to-digit converter according to claim 6, it is characterised in that at least one adder set is used for At least one initial clock signal is received correspondingly, wherein, each adder set is used for one addition of composition and enters Position chain, the initial clock signal that will be received as corresponding addition carry chain lowest order input signal, and from corresponding plus The output signal of predetermined number is selected in the output signal that method carry chain is exported as the multiple unordered clock signal At least a portion is exported to the sampling unit.

8. time-to-digit converter according to claim 7, it is characterised in that the delay unit also includes：

Certain number of adder set in certain number of look-up table unit, with least one adder set is one by one It is correspondingly connected；

Wherein, when at least one adder set will be the multiple unordered via the certain number of look-up table unit Certain number of unordered clock signal in clock signal is exported to the sampling unit, and by remaining unordered clock signal It is directly output to the sampling unit.

9. time-to-digit converter according to claim 6, it is characterised in that each in the multiple logic gates Logic gates is used to receive one of described at least one initial clock signal, and initial clock signal to being received prolongs When, wherein, the delay time of at least part of logic gates in the multiple logic gates is different from each other,

Wherein, the logic gates of the predetermined number in the multiple logic gates is connected with the sampling unit, described pre- Fixed number purpose logic gates is used for the clock signal after the time delay of predetermined number as the multiple unordered clock signal Export to the sampling unit.

10. time-to-digit converter according to claim 6, it is characterised in that at least one initial clock signal Number be more than 1, a plurality of delay line be used for correspondingly by least one initial clock signal from the clock Administrative unit is transferred to the sampling unit, wherein, the delay time of at least part of delay line in a plurality of delay line that This is different.

11. time-to-digit converters according to claim 5, it is characterised in that at least one initial clock signal Number be more than 1, the cycle phase of at least one initial clock signal is same, and at least one initial clock signal Uniform phase is distributed in the range of 0 to 180 °.

12. time-to-digit converters according to claim 1, it is characterised in that the unordered signal generation unit includes：

Clock Managing Unit, for generating the multiple unordered clock signal using phaselocked loop.

13. time-to-digit converters according to claim 1, it is characterised in that the sampling unit includes：

Multiple registers, for receiving the multiple unordered clock signal correspondingly, by with the input letter to be measured Number enable the multiple unordered clock signal of signal latch the multiple unordered clock signal adopted as latching Sample.

14. time-to-digit converters according to claim 1, it is characterised in that the time-to-digit converter also includes：

Output unit, is connected with the decoding unit and the thick time counting unit, for export the thick time result and The thin time result.

A kind of 15. Method Of Time Measurements, including：

The multiple unordered clock signals of generation；

The multiple unordered clock signal is sampled using input signal to be measured, to obtain actual samples result；

Institute is determined according to the actual samples result and the timing information related to the sequential of the multiple unordered clock signal State the first certain edges thereof of input signal to be measured along with the multiple unordered clock signal in selected clock signal it is first special Time difference of the deckle between, to obtain the thin time result of the input signal to be measured；And

The input signal to be measured is counted using the selected clock signal as counting clock, it is described to be measured to obtain The thick time result of input signal.

16. Method Of Time Measurements according to claim 15, it is characterised in that described according to the actual samples result And the timing information related to the sequential of the multiple unordered clock signal determines the first specific of the input signal to be measured Before time difference of first certain edges thereof of the selected clock signal in edge and the multiple unordered clock signal between, institute Stating Method Of Time Measurement also includes：

The multiple unordered clock signal is sampled using calibration signal, to obtain calibration sampled result；And

The sequential of the multiple unordered clock signal is determined according to the calibration sampled result, it is unordered with the multiple to obtain Clock signal the related timing information of sequential.

17. Method Of Time Measurements according to claim 16, it is characterised in that the calibration signal is including the sampling period etc. The integral multiple in cycle and the first sampled signal of predetermined time interval sum and sampling in the multiple unordered clock signal Cycle second sampled signal unrelated with the cycle of the multiple unordered clock signal, the calibration sampled result using The first sampled result and utilize institute that first sampled signal is sampled obtained to the multiple unordered clock signal The second sampled signal is stated to sample the multiple unordered clock signal the second obtained sampled result,

It is described to determine that the sequential of the multiple unordered clock signal includes according to the calibration sampled result：

One of the multiple unordered clock signal is selected as reference signal；

The value of the reference signal according to first sampled result estimates the second certain edges thereof edge of the reference signal There is position, it is determined that be cycle initial position in the nearest sampling location occurred behind position on the second certain edges thereof edge, and It is determined that with the cycle initial position as starting point, the duration be equal to the multiple unordered clock signal cycle time Section is the reference cycle；

The appearance ratio of every kind of value of reference signal described in second sampled result is counted, to determine the reference signal High level and/or the low level shared time in the reference cycle；

Value and benchmark letter of the reference signal according to first sampled result at the cycle initial position Number high level and/or the low level shared time in the reference cycle determine the sequential of the reference signal；

Each clock signal in for the multiple unordered clock signal, in addition to the reference signal,

Count the appearance ratio of every kind of combination value of the clock signal and the reference signal in second sampled result；With And

According at least to the clock signal in first sampled result with the reference signal at the cycle initial position The appearance ratio of every kind of combination value of the clock signal and the reference signal in value and second sampled result, it is determined that The sequential of the clock signal.

18. Method Of Time Measurements according to claim 17, it is characterised in that described for the multiple unordered clock Each clock signal in signal, in addition to the reference signal, believes according at least to the clock in first sampled result The clock signal and institute in value and second sampled result number with the reference signal at the cycle initial position The appearance ratio of every kind of combination value of reference signal is stated, determining the sequential of the clock signal includes：

Any clock signal for treating sequencing in for the multiple unordered clock signal,

Treat that the clock signal of sequencing combines value with the every kind of of the reference signal according to second sampled result Occur being treated described in ratio-dependent that the clock signal of sequencing and the every kind of of the reference signal combine value in the reference cycle The shared time；

If the clock signal for treating sequencing includes four kinds of different combination values simultaneously from the combination value of the reference signal And every kind of combination value shared time in the reference cycle is more than the predetermined time interval, then according to the described first sampling Treat that value of the clock signal of sequencing with the reference signal at the cycle initial position, described second are adopted described in result Treat that the clock signal of sequencing and the combination value of the reference signal treat the clock signal of sequencing described in determining described in sample result Sequential；

If the clock signal for treating sequencing includes four kinds of different combination values simultaneously from the combination value of the reference signal And the two kind combinations consistent with the level occurred after in second certain edges thereof of the value of the reference signal for being included take Any one in the value shared time in the reference cycle is less than or equal to the predetermined time interval, then from sequencing when The first auxiliary signal is selected in clock signal, according to first auxiliary signal, the clock signal for treating sequencing and the benchmark The distributed wave situation of the clock signal of sequencing is treated described in the combination value determination of signal, and according to the clock letter for treating sequencing Number distributed wave situation, treat described in first sampled result clock signal of sequencing with the reference signal in the week The combination of the clock signal and the reference signal of sequencing is treated described in the value of phase original position, second sampled result Value determine described in treat sequencing clock signal sequential, wherein, the combination of first auxiliary signal and the reference signal Value includes that four kinds of different combination values, every kind of combination values shared time in the reference cycle are more than the pre- timing Between interval and first sampled result described in value of first auxiliary signal at the cycle initial position with institute The level that the second certain edges thereof is stated along preceding appearance is consistent；

If the clock signal for treating sequencing includes three kinds of different combination values from the combination value of the reference signal, its In, treat that the specific value of the clock signal of sequencing only occurs once described in described three kinds different combination values, then from The second auxiliary signal, and the second auxiliary signal and institute according to second sampled result are selected in the clock signal of sequencing The sequential of the clock signal of sequencing is treated described in the combination value determination for stating the clock signal for treating sequencing, wherein, second auxiliary Signal includes four kinds of different combination values and in second auxiliary signal and institute from the combination value of the reference signal Treat that the described specific value of the clock signal of sequencing occurs twice described in the combination value for stating the clock signal for treating sequencing.

19. Method Of Time Measurements according to claim 16, it is characterised in that the calibration signal is including the sampling period etc. The integral multiple in cycle and the first sampled signal of predetermined time interval sum and sampling in the multiple unordered clock signal Cycle second sampled signal unrelated with the cycle of the multiple unordered clock signal, the calibration sampled result using The first sampled result and utilize institute that first sampled signal is sampled obtained to the multiple unordered clock signal The second sampled signal is stated to sample the multiple unordered clock signal the second obtained sampled result,

It is described to determine that the sequential of the multiple unordered clock signal includes according to the calibration sampled result：

One of the multiple unordered clock signal is selected as reference signal；

Following ordering operation is repeated untill the sequential of the multiple unordered clock signal is determined：

The value of the reference signal according to first sampled result estimates the second certain edges thereof edge of the reference signal There is position, it is determined that be cycle initial position in the nearest sampling location occurred behind position on the second certain edges thereof edge, and It is determined that with the cycle initial position as starting point, the duration be equal to the multiple unordered clock signal cycle time Section is the reference cycle；

It is in for the multiple unordered clock signal, the pre-conditioned clock signal for treating sequencing is met, according to described Treat that the clock signal of sequencing combines the appearance ratio-dependent institute of value with the every kind of of the reference signal described in two sampled results State and treat that the clock signal of sequencing is combined value shared time in the reference cycle with the every kind of of the reference signal, and according to Treated described in first sampled result clock signal of sequencing with the reference signal taking at the cycle initial position Treat that the clock signal of sequencing and the combination value of the reference signal determine described in value, second sampled result described undetermined The sequential of the clock signal of sequence, wherein, it is described pre-conditioned including the clock signal for treating sequencing and the reference signal Combination value includes four kinds of different combination values and every kind of combination value shared time in the reference cycle is more than in advance If the time period, the preset time period is related to the predetermined time interval；

One of clock signal of sequencing in the multiple unordered clock signal is selected as new reference signal；And

The sequential of the multiple unordered clock signal is corrected based on unified cycle initial position.