CN107944073B - Ring oscillation integrated circuit for multi-channel time measurement - Google Patents
Ring oscillation integrated circuit for multi-channel time measurement Download PDFInfo
- Publication number
- CN107944073B CN107944073B CN201710948205.6A CN201710948205A CN107944073B CN 107944073 B CN107944073 B CN 107944073B CN 201710948205 A CN201710948205 A CN 201710948205A CN 107944073 B CN107944073 B CN 107944073B
- Authority
- CN
- China
- Prior art keywords
- ring oscillation
- delay
- sampling
- ring
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a ring oscillation integrated circuit for multi-channel time measurement, wherein ring oscillation units are arranged in two rows from top to bottom along the transverse direction of a layout coordinate system, delay circuits of the ring oscillation units in the upper row are positioned at the lowest part of the ring oscillation units and are sequentially connected in a cascade mode along the positive direction of a transverse shaft of the layout coordinate system, delay circuits of the ring oscillation units in the lower row are positioned at the top of the ring oscillation units and are sequentially connected in a cascade mode along the negative direction of the transverse shaft of the layout coordinate system, the delay circuits of all the ring oscillation units form a delay chain which is connected end to end, the signal delay time between every two adjacent ring oscillation unit delay circuits is equal, an externally input measured signal start is transmitted in the ring delay chain, and the ring oscillation units are driven by sampling control signals to parallelly acquire the state of the output ends of the ring oscillation unit delay circuits so as to realize multi-channel time measurement of the same signal. The ring oscillation circuit can improve the linearity of a measurement result, reduce measurement errors and improve the utilization rate of the area of a chip.
Description
Technical Field
The invention relates to a ring oscillation integrated circuit for multi-channel time measurement, which can be used in the layout design process of the integrated circuit in the field of high-resolution time measurement and belongs to the technical field of integrated circuit design.
Background
Time is a basic physical quantity and plays an extremely important role in space exploration, high-energy physics, remote sensing and remote measuring, flow and distance measurement and the like. The time measurement is a measure of the time period, i.e. the time interval between the start signal start and the end signal stop is to be measured. There are many methods for realizing high-precision time measurement by using electronic circuits, and a common method at present is a tapped delay line method.
The principle of the tapped delay line method is to pass a measured start signal through the delay line, detect the position to which it has passed during the measured time period by the tapped signal, and thereby obtain the result of the time measurement. The signal delay time between adjacent taps is the minimum resolution of the measurement. When implemented in a circuit, the delay line is typically constructed by a delay circuit, and the resolution of the measurement is the delay time of the cells. In an integrated circuit, the circuit elements commonly used are basic gates, such as inverters, nand gates, etc.
A basic tapped delay line time measurement circuit is shown in figure 1. Where the start signal start transmitted through the delay line is sampled at the tap with the stop signal stop, the position to which the start signal is transmitted through the measured period can be determined from the sampling results Q0-Qn (thermometer type coding), whereby the measured time interval can be calculated in combination with the delay time τ of each cell. The range of the tapped delay line method is determined by the length of the delay line (the number of delay circuits included). This structure forms the basis of many time measurement circuits, and different circuit forms can be formed by combining with other technologies.
In many cases, it is also necessary to measure the time intervals of multiple channels simultaneously during the measurement process, that is, the same start signal may correspond to different sources of stop signals, and these different stop signals constitute different channels. Since the sampling process is independent between different channels, it is necessary to provide independent sampling logic (sampling circuit) for different channels, and use different termination (sampling) signals, such as stop1, stop2, etc., to control the corresponding sampling circuits respectively. The tap delay sections may be shared in a multi-channel time measurement and do not have to change as the number of channels changes. These sampling circuits also form delay-sampling logic for each stage, along with delay circuits.
The range of the simple tapped delay line method is determined by the delay time of the delay circuit and the number of units, and in this way, a plurality of delay circuits are needed when the measurement with a larger range is realized, so that the hardware cost is larger. To achieve a large scale with less hardware resources, the delay line therein is typically constructed in the form of a ring oscillator (ring oscillator) when implemented.
In the implementation of integrated circuit design, for a simple tapped delay line type time measurement circuit, the layout can be arranged in sequence without excessive consideration. However, when the delay line is connected end to form a ring oscillator to reduce hardware overhead, the loop structure may damage the original linear structure due to the end-to-end processing of the loop structure, which may affect the accuracy and linearity of the measurement result.
If the ring oscillation is arranged according to a straight line type, and a signal is fed back to the position where the ring oscillation starts through the connecting line at the final end, the connecting lines connected end to end can generate large line delay, so that the linearity of a measurement result is influenced, particularly in a deep submicron integrated circuit process, the line delay accounts for a larger proportion than the gate delay, and the influence of the line delay on the design of the ring oscillation must be considered.
If the layout of the ring oscillation is also arranged in a ring shape during design, the linearity of the ring oscillation result can be better ensured, but a lot of chip area can not be utilized at the center and the outside of the ring, so that the chip area is wasted, and the implementation cost is increased.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, and the ring oscillation integrated circuit for multi-channel time measurement is provided to improve the linearity of the measurement result, reduce the measurement error and improve the chip area utilization rate.
The technical solution of the invention is as follows: a ring oscillation integrated circuit for multichannel time measurement comprises 2N-1 ring oscillation units, wherein N is an integer greater than 1, each ring oscillation unit comprises 1 delay circuit and M sampling circuits, the ring oscillation units are arranged in an upper row and a lower row along the transverse direction of a layout coordinate system, the two rows of ring oscillation units are arranged in a mirror-image overturning manner by a central axis parallel to the transverse axis direction, the delay circuits of the upper row of ring oscillation units are positioned at the lowest part of the ring oscillation units and are sequentially connected in a cascade manner along the positive direction of the transverse axis of the layout coordinate system; and the delay circuits of the next row of ring oscillation units are positioned at the top of the ring oscillation units and are sequentially connected in a cascade mode along the negative direction of the horizontal shaft of the layout coordinate system. The ring oscillation unit delay circuits at two end parts of the upper row and the lower row are connected through a rotary line, the delay circuits of 2N-1 ring oscillation units form a ring oscillator connected end to end, and the signal delay time between two adjacent ring oscillation unit delay circuits is equal. The external input measured signal start is transmitted in the annular delay chain, and M sampling circuits in each ring oscillation unit are driven by the external input mutually independent sampling control signals to parallelly acquire the state of the output end of the delay circuit of the ring oscillation unit, so that the multi-channel time measurement of the same signal is realized.
The delay circuit is realized by adopting two-input NAND gates, an externally input measured signal start is connected with one input end of the two-input NAND gate of any ring oscillation unit in the ring oscillation circuit and is used as a ring oscillation starting point, the other input end of the two-input NAND gate of the ring oscillation unit is connected with the output end of the two-input NAND gate of the preceding ring oscillation unit, one input end of the two-input NAND gate of the other ring oscillation unit is fixedly connected with a high level, and the other input end of the two-input NAND gate of the other ring oscillation unit is connected with the output end of the two-input.
The sampling circuit is realized by adopting a D trigger, and the D input end of the D trigger is used as the data input end of the sampling circuit and is connected with the output end of the delay circuit; the clock input end of the D trigger is connected with a sampling control signal, and the input signal of the D trigger is collected to the output end Q under the control of the sampling control signal and is used as the output of the sampling circuit.
The width of the 1 delay circuit and the width of the M sampling circuits in each ring oscillation unit are equal, the delay circuits and the M sampling circuits are aligned along the direction of the longitudinal axis of the layout coordinate system, and two adjacent sampling circuits are placed in the same direction.
The width of the 1 delay circuit and the width of the M sampling circuits in each ring oscillation unit are equal, the delay circuits and the M sampling circuits are aligned along the direction of the longitudinal axis of the layout coordinate system, and two adjacent sampling circuits are arranged in a mirror image mode by the central line parallel to the transverse axis of the coordinate system.
And the externally input sampling control signals are routed to the sampling control signal input ends of the corresponding sampling circuits of all the ring oscillation units in a balanced tree mode, so that the delay time from the externally input sampling control signals to the corresponding sampling circuit control signal input ends of the 2N-1 ring oscillation units is the same.
And the routing from the output end of the delay circuit of each ring oscillation unit to the data input ends of the M sampling circuits is carried out in a balanced tree mode, so that the routing delay from the output end of the delay circuit in each ring oscillation unit to the data input ends of the M sampling circuits is the same.
Compared with the prior art, the invention has the beneficial effects that:
(1) the upper row and the lower row of the ring oscillation unit are distributed in a mirror image mode in the longitudinal direction, the ring delay chains are concentrated in the center of the whole ring oscillation circuit layout, other interference does not exist among the delay chains, smaller and uniform signal delay time can be obtained, and time measurement accuracy is improved;
(2) the whole ring oscillation circuit layout adopts rectangular layout, so that the area of the ring oscillation design is as compact as possible on the premise of ensuring linearity and accuracy, and the layout and wiring in the whole design of a rear chip are facilitated.
(3) Two adjacent sampling circuits in the ring oscillation unit are arranged in a mode of up-down mirror image overturning in an axis parallel to the direction of the transverse axis during layout design, so that the area of a chip is saved, and the total length of wiring of a sampling signal can be reduced;
(4) each sampling control signal is wired in a balanced tree mode, so that the time of reaching each ring oscillation unit sampling control input signal point is the same, and the consistency of the measurement result of each ring oscillation unit and the linearity of final time measurement are ensured;
(5) the output of the delay circuit in the ring oscillation unit is routed to the input of the sampling circuit in a balanced tree mode, so that the time for the output of the delay signal of each ring oscillation unit to reach the input end of each sampling circuit is ensured to be the same, namely the consistency of the measurement results among channels.
Drawings
FIG. 1 is a basic tapped delay line method time measurement circuit structure;
FIG. 2 is a diagram illustrating an overall layout of a ring oscillator circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a single-channel ring unit according to an embodiment of the present invention;
FIG. 4(a) is a circuit diagram of a dual-channel ring unit according to an embodiment of the present invention (adjacent sampling units are not flipped over);
FIG. 4(b) is a circuit diagram of a dual-channel ring unit according to an embodiment of the present invention (adjacent sampling units are flipped over);
fig. 5(a) is a circuit diagram of a channel ring unit in embodiment 3 of the present invention (adjacent sampling units are not flipped);
fig. 5(b) is a circuit diagram of a channel ring unit (adjacent sampling units are turned over) in embodiment 3 of the present invention;
FIG. 6(a) is a control signal layout diagram (in the case of single drive) for sampling according to an embodiment of the present invention;
FIG. 6(b) is a diagram of a control signal distribution scheme (in the case of progressive driving) for sampling according to an embodiment of the present invention;
FIG. 7 is a complete layout (dual channels) of the ring unit according to the embodiment of the present invention;
FIG. 8 is a circular vibration complete layout (dual channels) according to the embodiment of the present invention;
fig. 9 is a post-simulation result of layout delay variation of the ring oscillator circuit according to the embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The layout design of the ring oscillation circuit needs to ensure the uniformity, consistency and accuracy of delay time and sampling time of each stage of units so as to reduce factors such as nonlinearity introduced by design and provide accurate and reliable measurement results as much as possible. This puts high demands on the design of the ring oscillator itself and the delay and sampling part. The reasonable design of the ring vibration layout plays an important role in improving the linearity of the measurement result, reducing the measurement error and improving the utilization rate of the chip area.
The invention provides a ring oscillation integrated circuit for multi-channel time measurement. The layout design of the ring oscillation adopts a rectangular layout. The ring oscillation unit is arranged in sequence in one direction, and the delay circuit and the sampling circuit are arranged in the ring oscillation unit in the other direction. For convenience, the ring unit is arranged in the horizontal axis direction of the layout coordinate system, and the internal circuits (delay and sampling circuits) of the ring unit are arranged in the vertical axis direction of the layout coordinate system. For the way of using the opposite arrangement, i.e. arranging the units in the vertical axis direction and arranging the internal circuits (delay and sampling circuits) of the units in the horizontal axis direction, the principles are completely consistent, and are not described again.
As shown in fig. 2. The ring oscillation circuit comprises 2N-1 ring oscillation units, wherein N is an integer larger than 1, each ring oscillation unit comprises 1 delay circuit and M sampling circuits, the ring oscillation units are arranged in two rows from top to bottom along the transverse direction of a layout coordinate system, one row comprises N, the other row comprises N-1, the ring oscillation units in the previous row and the ring oscillation units in the next row are arranged in a mode of mirror image turning from top to bottom along a central axis parallel to the transverse axis direction, the delay circuits of the ring oscillation units in the previous row are located at the bottommost part of the ring oscillation units and are sequentially connected in a cascade mode along the positive direction of the transverse axis of the coordinate system, the delay circuits of the ring oscillation units in the next row are located at the topmost part of the ring oscillation units and are sequentially connected in a cascade mode along the negative direction of the transverse axis of the coordinate system, as shown in FIG. 2, the signal transmission direction in the ring oscillation in the previous row. The delay circuits of the ring oscillation units at two end parts of the upper row and the lower row are connected through a rotary line, the delay circuits of 2N-1 ring oscillation units form a delay chain (ring oscillator) connected end to end, the signal delay time between two adjacent delay circuits of the ring oscillation units is equal, an externally input measured signal start is transmitted in the ring delay chain, each ring oscillation unit receives M externally input mutually independent sampling control signals (wherein M is more than or equal to 1), and the sampling circuits of the M ring oscillation units are driven by the externally input mutually independent sampling control signals to parallelly acquire the state of the output end of the delay circuit of the ring oscillation unit, so that multi-channel time measurement of the same signal is realized.
The ring oscillation circuit formed by the upper and lower rows of ring oscillation units forms a rectangular layout, the layout can make the design of the ring oscillation layout as compact as possible on the premise of ensuring the accuracy and linearity of the measurement result, and the layout and the wiring in the whole design of a chip at the back are convenient.
The delay circuit and the sampling circuit in each stage of ring oscillation unit adopt a design mode of longitudinal arrangement and transverse equal width, the delay circuit is arranged at a position close to the center of the ring oscillation layout, the ring oscillation units are distributed in the same direction or in a mirror image mode along the longitudinal direction, and the ring delay chain is concentrated at the center of the whole ring oscillation circuit. The delay units are not interfered by other lines, so that the wiring can be arranged on the same layer of the integrated circuit layout, the delay amount is reduced, and the time measurement precision is improved. The sampling circuits are arranged at the outer edge position close to the ring oscillation layout, the number of the sampling circuits for multi-channel measurement only affects the height of each stage unit, the position and the performance of the ring oscillation delay circuit are not affected, and the portability and the expansibility are strong.
The delay circuit is used to pass the signal in the ring oscillator, and its output is used to measure the elapsed time (i.e., the number of delay circuits elapsed) in the measured period of time. In order to control the start and stop of the ring oscillation, in this embodiment, the delay circuit is implemented by using a two-input nand gate, an externally input measured signal start is connected to one input end of the two-input nand gate of any ring oscillation unit in the ring oscillation circuit, and serves as a ring oscillation starting point, the other input end of the two-input nand gate of the ring oscillation unit is connected to the output end of the two-input nand gate of the preceding ring oscillation unit, one input end of the two-input nand gate of the other ring oscillation unit is fixedly connected to a high level, and the other input end of the two-input nand gate of the preceding ring oscillation unit is connected to the output. The output of the delay circuit in each stage of ring oscillation unit is simultaneously used for driving the delay circuit of the next stage and providing the output of the delay circuit of the current stage for recording the measurement result. The signal paths of the delay circuits are designed in such a way that the delay times are uniform. The delay circuits of each stage have the same structure, and the connecting wire loads are the same, so that the consistency of signal delay time is ensured. The signals between two adjacent ring oscillator unit delay circuits are controlled by the wiring layers and the geometric shapes of the signals, so that the delay time of the signals passing through the wiring is equal. In the design of the gyro line at both ends of the ring oscillator, signal connection needs to be completed through different layers of connection lines of the integrated circuit. The hierarchy and geometry used for these links determine the latency of this portion of the link. The wires are made as short and consistent as possible by adjusting the size of the wires during layout, so that the delay time of the part of the wires is consistent. The connection between the two rows of units (units of the non-ring-oscillating rotating part) is also adjusted according to the delay condition of the connection of the rotating part, so as to ensure that the delay time is consistent whether the connection is between the two rows of units or the connection of the rotating part. For example, the wiring of the slewing portion is completed by 3 pieces of metal wiring of M1 and M2 layers, respectively, and the total delay time constituted by adding vias and the like is t 1. The interconnection between the cells of the sequential arrangement is completed by M1 metal interconnection, and the delay time is t 2. When the two are different, assuming that t2< t1, the delay time of each stage time can be finally realized by lengthening the connection line corresponding to the smaller t2 so that t2 is t 1. The layout is the same when an inverter or other type of delay circuit is used.
The sampling circuit measures the position of the signal propagation at the end of the measured period of time (i.e., the measurement) by recording the state of the delay circuit output, which may be implemented with a D flip-flop or similar edge-triggered memory cell. As a preferred scheme, in this embodiment, the sampling circuit is implemented by using a D flip-flop, and a D input end of the D flip-flop is used as a data input end of the sampling circuit and is connected to an output end of the delay circuit; the clock input end of the D trigger is connected with a sampling control signal, and the input signal of the D trigger is collected to the output end Q under the control of the sampling control signal and is used as the output of the sampling circuit. The number of sampling circuits in the multi-channel measurement is determined according to the number of channels, for example, the single-channel measurement is 1 sampling circuit, the dual-channel measurement is 2 sampling circuits, the three-channel measurement is 3 sampling circuits, and so on.
In layout design, M sampling circuits in each ring oscillation unit are designed to be equal in width and aligned along the longitudinal axis direction of a layout coordinate system, and two adjacent sampling circuits can be placed in two ways, wherein one sampling circuit is placed in the same direction, and the other sampling circuit is placed in a mirror image overturning manner by a central line parallel to the transverse axis of the coordinate system. The circuit diagram of the dual-channel ring oscillator unit is shown in fig. 4. Fig. 4(a) shows a case where the sampling circuit is not inverted, and fig. 4(b) shows a case where the sampling circuit is inverted. The circuit diagram of the three-channel ring oscillator unit is shown in fig. 5. Similar to dual channels, adjacent sampling flip-flops may also be brought as close together as possible in a flipped manner along the horizontal axis. Fig. 5(a) shows a case where the sampling circuit is not inverted, and fig. 5(b) shows a case where the sampling circuit is inverted. The other multi-channel conditions are similar, and can be analogized, and the description is omitted. The layout of these delay circuits can be designed exactly as in the circuit diagram described above.
In order to ensure that the path delay of the delay signal from a source point (output of the delay circuit) to a destination point (data input end of the sampling circuit) is the same, the route from the output end of each ring oscillator unit delay circuit to the data input ends of the M sampling circuits is routed according to a balanced tree mode.
For a single channel, only one sampling circuit is needed, so that special design is not needed, and only the delay among all stages of ring oscillation units is kept consistent. The circuit diagram of the single-channel ring oscillator unit is shown in fig. 3.
For multi-channel sampling, the delay from the delay circuit output to each sampling circuit input is kept consistent inside each stage of unit, and the signal is wired by adopting a balanced tree method. For two-channel sampling, a balanced tree approach is utilized, as shown in fig. 4(a) and 4(b), respectively. As shown in fig. 4(a), when two D flip-flops are arranged in the same direction, the delay signal reaches the midpoint of the input ends of the two D flip-flops, and is divided into two branches to be sent to the input ends of the D flip-flops. As shown in fig. 4(b), when the sampling flip-flop is turned over along the horizontal axis, the two D flip-flops may be as close as possible, which may save chip area and also reduce the total length of the trace of the sampling signal. For three-channel sampling, the balanced tree method is also employed, as shown in fig. 5(a) and 5 (b).
In order to ensure that the delay time from the externally input sampling control signal to the corresponding circuit sampling control signal input end of each ring oscillation unit is the same, and thus the accuracy and consistency of the measurement result are ensured, the externally input sampling control signal is routed to the sampling control signal input end of the corresponding sampling circuit of each ring oscillation unit in a balanced tree manner.
The balance trees of the sampling control signals are arranged on the upper side and the lower side of the ring oscillation rectangular layout (namely the part of the ring oscillation unit close to the outer side), and the layout and the performance of the whole ring oscillation layout are not influenced while the balance is ensured. The equalizing layout mode of the sampling control signal is explained by taking a single channel as an example. As shown in FIG. 6, the sampling control signal is routed from the midpoint position of any longitudinal side edge of a rectangular region formed by 2N-1 ring oscillation units along the longitudinal positive and negative directions and reaches the transverse edge and exceeds the proper height required by the wiring, then the sampling control signal is turned 90 degrees and routed along the transverse direction of the rectangular region, after reaching the transverse midpoint of the ring oscillation rectangle, the turning 90 degrees is changed into the vertical routing for ring oscillation, then the routing is respectively routed to the central point of the next stage along the transverse direction of the rectangle according to the mode of a balance tree from the vertical routing, then the turning 90 degrees is changed into the vertical routing, the steps are circularly repeated and step-by-step decomposed until 2N-1 branches are obtained, and the 2N-1 branches are connected to the sampling control signal input ends of the sampling circuits corresponding to the 2N-1 ring oscillation units. In performing the sampled signal transfer, one large signal driver may be used, followed by a balanced tree routing of the sampled control signals, as shown in fig. 6 (a). Or, in the process of transmitting the sampling control signal, a driver is added to the branch as required, so that the signal driver is combined with the balanced tree, and the driving capability of the sampling control signal is improved, as shown in fig. 6 (b).
For the multi-channel case, the design approach is the same. The routing and drivers (if any) of the sampling control signals are arranged outside the ring oscillation unit (above and below the ring oscillation layout rectangle), so that the layout and layout of the ring oscillation are not influenced, and the balance of the sampling signals is ensured.
Fig. 7 shows a complete ring unit layout by taking a dual-channel ring unit as an example. The sampling circuit adopts a turnover mode, and the black part is an equalizing wiring of a delay signal. Fig. 8 shows an example of a complete layout of the two-channel ringing. In this example, a single drive is used. Wherein the black portion is the equalization wiring that samples the control signal. As can be seen from the figure, the layout design is compact, and no waste area exists. Design verification shows that the deviation between each stage of delay is within +/-1%, and the post-simulation result of the delay deviation of the ring oscillator layout is shown in an attached figure 9.
Parts of the specification which are not described in detail are within the common general knowledge of a person skilled in the art.
Claims (7)
1. A ring oscillator integrated circuit for multi-channel time measurement, comprising: the system comprises 2N-1 ring vibration units, wherein N is an integer larger than 1, each ring vibration unit comprises 1 delay circuit and M sampling circuits, the ring vibration units are arranged in two rows from top to bottom along the transverse direction of a layout coordinate system, the two rows of ring vibration units are arranged in a mirror-image overturning manner by a central axis parallel to the transverse axis direction, the delay circuits of the upper row of ring vibration units are positioned at the lowest part of the ring vibration units and are sequentially connected in a cascade manner along the positive direction of the transverse axis of the layout coordinate system; the delay circuits of the ring oscillation units in the next row are positioned at the top of the ring oscillation units and are sequentially connected in a cascade mode along the negative direction of a transverse shaft of a domain coordinate system, the delay circuits of the ring oscillation units at two end parts of the upper row and the lower row are connected through a rotary line, the delay circuits of the 2N-1 ring oscillation units form an annular oscillator which is connected end to end, the signal delay time between the delay circuits of the two adjacent ring oscillation units is equal, a measured signal start which is input from the outside is transmitted in an annular delay chain, and M sampling circuits in each ring oscillation unit are driven by mutually independent sampling control signals which are input from the outside to parallelly acquire the state of the output end of the delay circuit of the ring oscillation unit, so that multi-channel time measurement of the same signal is realized.
2. A ringing integrated circuit for multichannel time measurement as claimed in claim 1, characterized in that: the delay circuit is realized by adopting two-input NAND gates, an externally input measured signal start is connected with one input end of the two-input NAND gate of any ring oscillation unit in the ring oscillation circuit and is used as a ring oscillation starting point, the other input end of the two-input NAND gate of the ring oscillation unit is connected with the output end of the two-input NAND gate of the preceding ring oscillation unit, one input end of the two-input NAND gate of the other ring oscillation unit is fixedly connected with a high level, and the other input end of the two-input NAND gate of the other ring oscillation unit is connected with the output end of the two-input.
3. A ringing integrated circuit for multichannel time measurement as claimed in claim 1, characterized in that: the sampling circuit is realized by adopting a D trigger, and the D input end of the D trigger is used as the data input end of the sampling circuit and is connected with the output end of the delay circuit; the clock input end of the D trigger is connected with a sampling control signal, and the input signal of the D trigger is collected to the output end Q under the control of the sampling control signal and is used as the output of the sampling circuit.
4. A ringing integrated circuit for multichannel time measurement as claimed in claim 1, characterized in that: the width of the 1 delay circuit and the width of the M sampling circuits in each ring oscillation unit are equal, the delay circuits and the M sampling circuits are aligned along the direction of the longitudinal axis of the layout coordinate system, and two adjacent sampling circuits are placed in the same direction.
5. A ringing integrated circuit for multichannel time measurement as claimed in claim 1, characterized in that: the width of the 1 delay circuit and the width of the M sampling circuits in each ring oscillation unit are equal, the delay circuits and the M sampling circuits are aligned along the direction of the longitudinal axis of the layout coordinate system, and two adjacent sampling circuits are arranged in a mirror image mode by the central line parallel to the transverse axis of the coordinate system.
6. A ringing integrated circuit for multichannel time measurement as claimed in claim 1, characterized in that: and the externally input sampling control signals are routed to the sampling control signal input ends of the corresponding sampling circuits of all the ring oscillation units in a balanced tree mode, so that the delay time from the externally input sampling control signals to the corresponding sampling circuit control signal input ends of the 2N-1 ring oscillation units is the same.
7. A ringing integrated circuit for multichannel time measurement as claimed in claim 1, characterized in that: and the routing from the output end of the delay circuit of each ring oscillation unit to the data input ends of the M sampling circuits is carried out in a balanced tree mode, so that the routing delay from the output end of the delay circuit in each ring oscillation unit to the data input ends of the M sampling circuits is the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710948205.6A CN107944073B (en) | 2017-10-12 | 2017-10-12 | Ring oscillation integrated circuit for multi-channel time measurement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710948205.6A CN107944073B (en) | 2017-10-12 | 2017-10-12 | Ring oscillation integrated circuit for multi-channel time measurement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107944073A CN107944073A (en) | 2018-04-20 |
| CN107944073B true CN107944073B (en) | 2021-01-08 |
Family
ID=61935197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710948205.6A Active CN107944073B (en) | 2017-10-12 | 2017-10-12 | Ring oscillation integrated circuit for multi-channel time measurement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107944073B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10810344B1 (en) * | 2019-03-29 | 2020-10-20 | Hongchang Liang | Multi-instantiation time budgeting for integrated circuit design and manufacturing |
| CN111723539B (en) * | 2020-05-14 | 2024-03-22 | 天津大学 | Design method of double time-measurement mode TDC chip |
| CN111983423B (en) * | 2020-07-28 | 2023-08-29 | 成都华微电子科技股份有限公司 | Chip wiring delay built-in detection circuit and detection method |
| CN114896936B (en) * | 2022-02-16 | 2023-04-07 | 上海先楫半导体科技有限公司 | Ring oscillator and layout wiring structure thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101467067A (en) * | 2006-06-15 | 2009-06-24 | 皇家飞利浦电子股份有限公司 | Integrated multi-channel time-to-digital converter for time-of-flight PET |
| CN202166844U (en) * | 2011-06-23 | 2012-03-14 | 山东力创科技有限公司 | High precision time measurement circuit |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN103973303A (en) * | 2013-01-31 | 2014-08-06 | 富士通半导体股份有限公司 | Ring oscillator and semiconductor device |
| CN106200356A (en) * | 2016-09-23 | 2016-12-07 | 中国科学院上海高等研究院 | Vernier annular time-to-digit converter |
| CN106354001A (en) * | 2016-08-31 | 2017-01-25 | 中国科学院上海高等研究院 | Time-to-digital conversion circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6351058B2 (en) * | 2013-11-28 | 2018-07-04 | 株式会社メガチップス | Time digital converter and PLL circuit using the same |
-
2017
- 2017-10-12 CN CN201710948205.6A patent/CN107944073B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101467067A (en) * | 2006-06-15 | 2009-06-24 | 皇家飞利浦电子股份有限公司 | Integrated multi-channel time-to-digital converter for time-of-flight PET |
| CN202166844U (en) * | 2011-06-23 | 2012-03-14 | 山东力创科技有限公司 | High precision time measurement circuit |
| CN103973303A (en) * | 2013-01-31 | 2014-08-06 | 富士通半导体股份有限公司 | Ring oscillator and semiconductor device |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN106354001A (en) * | 2016-08-31 | 2017-01-25 | 中国科学院上海高等研究院 | Time-to-digital conversion circuit |
| CN106200356A (en) * | 2016-09-23 | 2016-12-07 | 中国科学院上海高等研究院 | Vernier annular time-to-digit converter |
Non-Patent Citations (2)
| Title |
|---|
| Harmonic Ring Oscillator Time-to-Digital Converter;Juan Pablo Caram，et al;《2015 IEEE International Symposium on Circuits and Systems》;20150730;正文第161-164页 * |
| 游标型时间数字转换器的研究与设计;田中一;《中国优秀硕士学位论文全文数据库 信息科技辑》;20140415;I135-135 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107944073A (en) | 2018-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107944073B (en) | Ring oscillation integrated circuit for multi-channel time measurement | |
| US5818797A (en) | Time measuring device | |
| WO2020114437A1 (en) | Fpga-based high-precision time measurement method | |
| EP0464632A2 (en) | Parallel data processing apparatus with signal skew compensation | |
| CN111983423B (en) | Chip wiring delay built-in detection circuit and detection method | |
| CN110069009A (en) | Multichannel time-to-digit converter and Electro-Optical Sensor Set | |
| US8307320B2 (en) | Method of placing delay units of pulse delay circuit on programmable logic device | |
| CN109891843A (en) | Clock recovery and data for programmable logic device restore | |
| US20150206559A1 (en) | Register file module and method therefor | |
| CN114253346A (en) | Timing signal generator and calibration system and method thereof | |
| CN111812490B (en) | Method for testing signal transmission delay in FPGA chip | |
| CN104298150A (en) | TDC achieving method and device based on logic resources special for FPGA | |
| CN113723046B (en) | Fishbone-shaped clock tree and implementation method | |
| US6862548B1 (en) | Methods and circuits for measuring clock skew on programmable logic devices | |
| US20230236999A1 (en) | Chip-to-chip interface of a multi-chip module (mcm) | |
| Brugge et al. | A Parameterizable NoC Router for FPGAs. | |
| Szplet et al. | Several issues on the use of independent coding lines for time-to-digital conversion | |
| US10114914B2 (en) | Layout effect characterization for integrated circuits | |
| US8901938B2 (en) | Delay line scheme with no exit tree | |
| Guo et al. | Multi-chain time interval measurement method utilizing the dedicated carry chain of FPGA | |
| US20020094057A1 (en) | Shift register | |
| US20090282279A1 (en) | Semiconductor integrated circuit and layout method thereof | |
| US6871335B1 (en) | Methods and circuits for measuring clock skew on programmable logic devices | |
| US7521962B2 (en) | Semiconductor integrated circuit apparatus | |
| Zhou et al. | Self-calibration Fan-out Method Research for Heavy-ion Accelerator Timing System |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |