CN113723046B - Fishbone-shaped clock tree and implementation method - Google Patents
Fishbone-shaped clock tree and implementation method Download PDFInfo
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- CN113723046B CN113723046B CN202110917416.XA CN202110917416A CN113723046B CN 113723046 B CN113723046 B CN 113723046B CN 202110917416 A CN202110917416 A CN 202110917416A CN 113723046 B CN113723046 B CN 113723046B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to the technical field of clock trees, and discloses a fishbone clock tree and an implementation method thereof. Has the advantages that: the fishbone clock tree structure is established by establishing the main clock tree and the sub-clock trees, so that the buffer units from the PLL to the sub-modules of the chip are reduced, and the power consumption of the chip is reduced; the main clock tree and the sub clock trees also play the role of a common path, the OCV occupies less clock cycles, and the final time sequence is easy to converge.
Description
Technical Field
The invention relates to the technical field of clock trees, in particular to a fishbone clock tree and an implementation method thereof.
Background
The clock tree is a mesh structure built by balancing a plurality of buffer units (buffer/inv cells), and has a source point, generally a clock input port (clock input port) and possibly a certain unit output pin (cell output pin) inside a design, which are built by one-level and one-level buffer units, and key factors for measuring the quality of the clock tree include: clock tree length, clock tree common path, clock tree signal transition time (clock transition time), clock tree drift (clock skew), clock tree noise, clock duty cycle.
The clock tree construction scheme is a very important step in the realization of the back-end physical design of the chip, and the quality of the clock tree directly concerns the power consumption of the chip and the running speed of the chip. The high calculation power chip has extremely high tracing speed and extremely high power consumption, and the Internet of things chip has extremely high tracing power consumption. However, in any chip, how to construct a clock tree with few stages, many common paths, low noise interference, and easily converged timing is a problem that designers in the back end of the chip need to expend energy and much time to solve.
A traditional clock tree is firstly led out of a buffer unit from a PLL (phase locked loop) during building, then two next-level buffer units are arranged by taking the buffer unit as a source, a third-level buffer unit is arranged below the next-level buffer unit, and the like is carried out until the buffer units are connected to submodules of a chip. According to the traditional clock tree building method, the number of stages of the clock tree from the PLL to each submodule is the same, the submodule close to the PLL and the submodule far away from the PLL have the same number of stages, and synchronous timing sequence check exists among a plurality of submodules.
Those skilled in the art know that too many clock buffers can cause the clock tree to have long length and large power consumption, and easily cause channel wiring congestion, the clock tree wiring occupies more resources, the clock tree has large noise, and meanwhile, too many buffer units on the clock tree can cause the clock tree to have less branching and early common paths, so that more clock cycles are occupied by OCVs, and the final timing sequence convergence is difficult.
Therefore, the existing clock tree building method needs to be improved, the chip power consumption is reduced, and the difficulty of time sequence convergence is reduced.
Disclosure of Invention
The purpose of the invention is: a novel clock tree and an implementation method are provided, so that the power consumption of a chip is reduced, and the difficulty of time sequence convergence is reduced.
In order to achieve the above object, the present invention provides a fishbone clock tree, which includes a main clock tree and several sub clock trees, wherein the main clock tree is led out from a PLL, the sub clock trees are led out from the main clock tree, the sub clock trees are provided with several clock branching points, and the clock branching points are used as the source of a traditional clock tree to establish a traditional clock tree.
Further, the master clock tree is arranged on a central axis of the chip.
Furthermore, the main clock tree comprises a plurality of first buffer units which are connected in sequence, the sub clock tree comprises a plurality of second buffer units which are connected in sequence, and the sub clock tree is led out from a connecting line between two adjacent first buffer units.
Furthermore, the first buffer unit of the main clock tree is arranged outside the sub-module of the chip, the second buffer unit penetrates through the sub-module of the chip, the sub-module penetrated by the sub-clock tree comprises a plurality of second buffer units, and a clock bifurcation point is led out between every two adjacent second buffer units.
The invention also discloses a method for realizing the fishbone clock tree, which comprises the following steps:
and acquiring the sub-module layout of the chip.
And leading out a main clock tree from the PLL of the chip and setting the main clock tree according to the layout of the sub-modules so that the main clock tree is positioned on the central axis of the chip.
Several sub-clock trees are led out from the main clock tree, and the sub-clock trees are uniformly distributed on two sides of the main clock tree.
And leading out clock bifurcation points from the sub-clock trees, and establishing the traditional clock tree by taking the clock bifurcation points as the source of the traditional clock tree.
Furthermore, the main clock tree comprises a plurality of first buffer units which are connected in sequence, the sub clock tree comprises a plurality of second buffer units which are connected in sequence, and the sub clock tree is led out from a connecting line between two adjacent first buffer units.
Furthermore, the first buffer unit of the main clock tree is arranged outside the sub-module of the chip, the second buffer units penetrate through the sub-module of the chip, the sub-module penetrated by the sub-clock tree comprises a plurality of second buffer units, and a clock bifurcation point is led out between every two adjacent second buffer units.
Furthermore, the sub-module layout of the chip comprises a single-layer sub-module layout and a double-layer sub-module layout.
Furthermore, when the chip is in a single-layer sub-module layout, the sub-clock tree led out from the main clock tree divides the chip into a plurality of sub-regions, and a traditional clock tree is established at each sub-region through a clock branch point led out from the sub-clock tree.
Furthermore, when the chip is distributed as a double-layer submodule, a plurality of second-layer submodules which are uniformly distributed are arranged on the first-layer submodule of the chip, a main clock tree is led out from a PLL of the chip and is arranged at the central axis position of the second-layer submodules, a plurality of sub clock trees are led out from the main clock tree and pass through the second-layer submodules, so that the second-layer submodules which are positioned on the same layer and in the same column of the main clock tree are positioned on the same sub clock tree, clock bifurcation points are arranged in the second-layer submodules, and the clock bifurcation points are used as the source of the traditional clock tree to arrange the traditional clock tree.
Compared with the prior art, the fishbone clock tree and the implementation method thereof have the beneficial effects that: the fishbone clock tree structure is established by establishing the main clock tree and the sub-clock trees, so that the buffer units from the PLL to the sub-modules of the chip are reduced, and the power consumption of the chip is reduced; the main clock tree and the sub clock trees also play the role of a common path, the OCV occupies less clock cycles, and the final time sequence is easy to converge.
Drawings
FIG. 1 is a diagram illustrating a conventional clock tree in the background of the present invention;
FIG. 2 is a schematic diagram of a fishbone clock tree for a single-level sub-module layout according to the present invention;
FIG. 3 is a schematic diagram of a two-layer sub-module layout of the chip of the present invention;
FIG. 4 is a schematic diagram of a fishbone clock tree for a two-level sub-module layout according to the present invention;
FIG. 5 is a schematic diagram of a sub-clock tree structure with clock branching points according to the present invention.
In the figure, 1, a master clock tree; 2. a child clock tree; 3. the data stream flows.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Example 1:
referring to fig. 2, 4 and 5, the invention discloses a fishbone clock tree, which comprises a main clock tree and a plurality of sub clock trees, wherein the main clock tree is led out from a PLL, the sub clock trees are led out from the main clock tree, the sub clock trees are provided with a plurality of clock bifurcation points, and the clock bifurcation points are used as the source of the traditional clock tree to establish the traditional clock tree.
In this embodiment, the master clock tree is disposed on a central axis of the chip. The main clock tree is arranged on the central axis of the chip or at the center of a plurality of submodules of the chip, so that the submodules of the chip are uniformly distributed on two sides of the main clock tree as far as possible, and the length of wiring and the number of the wiring can be reduced in physical distance. Meanwhile, when the main clock tree is positioned on the central axis of the chip, the sub-clock trees can conveniently and uniformly connect the sub-modules together. The layout of the actual submodules of the chip should be considered when setting the sub-clock tree, and the sub-clock tree is set according to the number and the positions of the submodules.
In this embodiment, the main clock tree includes a plurality of first buffer units connected in sequence, the sub-clock tree includes a plurality of second buffer units connected in sequence, and the sub-clock tree is led out from a connection line between two adjacent first buffer units.
In this embodiment, the plurality of first buffer units on the main clock tree form a main clock tree path, and the plurality of second buffer units on the sub-clock trees form a secondary clock tree path.
In this embodiment, the first buffer unit of the main clock tree is disposed outside the sub-module of the chip, the second buffer unit passes through the sub-module of the chip, the sub-module through which the sub-clock tree passes includes a plurality of second buffer units, and a clock bifurcation is led between two adjacent second buffer units.
An alternative embodiment is: two second buffer units are arranged in the submodule, and a clock bifurcation point is led out from a connecting line between the two second buffer units.
In the embodiment, the fishbone-shaped clock tree structure is established by establishing the main clock tree and the sub-clock trees, so that the buffer units from the PLL to the sub-modules of the chip are reduced, and the power consumption of the chip is reduced; the main clock tree and the sub-clock trees also play the role of a common path, the OCV occupies less clock cycles, and the final time sequence is easy to converge.
Example 2:
the invention also discloses a method for realizing the fishbone clock tree, which applies the fishbone clock tree in the embodiment 1 to a chip and mainly comprises the following steps:
And 2, leading out a main clock tree from the PLL of the chip and setting the main clock tree according to the layout of the sub-modules so that the main clock tree is positioned on the central axis of the chip.
And 3, leading out a plurality of sub-clock trees from the main clock tree, and enabling the sub-clock trees to be uniformly distributed on two sides of the main clock tree.
And 4, leading out clock bifurcation points from the sub-clock trees, and establishing the traditional clock tree by taking the clock bifurcation points as the source of the traditional clock tree.
In step 1, since different chips have different numbers of sub-modules during design and the arrangement positions of the sub-modules are different, the actual sub-module layout of the chip should be considered when applying the fishbone clock tree to different chips.
In this embodiment, the sub-module layout of the chip includes a single-layer sub-module layout and a double-layer sub-module layout. FIG. 2 is a schematic diagram of a single-layer sub-module chip, and FIG. 3 is a schematic diagram of a double-layer sub-module chip.
In step 2, the main clock tree is arranged on the central axis of the chip or at the center of a plurality of submodules of the chip, so that the submodules of the chip are uniformly distributed on two sides of the main clock tree as far as possible, and the length of wiring and the number of wiring can be reduced in physical distance. Meanwhile, when the main clock tree is positioned on the central axis of the chip, the sub-clock trees can conveniently and uniformly connect the sub-modules together. The layout of the actual submodules of the chip should be considered when setting the sub-clock tree, and the sub-clock tree is set according to the number and the positions of the submodules.
In step 3, the main clock tree includes a plurality of first buffer units connected in sequence, the sub clock tree includes a plurality of second buffer units connected in sequence, and the sub clock tree is led out from a connection line between two adjacent first buffer units.
In step 4, clock bifurcation points are led out from the sub-clock trees, and the clock bifurcation points are used as the source of the traditional clock tree to establish the traditional clock tree. Referring to fig. 5, a third buffer unit is disposed at a clock branch point led out from the sub-clock tree, and the third buffer unit is used as a source of the conventional clock tree to construct the conventional clock tree.
In this embodiment, the structure and setting method of the conventional clock tree are that one buffer unit is determined as a source, two next-level buffer units are set under the source buffer unit, and a third-level buffer unit is set under the next-level buffer unit, that is, two next-level buffer units are set under the previous-level buffer unit. And repeatedly establishing the multi-stage buffer units until all the chip submodules are connected.
In this embodiment, the first buffer unit of the main clock tree is disposed outside the sub-module of the chip, the second buffer unit passes through the sub-module of the chip, the sub-module through which the sub-clock tree passes includes a plurality of second buffer units, and a clock bifurcation is led between two adjacent second buffer units.
Since embodiment 2 is written based on embodiment 1, the technical features that are partially repeated are not repeated.
Example 3:
on the basis of embodiment 2, referring to fig. 2, when a chip is laid out as a single-layer sub-module, a sub-clock tree derived from a main clock tree divides the chip into a plurality of sub-regions, and a conventional clock tree is established at each sub-region through a clock branch point derived from the sub-clock tree.
Example 4:
on the basis of embodiment 2, when the chip is a double-layer sub-module layout, a plurality of uniformly distributed second-layer sub-modules are arranged on a first-layer sub-module of the chip, a main clock tree is led out from a PLL of the chip and is arranged in a central axis position of the second-layer sub-modules, a plurality of sub-clock trees are led out from the main clock tree and pass through the second-layer sub-modules, so that the second-layer sub-modules which are positioned on the same layer and in the same column of the main clock tree are positioned on the same sub-clock tree, a clock branching point is arranged in the second-layer sub-modules, and the clock branching point is used as a source of a traditional clock tree to arrange a traditional clock tree.
Referring to fig. 3 and 4, the layout of the double-layer sub-modules of the chip specifically includes: a second tier sub-module is placed on the first tier sub-module, the large box of figure 4. The second layer of sub-modules is multiple.
In this embodiment, when building a fishbone-shaped clock tree, the central axis positions of a plurality of second-layer sub-modules are selected to set a main clock tree, and then the sub-clock trees are drawn out from the arrangement positions of the second-layer sub-modules, and the sub-clock trees pass through the second-layer sub-modules. Reference numeral 1 in fig. 4 is a main clock tree which is directly provided from the PLL and is laterally distributed in the middle of the chip under the condition that clock transition time (clock transition time) is satisfied, and reference numeral 2 is a clock tree which is sent from the main clock tree and passes through the sub-modules, and the main clock tree and the sub-clock trees together form a fishbone-shaped clock tree structure.
In this embodiment, reference numeral 3 in fig. 4 denotes the data stream flow direction, and data is generated by the chip main control logic. Examples are as follows: the data generated by the main control is processed by the north H12 submodule and then flows into H6 for processing, and then enters H0 for processing, the data is reversely sent back to H6 after being processed for 2 times by H0, the data is processed once again by H6 and sent back to H12, the data is sent back to the chip main control unit after being processed by H12, and a data processing is completed. In fig. 4 12 data processing links are shown.
Referring to fig. 5, the common path of the clock tree of the flip-flops in the sub-module H12 is buffer0 and buffer4, a conventional clocktree is constructed behind the buffer4 (in the same way as in fig. 1), and the non-common path of the clock for the flip-flops inside H12 is controlled in the sub-module H12, and belongs to the common path of the clock from the PLL to the buffer 4; the common paths of the clocks of the flip-flops in the module H6 are buffer0, buffer1, buffer2 and buffer5, and similarly, a traditional clock tree is constructed behind the buffer5, and the non-common paths of the clocks for the flip-flops inside the module H6 are controlled inside the sub-module H6, and all the clock paths from the beginning of the PLL to the buffer5 belong to a common clock path. For the flip-flops needing to be interacted between the sub-modules H12 and H6, the clock common path only reaches the buffer0, and the delay of the buffer1 + the buffer2 is the deviation between the flip-flop clocks inside the sub-modules H12 and H6, the interface is fully considered in the logic design stage, and the timing margin is sufficient.
If the chip structure in fig. 4 directly uses the conventional clock tree to connect the PLL and the sub-module, the connection mode is the connection mode in fig. 1. The number of clock tree stages from the PLL to each submodule is the same, and physically, submodules H0, H6, H12, H18, H24, and H30 which are close to the PLL do not need as many clock tree buffer lists according to the physical distance. And synchronous timing check exists among H0, H6, H12, H18, H24 and H30. Too many clock buffers can cause the clock tree to have long length, the clock tree has high power consumption, the channel wiring is easy to be congested, the clock tree wiring occupies more resources, the noise on the clock tree is high, meanwhile, too many buffer units on the clock tree can cause the clock tree to have less branching and early public paths, more clock cycles are occupied by OCVs, and the final time sequence convergence is difficult.
To sum up, the embodiment of the invention provides a fishbone clock tree and a realization method thereof, compared with the prior art, the fishbone clock tree has the beneficial effects that: the fishbone clock tree structure is established by establishing the main clock tree and the sub-clock trees, so that the buffer units from the PLL to the sub-modules of the chip are reduced, and the power consumption of the chip is reduced; the main clock tree and the sub clock trees also play the role of a common path, the OCV occupies less clock cycles, and the final time sequence is easy to converge.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.
Claims (6)
1. A fishbone clock tree is characterized by comprising a main clock tree and a plurality of sub clock trees, wherein the main clock tree is led out from a PLL (phase locked loop), the sub clock trees are led out from the main clock tree, the sub clock trees are provided with a plurality of clock bifurcation points, and the clock bifurcation points are used as the source of a traditional clock tree to establish the traditional clock tree; the main clock tree comprises a plurality of first buffer units which are connected in sequence, the sub clock tree comprises a plurality of second buffer units which are connected in sequence, and the sub clock tree is led out from a connecting line between two adjacent first buffer units; the first buffer unit of the main clock tree is arranged outside the sub-modules of the chip, the second buffer units penetrate through the sub-modules of the chip, the sub-modules penetrated through by the sub-clock tree comprise a plurality of second buffer units, and a clock bifurcation is led out between every two adjacent second buffer units.
2. The fishbone clock tree of claim 1, wherein the master clock tree is disposed on a central axis of the chip.
3. A method for realizing a fishbone clock tree is characterized by comprising the following steps:
obtaining the sub-module layout of the chip;
leading out a main clock tree from a PLL of the slave chip and setting the main clock tree according to the layout of the sub-modules so that the main clock tree is positioned on a central axis of the chip;
leading out a plurality of sub-clock trees from the main clock tree, and enabling the sub-clock trees to be uniformly distributed on two sides of the main clock tree;
leading out clock bifurcation points from the sub-clock trees, and establishing the traditional clock trees by taking the clock bifurcation points as the sources of the traditional clock trees;
the main clock tree comprises a plurality of first buffer units which are connected in sequence, the sub clock tree comprises a plurality of second buffer units which are connected in sequence, and the sub clock tree is led out from a connecting line between two adjacent first buffer units;
the first buffer unit of the main clock tree is arranged outside the sub-modules of the chip, the second buffer units penetrate through the sub-modules of the chip, the sub-modules penetrated through by the sub-clock tree comprise a plurality of second buffer units, and a clock bifurcation is led out between every two adjacent second buffer units.
4. The method as claimed in claim 3, wherein the sub-module layout of the chip includes a single-layer sub-module layout and a double-layer sub-module layout.
5. The method as claimed in claim 4, wherein when the chip is in a single-layer sub-module layout, the sub-clock tree derived from the main clock tree divides the chip into a plurality of sub-regions, and the conventional clock tree is established at each sub-region by a clock branch point derived from the sub-clock tree.
6. The method as claimed in claim 4, wherein when the chip is a double-layer sub-module layout, a plurality of uniformly distributed second-layer sub-modules are disposed on a first-layer sub-module of the chip, the main clock tree is led out from the PLL of the chip and is disposed on a central axis of the second-layer sub-modules, a plurality of sub-clock trees are led out from the main clock tree and pass through the second-layer sub-modules, so that the second-layer sub-modules on the same layer and the same column of the main clock tree are disposed on the same sub-clock tree, and a clock bifurcation point is disposed in the second-layer sub-modules and serves as a source of a conventional clock tree to dispose the conventional clock tree.
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| CN103793483B (en) * | 2014-01-16 | 2017-02-15 | 清华大学 | Clock tree generating method and system based on clock node clusters |
| JP2015185769A (en) * | 2014-03-25 | 2015-10-22 | ソニー株式会社 | Unit cell circuit of clock tree, clock tree, and device |
| CN111259614B (en) * | 2018-11-15 | 2022-04-26 | 北京大学 | Design method for optimizing metal routing of fishbone clock tree |
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