CN103793483B - Clock tree generating method and system based on clock node clusters - Google Patents
Clock tree generating method and system based on clock node clusters Download PDFInfo
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- CN103793483B CN103793483B CN201410021210.9A CN201410021210A CN103793483B CN 103793483 B CN103793483 B CN 103793483B CN 201410021210 A CN201410021210 A CN 201410021210A CN 103793483 B CN103793483 B CN 103793483B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a clock tree generating method based on clock node clusters. The clock tree generating method includes the following steps: (1) dividing clock nodes in a territory into the multiple bottom-layer clock node clusters, constructing a bottom-layer clock tree inside the bottom-layer clock node clusters, and inserting first buffers into the root of the bottom-layer clock tree, wherein the first buffers are used for driving the bottom-layer clock node clusters; (2) enabling all the first buffers to serve as top-layer clock nodes to construct a top-layer clock tree, and inserting a plurality of second buffers into routing of the top-layer clock tree, wherein the second buffers are used for driving the top-layer clock nodes; (3) combining the bottom-layer clock tree with the top-layer clock tree with the first buffers as connecting points to form a whole clock tree. According to the clock tree generating method, the power consumption of a clock network and clock skewing can be reduced.
Description
Technical field
The present invention relates to IC design field, more particularly, to a kind of clock trees generation side tying group based on clock node
Method and system.
Background technology
Clock network controls the synchronizing signal of whole integrated circuit, plays decisive in the performance of circuit chip
Effect.The factor direct relation such as the power consumption of clock network, clock jitter the designing quality of whole circuit chip.
Increase with super large-scale integration integrated level and the raising of operating frequency, the power consumption of chip unit area is in
Exponential growth.For battery-powered portable set, power consumption is directly linked up with stand-by time and battery life.And
The length of stand-by time and battery life is most important for portable set, directly influences the market competition of product
Status.For high reliability equipment, power consumption is excessive to lead to chip temperature drastically to raise, and then affects the electrical property of device and line
Can, or even cause circuit malfunction.Therefore, low-power consumption has become as one of main target of optimization of IC design.
Clock network is high due to its clock frequency, the features such as the load capacitance of driving is big, occupies larger in total power consumption
Proportion.Therefore, clock network design, in addition to considering traditional optimization aim such as line length, time delay, deviation, more should pay attention to work(
Consumption, the power consumption only resolving clock network could effectively reduce the total power consumption of whole circuit.
In low power dissipation design flow process traditional at present, mainly pass through to reduce clock line in clock network construction phase
Long, gated clock, the technology such as duplicate supply pressure is reducing the power consumption of clock network.
Traditional commonly used binary tree structure of clock network integrated approach.Clock jitter in order to meet system requirements will
Ask, be frequently necessary to insert the time delay of substantial amounts of buffer de-regulation clock node in the vicinity of clock node, as shown in figure 4, its
It is clock trees construction result schematic diagram under conventional clock network synthesis flow process for the sample shown in Fig. 3.Clock node is turned
For throw-over rate, a big chunk buffer is unwanted, has thus resulted in the waste of power consumption.
Therefore, need a kind of scheme badly to solve the above problems, to reduce the waste of power consumption and effectively to reduce whole system
Clock jitter.
Content of the invention
The technical problem to be solved is to need to provide a kind of to reduce the waste of power consumption and effectively reduce
The clock trees generation method of the clock jitter of whole system.
In order to solve above-mentioned technical problem it is proposed that a kind of based on clock node tie group clock trees generation method, including
Following steps：
Step A, the clock node in domain is divided into several bottom clock node clusters, in described bottom clock node
Carry out bottom clock trees construction inside cluster, insert the first buffer in the root of described bottom clock trees, for driving described bottom
Layer clock node cluster；
Step B, using all of first buffer as top layer clock node, constructs top layer clock trees, in described top layer
Several the second buffers are inserted on the cabling of Zhong Shu, for driving described top layer clock node；
Step C, with described first buffer as junction point, when bottom clock trees and the merging of top layer clock trees are integrally formed
Zhong Shu.
According to one embodiment of present invention, also include step D, by carry out on cabling in described overall clock trees around
Line, changes track lengths, reduces the clock jitter of overall clock trees.
According to one embodiment of present invention, in described step A, the clock node in domain is divided into several bottoms
Layer clock node cluster, is according to the first clock node information and the first complaint message, is divided using the balance two with obstacle for the OBB and calculate
Method carries out what L recurrence division obtained, recurrence number of times
Wherein, N represents the number of clock node in domain, ciRepresent the electric capacity of i-th clock node, D represents in domain
Apart from the manhatton distance of two farthest nodes, α, β, CbFor constant, α, β are used for adjusting clock node electric capacity and walk line capacitance
Shared proportion, C in total capacitance is estimatedbRepresent the expected value of the total load to bottom clock node cluster.
According to one embodiment of present invention, carry out bottom inside described bottom clock node cluster in described step A
Clock trees construct, and are according to second clock nodal information and the second complaint message, using balance two partitioning algorithm with obstacle for the OBB
Described bottom clock node cluster is divided, merges insertion algorithm using the delay with obstacle for the ODME and complete clock trees coiling,
Generate bottom clock trees.
According to one embodiment of present invention, the construction top layer clock trees in described step B, are according to the 3rd clock node
Described top layer clock node is divided by information and the 3rd complaint message using balance two partitioning algorithm with obstacle for the OBB, profit
Merge insertion algorithm with the delay with obstacle for the ODME and complete clock trees coiling, determine top layer clock trees cabling.
According to one embodiment of present invention, when the output signal of described first buffer reaches clock node, signal turns over
Rotational speed rate is less than the upset speed that overall clock trees require.
According to one embodiment of present invention, from arbitrary road of clock source to described clock node in described overall clock trees
The quantity sum of the first buffer on footpath and the second buffer is even number.
According to a further aspect in the invention, a kind of clock trees generation system being tied group based on clock node is also provided, including：
Bottom clock trees constructing module, for the clock node in domain is divided into several bottom clock node clusters,
Carry out bottom clock trees construction inside described bottom clock node cluster, insert the first buffer in the root of bottom clock trees,
Drive described bottom clock node cluster；
Top layer clock trees constructing module, using all of first buffer as top layer clock node, constructs top layer clock trees,
Several the second buffers are inserted on the cabling of top layer clock trees, for driving top layer clock node；
Overall clock trees constructing module, for being closed bottom clock trees and top layer clock trees with the first buffer for junction point
And it is integrally formed clock trees.
According to one embodiment of present invention, also include：
Global optimization module, by carrying out coiling on cabling in described overall clock trees, changes track lengths, reduces whole
The clock jitter of individual clock trees.
Present invention offers following beneficial effect：By the clock node in domain is divided into several clock nodes
Cluster, each node cluster is driven by a buffer, and several clock nodes share a buffer, therefore number of buffers in bottom
Measure more common clock tree synthesis flow process less.Meanwhile, the clock node cluster of bottom is not because of clock node knot group
Increase time delay.Then using all buffers as the comprehensive input node of clock network, carry out clock network construction and optimize, energy
Enough power consumptions effectively reducing clock network, and meet the switching rate of system requirements, clock jitter, time delay etc. constrains.
Other features and advantages of the present invention will illustrate in the following description, and partly become from description
It is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by wanting in description, right
Structure specifically noted in book and accompanying drawing is asked to realize and to obtain.
Brief description
Fig. 1 is that the flow process of the according to embodiments of the present invention one clock trees generation method tying group based on clock node is illustrated
Figure；
Fig. 2 shows the flow chart selecting buffer in the embodiment of the present invention one；
Fig. 3 is an actual domain sample；
Fig. 4 is the construction result schematic diagram of clock trees under conventional clock tree general flow for the sample shown in Fig. 3；
Fig. 5 is to tie the clock trees generation method of group to domain sample shown in Fig. 3 using embodiment one based on clock node
The construction result schematic diagram of the clock trees after being processed；
Fig. 6 is the domain sample in embodiment two；
Fig. 7 is the result schematic diagram constructing bottom clock trees in embodiment two；
Fig. 8 is the virtual schematic diagram constructing top layer clock trees in embodiment two；
Fig. 9 is the result schematic diagram generating overall clock trees in embodiment two；
Figure 10 is that in embodiment two, the clock trees after clock jitter optimization processing generate result schematic diagram；
Figure 11 is the according to embodiments of the present invention three clock trees generation system schematic tying group based on clock node.
Specific embodiment
To describe embodiments of the present invention below with reference to accompanying drawing in detail, whereby to the present invention how application technology means
To solve technical problem, and reach realizing process and fully understanding and implement according to this of technique effect.As long as it should be noted that
Do not constitute conflict, each feature in various embodiments of the present invention and each embodiment can be combined with each other, the technical side being formed
Case is all within protection scope of the present invention.
In addition, the step that illustrates of flow process in accompanying drawing can be in the department of computer science of such as one group of computer executable instructions
Execute in system, and although showing logical order in flow charts, but in some cases, can be with different from herein
The shown or described step of order execution.
Embodiment one
Fig. 1 is that the flow process of the according to embodiments of the present invention one clock trees generation method tying group based on clock node is illustrated
Figure, to describe each step of the present embodiment in detail below with reference to Fig. 1.
Step A, the clock node in domain is divided into several bottom clock node clusters, in described bottom clock node
Carry out bottom clock trees construction inside cluster, insert the first buffer in the root of described bottom clock trees, for driving described bottom
Layer clock node cluster；
Specifically, including following sub-step：
Step A1, the clock node in domain is divided into several bottom clock node clusters；
Including：
Step A11, determines the first clock node information and the first complaint message in domain；
Read in layout information, the clock node data in domain is stored in the data structure of setting, constitute the first clock
Nodal information, this data structure includes the two-dimensional coordinate of clock node, capacitance；The data of obstacle in domain is stored in setting
In data structure, constitute the first complaint message, this data structure includes the two-dimensional coordinate of obstacle, length and width；
Step A12, according to the first clock node information and the first complaint message, using OBB（Obstacle-aware
Balanced Bipartition）Balance two partitioning algorithm with obstacle carries out L recurrence and divides, by version to clock node
The clock node of in figure is divided into several bottom clock node clusters；The purpose of this algorithm is, obstacle in considering domain
In the case of carry out the division of bottom clock node cluster, can be with cut-through with the clock cabling ensureing to generate.
Preferably, in OBB algorithm, the number of times L of recurrence to be calculated by following formula：
Wherein, N represents the number of clock node in domain, ciRepresent the electric capacity of i-th clock node, D represents in domain
Apart from the manhatton distance of two farthest nodes, α, β, CbFor constant.α, β are used for adjusting clock node electric capacity and walk line capacitance
Shared proportion in total capacitance is estimated.CbRepresent the expected value of the total load to bottom clock node cluster.
It is used for estimating the total capacitance of clock node and cabling in bottom clock node cluster.
Represent the expected value to bottom clock node number of clusters amount, because OBB algorithm is one
Two partition process, so the expected value that the number of times L of recurrence is this quantity takes 2 logarithm.
Step A2, carries out bottom clock trees construction inside bottom clock node cluster；
Specifically, including following sub-step：
Step A21, determines the second clock nodal information within bottom clock node cluster and the second complaint message.
Preferably, read in bottom clock node cluster information, the clock node data in bottom clock node cluster is stored in and sets
In fixed data structure, constitute second clock nodal information, this data structure includes the two-dimensional coordinate of clock node, capacitance；
Obstruction data in bottom clock node cluster is stored in the data structure of setting, constitutes the second complaint message, this data structure
Including the two-dimensional coordinate of obstacle, length and width.
Step A22, according to second clock nodal information and the second complaint message, using OBB algorithm by described bottom clock
Clock node in node cluster is divided, till clock node is divided into individual node.
Step A23, according to second clock nodal information and the second complaint message, using ODME（obstacle-aware
Deferred-Merge Embedding）Delay with obstacle merges insertion algorithm and completes clock trees coiling, determines bottom clock
The cabling of tree, generates bottom clock trees.So far, before being not inserted into bottom local buffer, generate a zero-deviation
Bottom clock trees.
Step A3, inserts the first buffer in the root of bottom clock trees, for driving described bottom clock node cluster；
It is illustrated in figure 2 the flow chart in this step, buffer is selected according to driving force, specifically, by following sub-step
Suddenly select the first buffer：
Step A31, buffer is sorted from small to large according to driving force.
Step A32, calculates the decay on cabling for the upset speed of clock signal.
Calculate decay Sl (e) on cabling of the upset speed of clock signal by following formula,
Sl(e)=ln9·r·(0.5·c+cload) （2）
Wherein, r represents the resistance of the cabling that buffer drives, and c represents the electric capacity of cabling, cloadRepresent that cabling drives negative
Carry electric capacity.
Step A33, searches the upset speed of the output signal of buffer successively using look-up table.Preferably, pass through
NGSPICE circuit simulation obtains the upset rate lookup table of the output signal of buffer.
Step A34, signal calculated reaches signal upset speed during clock node.
Reach signal during clock node by following formula come signal calculated and overturn speed Sl (r),
Wherein, Sl (b) represents the signal upset speed of buffer output, and Sl (e) represents the upset speed of signal in cabling
On decay.
Step A35, when judging that signal reaches clock node, whether the upset speed of signal requires more than overall clock trees
Upset speed,
If it is, repeat step A33～A35；
If it is not, then carrying out step A36；
Step A36, chooses the local buffer meeting the buffer of overall clock trees requirement as this clock node cluster, this
In referred to as the first buffer.
By above-mentioned steps, the clock node in domain several bottom clock node clusters are divided into, in each bottom
Complete bottom clock trees construction in clock node cluster, and the root in bottom clock trees inserts the first buffer, for driving
Bottom clock node cluster.Also need to following steps after this step to complete the construction of whole clock tree construction.
Step B, using all of first buffer as top layer clock node, constructs top layer clock trees, in top layer clock trees
Cabling on insert several the second buffers, for driving top layer clock node；
Specifically, including following sub-step：
Step B1, determines the 3rd clock node information and the 3rd complaint message of top layer clock node；
Using the input capacitance of all first buffers as top layer clock node electric capacity, by the two of all first buffers
Dimension coordinate is as the two-dimensional coordinate of top layer clock node.
Top layer clock node data is stored in the data structure of setting, constitutes the 3rd clock node information, this data is tied
Structure includes top layer clock node, i.e. the two-dimensional coordinate of the first buffer, capacitance；Obstruction data in domain is stored in setting
In data structure, constitute the 3rd complaint message, this data structure includes the two-dimensional coordinate of obstacle in domain, length and width.
Step B2, according to the 3rd clock node information and the 3rd complaint message, is entered to top layer clock node using OBB algorithm
Row divides, until being divided into single clock node；
Step B3, completes clock trees coiling using ODME algorithm, determines top layer clock cabling, generates top layer clock trees.
Step B4, inserts several the second buffers on the cabling of top layer clock trees, for driving top layer clock trees, and
The signal meeting system requirements overturns the requirement of speed and signal polarity.
Determine the position candidate of the second buffer first.In the present embodiment, the position candidate of the second buffer is in y-bend
It is equally distributed in each edge of tree.It is the side of L for a length, the second number of buffers that may be inserted on this edge
Measuring N is
Wherein m represents the drivable track lengths of driving force buffer placed in the middle；
Therefore, on this edge, spacing d of the second buffer is
d=L/(N+1).
Because the length of each edge is all not quite similar in binary tree, spacing d of the second buffer is not one and consolidates
Fixed value.
Then, buffer is selected according to driving force, to meet the requirement that clock signal overturns speed.
Specifically, according to the step shown in Fig. 2, according to step A31 to step A36, selecting respectively needs in each candidate
The buffer of insertion on position.
Meanwhile, in order to meet the requirement of signal polarity, need to ensure every from clock the source point then path of clock node
The first buffer and the second buffer quantity summation be even number.
Step C, with the first buffer as junction point, bottom clock trees and top layer clock trees is merged and is integrally formed clock
Tree.
By above step, obtain complete clock trees, but be because that buffer itself can cause time delay, so when overall
The deviation of clock is not also optimum.
Preferably in addition it is also necessary to following steps optimize the deviation of overall clock trees：
Step D, by carrying out coiling on some paths from clock source to clock node in overall clock trees, change is walked
The length of line, reduces the clock jitter of overall clock trees.
In the present embodiment, simulation calculation is carried out to overall clock trees by NGSPICE breadboardin simulation software, obtain standard
Calculate, after true clock jitter result, the length that each edge should carry out coiling, be finely adjusted.
Preferably, only coiling in the cabling of top layer clock trees, changes the length of cabling in clock trees, the overall clock of fine setting
Tree deviation, obtains the clock trees result of optimum.
Fig. 5 is to tie the clock tree synthesis method of group to domain sample shown in Fig. 3 using the present embodiment based on clock node
Clock trees construction result schematic diagram after being processed, Fig. 5 and Fig. 4 is compared it can be seen that wrapping in clock network in Fig. 5
Containing less buffer, therefore there is relatively low power consumption, and equally meet the signal of system requirements and overturn speed, clock is inclined
Difference, time delay etc. constrains.
In sum, the present invention is by being divided into several clock node clusters, each node by the clock node in domain
Cluster is driven by a buffer, and several clock nodes share a buffer in bottom, and therefore number of buffers is more common
Clock tree synthesis flow process is less.Meanwhile, the clock node cluster of bottom does not increase time delay because of clock node knot group.So
Afterwards using all buffers as the comprehensive input node of clock network, carry out clock network construction and optimize, can effectively reduce
The power consumption of clock network, and meet the switching rate of system requirements, clock jitter, time delay etc. constrains.
Embodiment two
Below embodiment two is illustrated, to further understand the feature of the embodiment of the present invention.
Domain sample as shown in Figure 6, this domain includes 16 clock nodes.Clock node by using embodiment one
This 16 clock nodes are reasonably divided by knot group's method, and construct the clock tree construction of a high-performance low-power-consumption.
First, the clock node in domain being utilized OBB algorithm partition is 4 clock node clusters, as bottom clock section
Point cluster, then inside bottom clock node cluster, carry out bottom clock trees construction using OBB algorithm and ODME algorithm, finally for
Each bottom clock node cluster distributes first buffer, inserts this first buffer in bottom clock usage tree root.Result is such as
Shown in Fig. 7.Because being only inserted a buffer in bottom clock trees, it can be ensured that the quantity in overall clock trees is relatively
Few.
Then, carry out top layer clock trees construction, be illustrated in figure 8 the virtual schematic diagram of construction top layer clock trees.In figure institute
The top layer clock trees shown still in domain among, the first buffer 801 and the first buffer 801 ' are same buffer, by first
Buffer 801 ' is as top layer clock node.Likewise, the first buffer 802 and the first buffer 802 ' are same buffer,
First buffer 803 and the first buffer 803 ' are same buffer, and the first buffer 804 is same with the first buffer 804 '
Buffer；By the first buffer 802 ', the first buffer 803 ', the first buffer 804 ' is as top layer clock node.Using OBB
Algorithm and ODME algorithm, generate top layer clock trees, are that top layer clock trees distribute the second buffer, in walking of top layer clock trees
Several the second buffers are inserted in line.
Finally, with the first buffer as junction point, bottom clock trees and top layer clock trees are connected, generate overall clock
Tree, as shown in Figure 9.
Preferably, by coiling is carried out on two paths in overall clock trees, change the length of cabling, when reducing whole
The clock jitter of Zhong Shu, obtains the clock trees result of optimum, as shown in Figure 10.
Embodiment three
Figure 11 is the according to embodiments of the present invention three clock trees generation system schematic tying group based on clock node.
Generate system 110 based on the clock trees that clock node ties group and include bottom clock trees constructing module 1101, during top layer
Clock tree constructing module 1102, overall clock trees constructing module 1103 is it is preferable that also include global optimization module 1104.
Bottom clock trees constructing module 1101 is used for for the clock node in domain being divided into several bottom clock nodes
Cluster, carries out bottom clock trees construction inside bottom clock node cluster, inserts the first buffer in the root of bottom clock trees, drives
Dynamic bottom clock node cluster.Bottom clock trees constructing module 1101 is by the information transmission of bottom clock trees information, the first buffer
To top layer clock trees constructing module 1102 and overall clock trees constructing module 1103.
All of first buffer as top layer clock node, is constructed top layer clock by top layer clock trees constructing module 1102
Tree, inserts several the second buffers, for driving top layer clock node on the cabling of top layer clock trees.And by top layer clock
Tree information and the second buffer information pass to overall clock trees constructing module 1103.
Overall clock trees constructing module 1103, with the first buffer as junction point, bottom clock trees and top layer clock trees is closed
And it is integrally formed clock trees.
Preferably, global optimization module 1104 is passed through to carry out coiling on cabling in described overall clock trees, changes cabling
The clock jitter of whole clock trees, drops in length.
Bottom clock trees constructing module 1101, top layer clock trees constructing module 1102, overall clock trees constructing module 1103,
Global optimization module 1104 executes step A in embodiment one, step B, step C, the operation of step D respectively, and here is no longer detailed
Thin expansion explanation.
Those skilled in the art should be understood that each module of the above-mentioned present invention or step can be filled with general calculating
Put realization, they can concentrate on single computing device, or be distributed on the network that multiple computing devices are formed, can
Selection of land, they can be realized with the executable program code of computing device, it is thus possible to be stored in storage device
To be executed by computing device, or they to be fabricated to respectively each integrated circuit modules, or by the multiple modules in them
Or step is fabricated to single integrated circuit module to realize.So, the present invention is not restricted to any specific hardware and software
In conjunction with.
Although disclosed herein embodiment as above, described content is only to facilitate understanding the present invention and adopting
Embodiment, is not limited to the present invention.Technical staff in any the technical field of the invention, without departing from this
On the premise of the disclosed spirit and scope of invention, any modification and change can be made in the formal and details implemented,
But the scope of patent protection of the present invention, still must be defined by the scope of which is defined in the appended claims.
Claims (8)
1. a kind of clock trees generation method based on clock node knot group is it is characterised in that comprise the following steps：
Step A, the clock node in domain is divided into several bottom clock node clusters, in described bottom clock node cluster
Portion carries out bottom clock trees construction, inserts the first buffer in the root of described bottom clock trees, during for driving described bottom
Clock node cluster；
Step B, using all of first buffer as top layer clock node, constructs top layer clock trees, in described top layer clock trees
Cabling on insert several the second buffers, for driving described top layer clock node；
Step C, with described first buffer as junction point, bottom clock trees and top layer clock trees is merged and is integrally formed clock
Tree；
Wherein, the clock node in domain is divided into several bottom clock node clusters in described step A, is according to first
Clock node information and the first complaint message, carry out L recurrence division using balance two partitioning algorithm with obstacle for the OBB and obtain
, recurrence number of times
Wherein, the first clock node information is the clock node data in whole domain, and the first complaint message is in whole domain
All of obstruction data, N represents the number of clock node in domain, ciRepresent the electric capacity of i-th clock node, D represents domain
The manhatton distance of two farthest nodes of middle distance, α, β, CbFor constant, α, β are used for adjusting clock node electric capacity and cabling electricity
Hold shared proportion in total capacitance is estimated, CbRepresent the expected value of the total load to bottom clock node cluster.
2. the method for claim 1 is it is characterised in that also include step D, by cabling in described overall clock trees
On carry out coiling, change track lengths, reduce the clock jitter of overall clock trees.
3. method as claimed in claim 1 or 2 it is characterised in that in described step A inside described bottom clock node cluster
Carry out bottom clock trees construction, be according to second clock nodal information and the second complaint message, using the balance two with obstacle for the OBB
Described bottom clock node cluster is divided by partitioning algorithm, merges insertion algorithm using the delay with obstacle for the ODME and completes clock
Tree coiling, generates bottom clock trees, and wherein, described second clock nodal information is node contained by each bottom clock node cluster inside
Clock node data, described second complaint message is the internal all of complaint message of each bottom clock node cluster.
4. method as claimed in claim 3, it is characterised in that construction top layer clock trees in described step B, is according to the 3rd
Described top layer clock node is entered by clock node information and the 3rd complaint message using balance two partitioning algorithm with obstacle for the OBB
Row divides, and merges insertion algorithm using the delay with obstacle for the ODME and completes clock trees coiling, determines top layer clock trees cabling, its
In, described 3rd clock node information is the clock node data of all of top layer clock node, and described 3rd complaint message is
All of obstruction data in whole domain.
5. method as claimed in claim 4 it is characterised in that described first buffer output signal reach clock node when
The upset speed of signal is less than the upset speed that overall clock trees require.
6. method as claimed in claim 5 is it is characterised in that from clock source to described clock node in described overall clock trees
Either path on the first buffer and the second buffer quantity sum be even number.
7. a kind of clock trees generation system based on clock node knot group is it is characterised in that include：
Bottom clock trees constructing module, for the clock node in domain is divided into several bottom clock node clusters, in institute
State and inside bottom clock node cluster, carry out bottom clock trees construction, insert the first buffer in the root of bottom clock trees, drive
Described bottom clock node cluster；
Top layer clock trees constructing module, using all of first buffer as top layer clock node, constructs top layer clock trees, on top
Several the second buffers are inserted, for driving top layer clock node on the cabling of layer clock trees；
Overall clock trees constructing module, for being merged into bottom clock trees and top layer clock trees with the first buffer for junction point
For overall clock trees；
Clock node in domain is divided into several bottom clock node clusters, is according to the first clock node information and first
Complaint message, carries out what L recurrence division obtained using balance two partitioning algorithm with obstacle for the OBB, recurrence number of times
Wherein, the first clock node information is the clock node data in whole domain, and the first complaint message is in whole domain
All of obstruction data, N represents the number of clock node in domain, ciRepresent the electric capacity of i-th clock node, D represents domain
The manhatton distance of two farthest nodes of middle distance, α, β, CbFor constant, α, β are used for adjusting clock node electric capacity and cabling electricity
Hold shared proportion in total capacitance is estimated, CbRepresent the expected value of the total load to bottom clock node cluster.
8. system as claimed in claim 7 is it is characterised in that also include：
Global optimization module, by carrying out coiling on cabling in described overall clock trees, changes track lengths, when reducing whole
The clock jitter of Zhong Shu.
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