CN103793483A - Clock tree generating method and system based on clock node clusters - Google Patents

Abstract

The invention discloses a clock tree generating method based on clock node clusters. The clock tree generating method includes the following steps: (1) dividing clock nodes in a territory into the multiple bottom-layer clock node clusters, constructing a bottom-layer clock tree inside the bottom-layer clock node clusters, and inserting first buffers into the root of the bottom-layer clock tree, wherein the first buffers are used for driving the bottom-layer clock node clusters; (2) enabling all the first buffers to serve as top-layer clock nodes to construct a top-layer clock tree, and inserting a plurality of second buffers into routing of the top-layer clock tree, wherein the second buffers are used for driving the top-layer clock nodes; (3) combining the bottom-layer clock tree with the top-layer clock tree with the first buffers as connecting points to form a whole clock tree. According to the clock tree generating method, the power consumption of a clock network and clock skewing can be reduced.

Description

Clock Tree based on clock node knot group generates method and system

Technical field

The present invention relates to integrated circuit (IC) design field, relate in particular to a kind of Clock Tree based on clock node knot group and generate method and system.

Background technology

The synchronizing signal of whole integrated circuit in clock network control, in the performance performance of circuit chip, plays conclusive effect.The factor such as power consumption, the clock jitter direct relation of clock network the designing quality of whole circuit chip.

Along with the increase of VLSI (very large scale integrated circuit) integrated level and the raising of frequency of operation, the power consumption of chip unit area is exponential growth.For battery-powered portable set, power consumption is directly linked up with stand-by time and battery life.And the length of stand-by time and battery life is most important for portable set, directly have influence on the market competition status of product.For high reliability equipment, the excessive chip temperature that causes of power consumption sharply raises, and then affects the electric property of device and line, even causes circuit malfunction.Therefore, low-power consumption has become one of main target of optimization of integrated circuit (IC) design.

Clock network is because its clock frequency is high, and the feature such as the load capacitance of driving is large occupies larger proportion in total power consumption.Therefore, clock network design, except considering traditional optimization aim such as line length, time delay, deviation, more should be paid attention to power consumption, and the power consumption of only resolving clock network could effectively reduce the total power consumption of whole circuit.

In at present traditional low power dissipation design flow process, be mainly by reducing clock line length at clock network construction phase, gated clock, the technology such as duplicate supply pressure reduce the power consumption of clock network.

Traditional clock network integrated approach generally adopts binary tree structure.In order to meet the clock jitter requirement of system requirements, near clock node, often need to insert a large amount of impact dampers and go to regulate the time delay of clock node, as shown in Figure 4, it is the Clock Tree structure result schematic diagram of sample shown in Fig. 3 under traditional clock network general flow.For the switching rate of clock node, impact damper is unwanted greatly, thereby has caused the waste of power consumption.

Therefore, need a kind of scheme badly and solve the problems referred to above, to reduce the waste of power consumption and effectively to reduce the clock jitter of whole system.

Summary of the invention

Technical matters to be solved by this invention is that a kind of Clock Tree generation method that can reduce the waste of power consumption and effectively reduce the clock jitter of whole system need to be provided.

In order to solve the problems of the technologies described above, a kind of Clock Tree generation method based on clock node knot group has been proposed, comprise the following steps:

Steps A, is divided into several bottom clock nodes bunch by the clock node in domain, carries out bottom Clock Tree structure in described bottom clock node bunch inside, inserts the first impact damper at the root of described bottom Clock Tree, for driving described bottom clock node bunch;

Step B, using the first all impact dampers as top layer clock node, structure top layer Clock Tree inserts several the second impact dampers, for driving described top layer clock node on the cabling of described top layer Clock Tree;

Step C, take described the first impact damper as tie point, becomes overall Clock Tree by bottom Clock Tree and the merging of top layer Clock Tree.

According to one embodiment of present invention, also comprise step D, by winding the line on cabling, change track lengths in described overall Clock Tree, reduce the clock jitter of overall Clock Tree.

According to one embodiment of present invention, the clock node by domain in described steps A is divided into several bottom clock nodes bunch, be according to the first clock node information and the first complaint message, utilize balance two partitioning algorithms of OBB with obstacle to carry out L recurrence and divide and to obtain, recurrence number of times

Wherein, N represents the number of clock node in domain, c _irepresent the electric capacity of i clock node, D represents the manhatton distance of domain middle distance two nodes farthest, α, β, C _bfor constant, α, β is used for regulating clock node electric capacity and walks line capacitance shared proportion in total capacitance is estimated, C _bthe expectation value of the total load of representative to bottom clock node bunch.

According to one embodiment of present invention, in described steps A, carry out bottom Clock Tree structure in described bottom clock node bunch inside, according to second clock nodal information and the second complaint message, utilize balance two partitioning algorithms of OBB with obstacle that described bottom clock node bunch is divided, utilize the delay of ODME with obstacle to merge insertion algorithm and complete Clock Tree coiling, generate bottom Clock Tree.

According to one embodiment of present invention, structure top layer Clock Tree in described step B, according to the 3rd clock node information and the 3rd complaint message, utilize balance two partitioning algorithms of OBB with obstacle that described top layer clock node is divided, utilize the delay of ODME with obstacle to merge insertion algorithm and complete Clock Tree coiling, determine top layer Clock Tree cabling.

According to one embodiment of present invention, when the output signal of described the first impact damper arrives clock node, the upset speed of signal is less than the upset speed that overall Clock Tree requires.

According to one embodiment of present invention, in described overall Clock Tree, the first impact damper the arbitrary path from clock source to described clock node and the quantity of the second impact damper add up to even number.

According to a further aspect in the invention, also provide a kind of Clock Tree generation system based on clock node knot group, comprising:

Bottom Clock Tree constructing module, for the clock node of domain is divided into several bottom clock nodes bunch, carry out bottom Clock Tree structure in described bottom clock node bunch inside, insert the first impact damper at the root of bottom Clock Tree, drive described bottom clock node bunch;

Top layer Clock Tree constructing module, using the first all impact dampers as top layer clock node, structure top layer Clock Tree inserts several the second impact dampers, for driving top layer clock node on the cabling of top layer Clock Tree;

Entirety Clock Tree constructing module, for becoming overall Clock Tree take the first impact damper as tie point by bottom Clock Tree and the merging of top layer Clock Tree.

According to one embodiment of present invention, also comprise:

Global optimization module, by winding the line on cabling in described overall Clock Tree, changes track lengths, reduces the clock jitter of whole Clock Tree.

The present invention has brought following beneficial effect: by the clock node in domain is divided into several clock nodes bunch, each node cluster is driven by an impact damper, several clock nodes share an impact damper at bottom, and therefore the more common clock tree synthesis flow process of number of buffers is less.Meanwhile, the clock node cluster of bottom does not increase time delay because of clock node knot group.Then using all impact dampers as the comprehensive input node of clock network, carry out clock network structure and optimize, can effectively reduce the power consumption of clock network, and meet the switching rate of system requirements, clock jitter, the constraints such as time delay.

Other features and advantages of the present invention will be set forth in the following description, and partly from instructions, become apparent, or understand by implementing the present invention.Object of the present invention and other advantages can be realized and be obtained by specifically noted structure in instructions, claims and accompanying drawing.

Accompanying drawing explanation

Fig. 1 is according to the schematic flow sheet of the Clock Tree generation method based on clock node knot group of the embodiment of the present invention one;

Fig. 2 has shown the process flow diagram of selected impact damper in the embodiment of the present invention one;

Fig. 3 is an actual domain sample;

Fig. 4 is the structure result schematic diagram of the Clock Tree of sample shown in Fig. 3 under traditional clock tree synthesis flow process;

Fig. 5 utilizes the Clock Tree generation method based on clock node knot group of embodiment mono-sample of domain shown in Fig. 3 to be carried out to the structure result schematic diagram of Clock Tree after treatment;

Fig. 6 is the domain sample in embodiment bis-;

Fig. 7 is the result schematic diagram of constructing bottom Clock Tree in embodiment bis-;

Fig. 8 is the virtual schematic diagram of constructing top layer Clock Tree in embodiment bis-;

Fig. 9 is the result schematic diagram that generates overall Clock Tree in embodiment bis-;

Figure 10 is that in embodiment bis-, the Clock Tree after clock jitter optimization process generates result schematic diagram;

Figure 11 is the Clock Tree generation system schematic diagram based on clock node knot group according to the embodiment of the present invention three.

Embodiment

Describe embodiments of the present invention in detail below with reference to accompanying drawing, to the present invention, how application technology means solve technical matters whereby, and the implementation procedure of reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each feature in various embodiments of the present invention and each embodiment can mutually combine, and the technical scheme forming is all within protection scope of the present invention.

In addition, can in the computer system such as one group of computer executable instructions, carry out in the step shown in the process flow diagram of accompanying drawing, and, although there is shown logical order in flow process, but in some cases, can carry out shown or described step with the order being different from herein.

embodiment mono-

Fig. 1 is according to the schematic flow sheet of the Clock Tree generation method based on clock node knot group of the embodiment of the present invention one, describes each step of the present embodiment below with reference to Fig. 1 in detail.

Steps A, is divided into several bottom clock nodes bunch by the clock node in domain, carries out bottom Clock Tree structure in described bottom clock node bunch inside, inserts the first impact damper at the root of described bottom Clock Tree, for driving described bottom clock node bunch;

Particularly, comprise following sub-step:

Steps A 1, is divided into several bottom clock nodes bunch by the clock node in domain;

Comprise:

Steps A 11, determines the first clock node information and the first complaint message in domain;

Read in layout information, the clock node data in domain are deposited in the data structure of setting, form the first clock node information, this data structure comprises the two-dimensional coordinate of clock node, capacitance; The data of obstacle in domain are deposited in the data structure of setting, form the first complaint message, this data structure comprises the two-dimensional coordinate of obstacle, length and width;

Steps A 12, according to the first clock node information and the first complaint message, utilizing OBB(Obstacle-aware Balanced Bipartition) balance two partitioning algorithms with obstacle carry out L recurrence to clock node and divide, and the clock node in domain is divided into several bottom clock nodes bunch; The object of this algorithm is, carries out the division of bottom clock node bunch, to guarantee that the clock cabling generating can cut-through in the situation that considering obstacle in domain.

Preferably, in OBB algorithm, the number of times L of recurrence is calculated by following formula:

Wherein, N represents the number of clock node in domain, c _irepresent the electric capacity of i clock node, D represents the manhatton distance of domain middle distance two nodes farthest, α, β, C _bfor constant.α, β is used for regulating clock node electric capacity and walks line capacitance shared proportion in total capacitance is estimated.C _bthe expectation value of the total load of representative to bottom clock node bunch.

be used for estimating clock node in bottom clock node bunch and the total capacitance of cabling.

represent the expectation value to bottom clock node number of clusters amount, because OBB algorithm is two partition process, the expectation value that the number of times L of recurrence is this quantity is got 2 logarithm.

Steps A 2, carries out bottom Clock Tree structure in bottom clock node bunch inside;

Particularly, comprise following sub-step:

Steps A 21, determines bottom clock node bunch inner second clock nodal information and the second complaint message.

Preferably, read in bottom clock node bunch information, the clock node data in bottom clock node bunch are deposited in the data structure of setting, form second clock nodal information, this data structure comprises the two-dimensional coordinate of clock node, capacitance; Obstacle data in bottom clock node bunch are deposited in the data structure of setting, form the second complaint message, this data structure comprises the two-dimensional coordinate of obstacle, length and width.

Steps A 22, according to second clock nodal information and the second complaint message, utilizes OBB algorithm that the clock node in described bottom clock node bunch is divided, until clock node is divided into individual node.

Steps A 23, according to second clock nodal information and the second complaint message, utilizing ODME(obstacle-aware Deferred-Merge Embedding) delay with obstacle merges insertion algorithm and completes Clock Tree coiling, determines the cabling of bottom Clock Tree, generates bottom Clock Tree.So far, before not inserting bottom local buffer, generate the bottom Clock Tree of a zero-deviation.

Steps A 3, inserts the first impact damper at the root of bottom Clock Tree, for driving described bottom clock node bunch;

Be illustrated in figure 2 the process flow diagram of selecting impact damper in this step according to driving force, particularly, select the first impact damper by following sub-step:

Steps A 31, sorts impact damper from small to large according to driving force.

Steps A 32, the decay of the upset speed of calculating clock signal on cabling.

The decay Sl (e) of the upset speed of calculating clock signal by following formula on cabling,

Sl(e)=ln9·r·(0.5·c+c _load) （2）

Wherein, r represents the resistance of the cabling of impact damper driving, and c represents the electric capacity of cabling, c _loadrepresent the load capacitance that cabling drives.

Steps A 33, utilizes look-up table to search successively the upset speed of the output signal of impact damper.Preferably, obtain the upset rate lookup table of the output signal of impact damper by NGSPICE circuit simulation.

Steps A 34, the signal upset speed while calculating signal arrival clock node.

Signal upset speed Sl (r) when calculating signal and reach clock node by following formula,

$\mathrm{Sl}\left(r\right)=\sqrt{{\mathrm{Sl}\left(b\right)}^2+{\mathrm{Sl}\left(e\right)}^2}---\left(3\right)$

Wherein, Sl (b) represents the signal upset speed of impact damper output, the decay of the upset speed of Sl (e) expression signal on cabling.

Steps A 35, judges whether the upset speed of signal when signal arrives clock node is greater than the upset speed that overall Clock Tree requires,

If so, repeating step A33～A35;

If not, carry out steps A 36;

Steps A 36, chooses the impact damper that the meets overall Clock Tree requirement local buffer as this clock node bunch, referred to herein as the first impact damper.

By above-mentioned steps, the clock node in domain is divided into several bottom clock nodes bunch, in each bottom clock node bunch, complete bottom Clock Tree structure, and insert the first impact damper at the root of bottom Clock Tree, for driving bottom clock node bunch.After this step, also need following steps to complete the structure of whole Clock Tree structure.

Step B, using the first all impact dampers as top layer clock node, structure top layer Clock Tree inserts several the second impact dampers, for driving top layer clock node on the cabling of top layer Clock Tree;

Particularly, comprise following sub-step:

Step B1, determines the 3rd clock node information and the 3rd complaint message of top layer clock node;

Electric capacity using the input capacitance of all the first impact dampers as top layer clock node, the two-dimensional coordinate using the two-dimensional coordinate of all the first impact dampers as top layer clock node.

Top layer clock node data are deposited in the data structure of setting, form the 3rd clock node information, this data structure comprises top layer clock node, i.e. the two-dimensional coordinate of the first impact damper, capacitance; Obstacle data in domain are deposited in the data structure of setting, form the 3rd complaint message, this data structure comprises the two-dimensional coordinate of obstacle in domain, length and width.

Step B2, according to the 3rd clock node information and the 3rd complaint message, utilizes OBB algorithm to divide top layer clock node, until be divided into single clock node;

Step B3, utilizes ODME algorithm to complete Clock Tree coiling, determines top layer clock cabling, generates top layer Clock Tree.

Step B4 inserts several the second impact dampers on the cabling of top layer Clock Tree, for driving top layer Clock Tree, and meets the signal upset speed of system requirements and the requirement of signal polarity.

First determine the position candidate of the second impact damper.In the present embodiment, the position candidate of the second impact damper is equally distributed on every limit of binary tree.The limit that is L for a length, the second number of buffers N that can insert on this edge is

wherein m represents the drivable track lengths of driving force impact damper placed in the middle;

Therefore, on this edge, the spacing d of the second impact damper is

d=L/(N+1)。

Because the length on every limit is all not quite similar in binary tree, so the spacing d of the second impact damper is not a fixing value.

Then, select impact damper according to driving force, to meet the requirement of clock signal upset speed.

Particularly, according to the step shown in Fig. 2, to steps A 36, select respectively the impact damper that need to insert according to steps A 31 in each position candidate.

Meanwhile, in order to meet the requirement of signal polarity, then the first impact damper the path of clock node and the quantity summation of the second impact damper are even number from clock source point need to guarantee every.

Step C, take the first impact damper as tie point, becomes overall Clock Tree by bottom Clock Tree and the merging of top layer Clock Tree.

By above step, obtain complete Clock Tree, but because impact damper itself can cause time delay, so the deviation of overall clock is not also optimum.

Preferably, also need following steps to optimize the deviation of overall Clock Tree:

Step D, by winding the line on some path from clock source to clock node in overall Clock Tree, changes the length of cabling, reduces the clock jitter of overall Clock Tree.

In the present embodiment, by NGSPICE breadboardin simulation software, overall Clock Tree is carried out to simulation calculation, obtain after clock jitter result, calculating the length that every limit should wind the line accurately, finely tune.

Preferably, only in the cabling of top layer Clock Tree, wind the line, change the length of cabling in Clock Tree, finely tune overall Clock Tree deviation, obtain optimum Clock Tree result.

Fig. 5 utilizes the clock tree synthesis method based on clock node knot group of the present embodiment to carry out Clock Tree structure result schematic diagram after treatment to the sample of domain shown in Fig. 3, by Fig. 5 and Fig. 4 comparison, can find out, in clock network in Fig. 5, comprise less impact damper, therefore there is lower power consumption, and meet equally the signal upset speed of system requirements, clock jitter, the constraints such as time delay.

In sum, the present invention is by being divided into several clock nodes bunch by the clock node in domain, each node cluster is driven by an impact damper, and several clock nodes share an impact damper at bottom, and therefore the more common clock tree synthesis flow process of number of buffers is less.Meanwhile, the clock node cluster of bottom does not increase time delay because of clock node knot group.Then using all impact dampers as the comprehensive input node of clock network, carry out clock network structure and optimize, can effectively reduce the power consumption of clock network, and meet the switching rate of system requirements, clock jitter, the constraints such as time delay.

embodiment bis-

Below embodiment bis-is described, further understand the feature of the embodiment of the present invention.

Domain sample as shown in Figure 6, this domain comprises 16 clock nodes.By the clock node knot group method of utilizing embodiment mono-, these 16 clock nodes are reasonably divided, and constructed the Clock Tree structure of a high-performance low-power-consumption.

First, utilize OBB algorithm to be divided into 4 clock nodes bunch the clock node in domain, as bottom clock node bunch, then in bottom clock node bunch inside, utilize OBB algorithm and ODME algorithm to carry out bottom Clock Tree structure, be finally that each bottom clock node bunch distributes first impact damper, insert this first impact damper at bottom Clock Tree root.Result as shown in Figure 7.Because only insert an impact damper in bottom Clock Tree, can guarantee the negligible amounts in overall Clock Tree.

Then, carry out top layer Clock Tree structure, be illustrated in figure 8 the virtual schematic diagram of structure top layer Clock Tree.Top layer Clock Tree shown in figure is still among domain, and the first impact damper 801 and the first impact damper 801 ' are same impact damper, using the first impact damper 801 ' as top layer clock node.Same, the first impact damper 802 and the first impact damper 802 ' they are same impact damper, and the first impact damper 803 and the first impact damper 803 ' they are same impact damper, and the first impact damper 804 and the first impact damper 804 ' they are same impact damper; By first impact damper 802 ', the first impact damper the 803 ', the first impact damper 804 ' as top layer clock node.Utilize OBB algorithm and ODME algorithm, generate a top layer Clock Tree, for top layer Clock Tree distributes the second impact damper, in the cabling of top layer Clock Tree, insert several the second impact dampers.

Finally, take the first impact damper as tie point, bottom Clock Tree is connected with top layer Clock Tree, generates overall Clock Tree, as shown in Figure 9.

Preferably, by winding the line on two paths, change the length of cabling in overall Clock Tree, reduce the clock jitter of whole Clock Tree, obtain optimum Clock Tree result, as shown in figure 10.

embodiment tri-

Figure 11 is the Clock Tree generation system schematic diagram based on clock node knot group according to the embodiment of the present invention three.

Clock Tree generation system 110 based on clock node knot group comprises bottom Clock Tree constructing module 1101, top layer Clock Tree constructing module 1102, and overall Clock Tree constructing module 1103, preferably, also comprises global optimization module 1104.

Bottom Clock Tree constructing module 1101 is for being divided into the clock node of domain several bottom clock nodes bunch, carry out bottom Clock Tree structure in bottom clock node bunch inside, insert the first impact damper at the root of bottom Clock Tree, drive bottom clock node bunch.The information of bottom Clock Tree information, the first impact damper is passed to top layer Clock Tree constructing module 1102 and overall Clock Tree constructing module 1103 by bottom Clock Tree constructing module 1101.

Top layer Clock Tree constructing module 1102 is using the first all impact dampers as top layer clock node, and structure top layer Clock Tree inserts several the second impact dampers, for driving top layer clock node on the cabling of top layer Clock Tree.And top layer Clock Tree information and the second buffer information are passed to overall Clock Tree constructing module 1103.

Entirety Clock Tree constructing module 1103, take the first impact damper as tie point, becomes overall Clock Tree by bottom Clock Tree and the merging of top layer Clock Tree.

Preferably, global optimization module 1104, by winding the line on cabling in described overall Clock Tree, changes track lengths, falls the clock jitter of whole Clock Tree.

Bottom Clock Tree constructing module 1101, top layer Clock Tree constructing module 1102, overall Clock Tree constructing module 1103, global optimization module 1104 is carried out respectively the steps A in embodiment mono-, step B, step C, the operation of step D, launches explanation no longer in detail at this.

Those skilled in the art should be understood that, above-mentioned of the present invention each module or step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on the network that multiple calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in memory storage and be carried out by calculation element, or they are made into respectively to each integrated circuit modules, or the multiple modules in them or step are made into single integrated circuit module realize.Like this, the present invention is not restricted to any specific hardware and software combination.

Although the disclosed embodiment of the present invention as above, the embodiment that described content just adopts for the ease of understanding the present invention, not in order to limit the present invention.Technician in any the technical field of the invention; do not departing under the prerequisite of the disclosed spirit and scope of the present invention; can do any modification and variation what implement in form and in details; but scope of patent protection of the present invention, still must be as the criterion with the scope that appending claims was defined.

Claims (9)

1. the Clock Tree generation method based on clock node knot group, is characterized in that, comprises the following steps:

Steps A, is divided into several bottom clock nodes bunch by the clock node in domain, carries out bottom Clock Tree structure in described bottom clock node bunch inside, inserts the first impact damper at the root of described bottom Clock Tree, for driving described bottom clock node bunch;

Step B, using the first all impact dampers as top layer clock node, structure top layer Clock Tree inserts several the second impact dampers, for driving described top layer clock node on the cabling of described top layer Clock Tree;

Step C, take described the first impact damper as tie point, becomes overall Clock Tree by bottom Clock Tree and the merging of top layer Clock Tree.

2. the method for claim 1, is characterized in that, also comprises step D, by winding the line on cabling in described overall Clock Tree, changes track lengths, reduces the clock jitter of overall Clock Tree.

3. method as claimed in claim 1 or 2, it is characterized in that, the clock node by domain in described steps A is divided into several bottom clock nodes bunch, according to the first clock node information and the first complaint message, utilizing balance two partitioning algorithms of OBB with obstacle to carry out L recurrence divides and to obtain, recurrence number of times

Wherein, N represents the number of clock node in domain, c _irepresent the electric capacity of i clock node, D represents the manhatton distance of domain middle distance two nodes farthest, α, β, C _bfor constant, α, β is used for regulating clock node electric capacity and walks line capacitance shared proportion in total capacitance is estimated, C _bthe expectation value of the total load of representative to bottom clock node bunch.

4. method as claimed in claim 3, it is characterized in that, in described steps A, carry out bottom Clock Tree structure in described bottom clock node bunch inside, according to second clock nodal information and the second complaint message, utilize balance two partitioning algorithms of OBB with obstacle that described bottom clock node bunch is divided, utilize the delay of ODME with obstacle to merge insertion algorithm and complete Clock Tree coiling, generate bottom Clock Tree.

5. method as claimed in claim 4, it is characterized in that, structure top layer Clock Tree in described step B, according to the 3rd clock node information and the 3rd complaint message, utilize balance two partitioning algorithms of OBB with obstacle that described top layer clock node is divided, utilize the delay of ODME with obstacle to merge insertion algorithm and complete Clock Tree coiling, determine top layer Clock Tree cabling.

6. method as claimed in claim 5, is characterized in that, when the output signal of described the first impact damper arrives clock node, the upset speed of signal is less than the upset speed that overall Clock Tree requires.

7. method as claimed in claim 6, is characterized in that, the first impact damper the arbitrary path from clock source to described clock node in described overall Clock Tree and the quantity of the second impact damper add up to even number.

8. the Clock Tree generation system based on clock node knot group, is characterized in that, comprising:

Bottom Clock Tree constructing module, for the clock node of domain is divided into several bottom clock nodes bunch, carry out bottom Clock Tree structure in described bottom clock node bunch inside, insert the first impact damper at the root of bottom Clock Tree, drive described bottom clock node bunch;

Top layer Clock Tree constructing module, using the first all impact dampers as top layer clock node, structure top layer Clock Tree inserts several the second impact dampers, for driving top layer clock node on the cabling of top layer Clock Tree;

Entirety Clock Tree constructing module, for becoming overall Clock Tree take the first impact damper as tie point by bottom Clock Tree and the merging of top layer Clock Tree.

9. system as claimed in claim 8, is characterized in that, also comprises:

Global optimization module, by winding the line on cabling in described overall Clock Tree, changes track lengths, reduces the clock jitter of whole Clock Tree.

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