CN107944073A - A kind of ring for multichannel time measurement shakes integrated circuit - Google Patents
A kind of ring for multichannel time measurement shakes integrated circuit Download PDFInfo
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- CN107944073A CN107944073A CN201710948205.6A CN201710948205A CN107944073A CN 107944073 A CN107944073 A CN 107944073A CN 201710948205 A CN201710948205 A CN 201710948205A CN 107944073 A CN107944073 A CN 107944073A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
Shake integrated circuit the invention discloses a kind of ring for multichannel time measurement, ring shake unit along domain coordinate system laterally be divided to up and down two rows arrange, the shake delay circuit of unit of lastrow ring is located at ring and shakes the bottom of unit, connected along domain coordinate system transverse axis positive direction concatenated in order, the shake delay circuit of unit of next line ring is located at ring and shakes the top of unit, connected along domain coordinate system transverse axis negative direction concatenated in order, all rings shake unit delay circuit form an end to end delay chain, the signal delay time that two neighboring ring shakes between cell delay circuit is equal, externally input measured signal start is transmitted in ring delay chain, the ring unit parallel acquisition ring under the driving of sampling control signal that shakes shakes the state of cell delay circuit output end, realize the multichannel time measurement to same signal.This annular oscillation circuit can improve the linearity of measurement result, reduces measurement error and improve chip area utilization rate.
Description
Technical field
Shake integrated circuit the present invention relates to a kind of ring for multichannel time measurement, can be used for high resolution time survey
During the layout design for measuring integrated circuits, belong to IC design technical field.
Background technology
Time as a fundamental physical quantity, in space exploration, high-energy physics, remote sensing remote measurement and flow, the survey of distance
Amount etc. suffers from extremely important effect.Time measurement refers to measure a period, that is, to complete from opening
Time interval measurement between beginning signal start to end signal stop.High precision time measurement is realized by electronic circuit
Method has a variety of, and relatively common method is tapped delay collimation method at present.
The principle of tapped delay collimation method is measured commencing signal is transmitted by delay line, passes through tap signal
The position that it is delivered within the measured period is detected, so as to obtain the result of time measurement.Signal between adjacent taps
Time delay is exactly the minimum resolution measured.When realizing in circuit, delay line is formed generally by delay circuit, is surveyed
The resolution ratio of amount is exactly the time delay of these units.In integrated circuits, the circuit unit of generally use is basic gate circuit,
Such as phase inverter, NAND gate.
A kind of basic tapped delay collimation method time measuring circuit is as shown in Figure 1.Stopping letter being used wherein at tap
Number stop samples the commencing signal start by delay line transmission, and according to sampled result Q0~Qn, (thermometer type is compiled
Code) it is assured that the position that start signals are delivered to by the tested period, thus with reference to the delay time T of each unit
Tested time interval can be calculated.The range of tapped delay collimation method by delay line length (the deferred telegram way included
Amount) determine.This structure is to form the basis of many time measuring circuits, different by that can be formed from other technologies combination
Circuit form.
Many situations also need to measure the time interval of multiple passages at the same time in measurement process, that is, open same
Beginning signal start may correspond to different termination signal stop sources, these different termination signals constitute different passages.
Since the sampling process between different passages is independent, it is therefore desirable to set independent sample logic (to adopt in different passages
Sample circuit), and using different termination (sampling) signal such as stop1, stop2 etc., corresponding sample circuit is controlled respectively.More
Tapped delay part can share in channel time measurement, it is not necessary to change with the change of number of channels.These sample circuits
With delay circuit together, every grade of delay-sample logic is formed.
The range of simple tapped delay collimation method is to be determined by the time delay of wherein delay circuit with element number, is led to
Cross this mode needs many delay circuits when realizing the measurement of larger range, causes hardware spending larger.In order to by compared with
Few hardware resource reaches larger quantities journey, and when realizing, delay line therein would generally construct cyclization and shake (ring oscillator)
Form.
When IC design is realized, for the time measuring circuit of simple tapped delay-line, its laying out pattern
It can be considered with sequence arrangement without excessive.But when the end to end composition ring of delay line is shaken to realize reduction hardware spending,
, may be to the accuracy of measurement result and linear since the head and the tail processing of its loop structure may destroy original linear structure
Degree has an impact.
If ring shakes according to linear layout, signal is fed back to ring by line again when finally terminating shakes beginning
Position, can make end to end line produce very big wire delay, the linearity of measurement result be influenced, particularly in deep-submicron
In integrated circuit technology, wire delay occupies the proportion of bigger compared to gate delay, it is necessary to considers that wire delay shakes ring the influence of design.
If by the laying out pattern that ring shakes also arranging to circularize in design, it can preferably ensure that ring shakes the linear of result
Degree, but annular center and annular, outer all can have many chip areas not utilize, and cause chip area to waste, and increase realization
Cost.
The content of the invention
The technology of the present invention solves the problems, such as：Overcome the deficiencies of the prior art and provide one kind and be used for multichannel time measurement
Ring shake integrated circuit, improving the linearity of measurement result, reducing measurement error and improving chip area utilization rate.
The present invention technical solution be：A kind of ring for multichannel time measurement shakes integrated circuit, including 2N-1
A ring shakes unit, and N is the integer more than 1, and each ring unit that shakes includes 1 delay circuit and M sample circuit, and ring shakes unit edge
Domain coordinate system laterally be divided to up and down two rows arrange, the two row rings unit that shakes is put with the central axis mirror image switch parallel to X direction
Put, the shake delay circuit of unit of lastrow ring is located at ring and shakes the bottom of unit, along domain coordinate system transverse axis positive direction order levels
Connection connection；The shake delay circuit of unit of next line ring is located at ring and shakes the top of unit, suitable along domain coordinate system transverse axis negative direction
Sequence cascade Connection.Lastrow and the ring at next line both ends the cell delay circuit that shakes are connected by turning spur, and 2N-1 ring shakes list
The delay circuit of member forms an end to end ring oscillator, and the signal that two neighboring ring shakes between cell delay circuit prolongs
The slow time is equal.Externally input measured signal start is transmitted in ring delay chain, and each ring shakes M sampling in unit
Circuit parallel acquisition ring under externally input mutually independent sampling control signal driving shakes cell delay circuit output end
State, realize the multichannel time measurement to same signal.
The delay circuit is using the realization of two input nand gates, externally input measured signal start connections annular oscillation circuit
In any ring shake unit two input nand gates an input terminal, shake starting point as ring, the ring shake unit two inputs with it is non-
Another input terminal connection prime ring of door shakes the output terminal of two input nand gate of unit, other rings shake unit two inputs with it is non-
One input terminal of door is fixed and connects high level, another input terminal connection ring is shaken the output terminal of two input nand gate of prime.
The sample circuit realized using d type flip flop, the data input pin of the D input terminals of d type flip flop as sample circuit,
The output terminal of connection delay circuit；The input end of clock connection sampling control signal of d type flip flop, in the control of sampling control signal
The input signal of lower collection d type flip flop is to output terminal Q, the output as sample circuit.
Each ring shake 1 delay circuit inside unit and M sample circuit it is wide, and along the domain coordinate system longitudinal axis
Direction is alignd, and two neighboring sample circuit is placed in the same direction.
Each ring shake 1 delay circuit inside unit and M sample circuit it is wide, and along the domain coordinate system longitudinal axis
Direction is alignd, and two neighboring sample circuit is with parallel to the placement of the center line mirror image of coordinate system transverse axis.
The externally input sampling control signal to each ring shake the corresponding sample circuit of unit sampling control signal it is defeated
Enter end cabling in the way of balanced tree so that the externally input sampling control signal to 2N-1 ring shakes the corresponding of unit
The time delay of sample circuit control signal input is identical.
Each ring shake cell delay circuit output end to M sample circuit data input pin according to balanced tree side
Formula cabling so that each ring delay circuit output terminal in unit that shakes walks wire delay phase to the data input pin of M sample circuit
Together.
Compared with the prior art, the invention has the advantages that：
(1), ring of the invention shakes, and two rows are distributed unit in longitudinal direction mirror image up and down, and ring delay chain concentrates on whole ring
Shake the center of circuit layout, does not have other interference between delay chain, when can obtain smaller and uniform signal delay
Between, improve time resolution；
(2), whole annular oscillation circuit domain of the invention uses rectangular layout, the design that ring shakes is being ensured the linearity and standard
Area is as compact as possible on the premise of true property, and easy to the layout in chip global design below and wiring.
(3), ring of the invention shake inside unit two neighboring sample circuit in layout design with parallel to X direction
Axis mirror image switch is placed up and down, save chip area, the cabling total length of sampled signal can also be reduced；
(4), each sampling control signal of the present invention is adopted using balanced tree mode into walking line so as to reach each ring unit that shakes
The time of sample control input signaling point is identical, ensure that each ring shakes the uniformity of unit measurement result and the line of final time measurement
Property degree；
(5), ring of the present invention shake unit internal delay circuit be output to sample circuit input by the way of balanced tree
Into walking line, ensure each ring shake cell delay signal the time being output to up to the input terminal of each sample circuit it is identical, i.e., it is each logical
The uniformity of measurement result between road.
Brief description of the drawings
Fig. 1 is basic tapped delay collimation method time measuring circuit structure；
Fig. 2 is annular oscillation circuit integral layout figure of the embodiment of the present invention；
Fig. 3 shakes element circuit figure for single channel ring of the embodiment of the present invention；
Fig. 4 (a) shakes element circuit figure for binary channels ring of the embodiment of the present invention (adjacent sampling units are not overturn)；
Fig. 4 (b) shakes element circuit figure (adjacent sampling units upset) for binary channels ring of the embodiment of the present invention；
Fig. 5 (a) shakes element circuit figure for 3 passage ring of the embodiment of the present invention (adjacent sampling units are not overturn)；
Fig. 5 (b) shakes element circuit figure (adjacent sampling units upset) for 3 passage ring of the embodiment of the present invention；
Fig. 6 (a) is sampling control signal of embodiment of the present invention wiring diagram (using the situation of single driving)；
Fig. 6 (b) is sampling control signal of embodiment of the present invention wiring diagram (using situation about driving step by step)；
Fig. 7 shakes the complete domain of unit (binary channels) for ring of the embodiment of the present invention；
Fig. 8 shakes complete domain (binary channels) for ring of the embodiment of the present invention；
Fig. 9 is the post-layout simulation results exhibit of annular oscillation circuit domain delay distortion of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
The layout design of annular oscillation circuit need to ensure the time delay of units at different levels, the sampling time it is uniform, consistent and accurate
Really, to reduce the factor such as non-linear that design introduces, there is provided accurately and reliably measurement result as far as possible.This shakes ring itself with prolonging
Late, the design of sampling section proposes very high requirement.Rationally carry out ring shake layout design to improve measurement result the linearity,
Reduction measurement error and raising chip area utilization rate play the role of important.
Shake integrated circuit the present invention provides a kind of ring for multichannel time measurement.The layout design that ring shakes uses square
Shape is laid out.One direction sequence arrangement ring shakes unit, on another direction ring shake unit internal arrangement wherein delay circuit with
Sample circuit.For convenience's sake, ring is arranged to shake unit, y direction with domain coordinate system X direction in our design
The mode of arranging unit internal circuit (delay and sample circuit) illustrates.For using opposite arrangement, the i.e. longitudinal axis
The mode of direction arranging unit, X direction arranging unit internal circuit (delay and sample circuit), its principle is completely the same
, repeat no more.
As shown in Figure 2.The annular oscillation circuit shakes unit including 2N-1 ring, and N is the integer more than 1, and each ring shakes unit bag
Containing 1 delay circuit and M sample circuit, ring shake unit laterally be divided to along domain coordinate system up and down two rows arrange, a line includes N
A, another row includes N-1, and the lastrow ring unit that shakes shakes unit with the central axis parallel to X direction with next line ring
Lower mirror image switch is placed, and the shake delay circuit of unit of lastrow ring be located at ring and shakes the bottom of unit, along coordinate system transverse axis pros
Connected to concatenated in order, the shake delay circuit of unit of next line ring is located at ring and shakes the top of unit, along coordinate system transverse axis losing side
Connected to concatenated in order, as shown in Fig. 2, lastrow ring center of percussion signal transfer direction is from left to right, next line ring center of percussion signal
Direction of transfer is from right to left.Lastrow and the ring at next line both ends the cell delay circuit that shakes are connected by turning spur, 2N-1
The shake delay circuit of unit of a ring forms an end to end delay chain (ring oscillator), and two neighboring ring shakes cell delay
Signal delay time between circuit is equal, and externally input measured signal start is transmitted in ring delay chain, and each ring shakes
Unit receives the externally input mutually independent sampling control signal in M roads (wherein M >=1), and the shake sample circuit of unit of M ring exists
The externally input mutually independent sampling control signal driving lower parallel acquisition ring shakes the state of cell delay circuit output end,
Realize the multichannel time measurement to same signal.
The shake annular oscillation circuit of unit composition of above-mentioned two row rings up and down forms rectangular layout, which can make ring shake domain
Design is as compact as possible on the premise of measurement result accuracy and the linearity is ensured, and easy in chip global design below
Layout and wiring.
Every grade of ring shake delay circuit and sample circuit in unit using be longitudinally arranged, horizontal wide design method, delay
Circuit arrangement is in the center for layout of shaking by near-ring, and ring shakes, and in the same direction or mirror image is distributed unit along the longitudinal direction, ring delay
Chain concentrates on the center of whole annular oscillation circuit.There is no the interference of All other routes between delay cell, can be in integrated circuit diagram
Same layer wiring, reduce retardation, improve time resolution.Sample circuit is arranged in the outside position for layout of shaking by near-ring
Put, the quantity for the sample circuit of multi-channel measurement only influences the height of every grade of unit, has no effect on ring and shakes delay circuit
Position and performance, portable and autgmentability are strong.
Delay circuit is used to transmit the signal of ring center of percussion, its export be used to measuring elapsed time in the tested period (
The delay circuit quantity exactly passed through).For startup and stopping that control ring is shaken, in the present embodiment, the delay circuit uses
Two input nand gates realize, in externally input measured signal start connections annular oscillation circuit any ring shake unit two inputs and
One input terminal of NOT gate, shakes starting point as ring, the ring shake unit two input nand gates another input terminal connection prime
Ring shakes the output terminal of two input nand gate of unit, and the shake input terminal of two input nand gates of unit of other rings is fixed and connects high electricity
Flat, another input terminal connection ring is shaken the output terminal of two input nand gate of prime.The delay circuit that every grade of ring shakes inside unit is defeated
Go out while for driving next stage delay circuit and being supplied to the sample circuit of this grade to be used to record measurement result.Delay circuit
Signal path is designed according to time delay consistent mode.Every grade of delay circuit structure is identical, and inline load is identical, to protect
Demonstrate,prove the consistent of signal delay time.The signal that two neighboring ring shakes between cell delay circuit is by controlling its cabling level and several
What shape makes signal equal by the time delay of cabling.Ring shake both ends turning spur design in, it is necessary to pass through integrated circuit
Different layers line complete signal connection.When the level and physical dimension that these lines use determine the delay of this part line
Between.Size in Butut by adjusting line makes these lines as short as possible and consistent, so that the delay of this part line
Time consistency.The delay of line between upper and lower two rows unit (unit of the acyclic rotating part that shakes) also according to rotating part line
Situation is adjusted, to ensure that still the line of rotating part, its time delay are all consistent between two row units above and below either.
For example, the line of rotating part is completed by the metal connecting line that 3 sections are M1 and M2 layers respectively, total plus compositions such as through holes prolongs
The slow time is t1.Line is completed by M1 layers of metal connecting line between the unit of order aligning part, its time delay is t2.When both
When differing, it is assumed that t2<T1, can be by extending the corresponding wire lengths of wherein less t2 so that t2=t1, final to realize
The time delay of times at different levels is identical.When using phase inverter or other kinds of delay circuit, Butut mode is identical.
Sample circuit measures the position of signal transmission at the end of the tested period by recording state that delay circuit exports
(namely measurement result) is put, can be realized with d type flip flop or similar edging trigger storage unit.Preferably,
In the present embodiment, the sample circuit is realized using d type flip flop, and the D input terminals of d type flip flop are inputted as the data of sample circuit
End, the output terminal of connection delay circuit；The input end of clock connection sampling control signal of d type flip flop, in sampling control signal
The input signal of the lower collection d type flip flop of control is to output terminal Q, the output as sample circuit.Sample circuit in multi-channel measurement
Quantity determine that such as single channel measurement is 1 sample circuit according to number of channels, two pass bands are 2 sampling electricity
Road, triple channel measurement are 3 sample circuits, and so on.
In layout design, each ring shake M sample circuit inside unit be designed to it is wide, and along domain coordinate system
Y direction aligns, and two neighboring sample circuit can have two kinds of disposing ways, and one kind is to place in the same direction, and another kind is with parallel
Placed in the center line mirror image switch of coordinate system transverse axis.Binary channels ring shake unit circuit diagram it is as shown in Figure 4.Wherein, Fig. 4 (a)
It is the situation that sample circuit is not overturn, Fig. 4 (b) is the situation of sample circuit upset.Triple channel ring shakes circuit diagram such as Fig. 5 of unit
It is shown.It is similar with binary channels, adjacent sample trigger can also by the way of being overturn along transverse axis close proximity to.Wherein Fig. 5
(a) it is situation that sample circuit is not overturn, Fig. 5 (b) is the situation of sample circuit upset.The situation of other multichannels is similar, can
To analogize, repeat no more.The domain of these delay circuits can be designed in a manner of completely by foregoing circuit figure.
In order to ensure postpones signal from source point (output of delay circuit) to terminal (data input pin of sample circuit)
Path delay is identical, each ring shake cell delay circuit output end to the data input pin of M sample circuit according to balance
The mode cabling of tree.
For single channel, due to there was only a sample circuit, so need not be specifically designed, only need a rings at different levels shake unit it
Between keep delay consistent.Single channel ring shake unit circuit diagram it is as shown in Figure 3.
Also to keep being output to each sample circuit input from delay circuit for multi-channel sampling, inside every grade of unit
Delay is consistent, and at this moment this signal is connected up using balance tree method.Sampled for binary channels, utilize balanced tree side
Method, respectively as shown in Fig. 4 (a) and Fig. 4 (b).As shown in Fig. 4 (a), when two d type flip flops are put in the same direction, delay letter
Number reach two D device input terminal midpoints when, be divided into the input terminal that Liang Ge branches are sent to d type flip flop.As shown in Fig. 4 (b), sampling
For trigger when by the way of being overturn along transverse axis, two d type flip flops can be close proximity to, can save chip area, can be with
Reduce the cabling total length of sampled signal.Sampled for triple channel, it is same using balance tree method, such as Fig. 5 (a) and Fig. 5 (b) institutes
Show.
Shake to ensure the externally input sampling control signal to 2N-1 ring the related circuit controlling of sampling of unit
The time delay of signal input part is identical, so that ensure the accuracy and uniformity of measurement result, the externally input sampling
Control signal to each ring shake unit corresponding sample circuit sampling control signal input terminal in the way of balanced tree cabling.
The balanced tree of sampling control signal is arranged in ring and shakes that (the namely ring unit that shakes is outer for the bottom and upper segment of rectangle domain
The part on side), do not influence whole ring while ensureing balanced and shake the layout and performance of domain.Illustrate sampling by taking single channel as an example
The balanced Butut mode of control signal.As shown in fig. 6, sampling control signal from 2N-1 ring shake unit composition rectangular area indulge
Simultaneously exceed wiring along the forward and reverse and longitudinal negative direction cabling in longitudinal direction, arrival transverse edge respectively to the point midway of either side edge
After the appropriate height needed, turn 90 degree, along rectangular area horizontal direction cabling, arrival ring shake rectangle horizontal midpoint it
Afterwards, 90 degree of turning becomes the vertical cabling to shake to ring, and the mode from this vertical cabling according still further to balanced tree is horizontal to rectangle respectively
The central point of next stage is reached to direction cabling, then turns 90 degree and becomes vertical cabling, so moves in circles, decomposes step by step, directly
To obtaining 2N-1 branch, 2N-1 branch is connected to 2N-1 ring and is shaken the sampling control signal of the corresponding sample circuit of unit
Untill input terminal.During sampled signal transmission is carried out, a big signal driver can be used, passes through sampling afterwards
Control signal balanced tree cabling, as shown in Fig. 6 (a).Or as needed in branch during sampling control signal transmits
It is upper to add driving, signal driver is combined together with balanced tree, the driving force of sampling control signal is improved, such as Fig. 6 (b)
It is shown.
For multichannel situation, design method is identical.These sampling control signals cabling and driver (if
Have) just it is arranged in ring and shakes the outside (ring shakes above domain rectangle and following) of unit, ring is not influenced to shake the layout and version of itself
Figure, while also ensure that the equilibrium of sampled signal.
Fig. 7 gives complete ring by taking a binary channels ring shakes unit as an example and shakes cell layout.Sample circuit therein is adopted
With the mode of upset, black portions are the Equilibrium routings of postpones signal.Fig. 8 gives the complete domain that a binary channels ring shakes
Example.The mode of single driving is employed in this example.Wherein black portions are the Equilibrium routings of sampling control signal.From
It can be seen from the figure that, layout design is compact, the area not wasted.Shown by design verification, the deviation between delays at different levels
Within ± 1%, the shake post-layout simulation results exhibit of domain delay distortion of ring is shown in attached drawing 9.
It is not described in detail in this specification and partly belongs to general knowledge well known to those skilled in the art.
Claims (7)
- The integrated circuit 1. a kind of ring for multichannel time measurement shakes, it is characterised in that：Shake unit including 2N-1 ring, N is Integer more than 1, each ring unit that shakes include 1 delay circuit and M sample circuit, and the ring unit that shakes is horizontal along domain coordinate system It is divided to two rows arrangement up and down, two row rings shake unit to be placed parallel to the central axis mirror image switch of X direction, and lastrow ring shakes The delay circuit of unit is located at ring and shakes the bottom of unit, is connected along domain coordinate system transverse axis positive direction concatenated in order；Next line The shake delay circuit of unit of ring is located at ring and shakes the top of unit, is connected along domain coordinate system transverse axis negative direction concatenated in order.On A line and the ring at next line both ends the cell delay circuit that shakes are connected by turning spur, and 2N-1 ring shakes the delay circuit structure of unit The ring oscillator end to end into one, the signal delay time that two neighboring ring shakes between cell delay circuit are equal.Outside The measured signal start of portion's input is transmitted in ring delay chain, and the M sample circuit that each ring shakes in unit is in external input The lower parallel acquisition ring of mutually independent sampling control signal driving shake the state of cell delay circuit output end, realize to same The multichannel time measurement of one signal.
- The integrated circuit 2. a kind of ring for multichannel time measurement according to claim 1 shakes, it is characterised in that：It is described Delay circuit realized using two input nand gates, and any ring shakes list in externally input measured signal start connections annular oscillation circuit One input terminal of two input nand gates of member, shakes starting point as ring, the ring shake unit two input nand gates another is defeated Enter end connection prime ring to shake the output terminal of two input nand gate of unit, other rings shake unit two input nand gates an input End fixation connects high level, another input terminal connection ring is shaken the output terminal of two input nand gate of prime.
- The integrated circuit 3. a kind of ring for multichannel time measurement according to claim 1 shakes, it is characterised in that：It is described Sample circuit realized using d type flip flop, the data input pin of the D input terminals of d type flip flop as sample circuit, connection delay circuit Output terminal；The input end of clock connection sampling control signal of d type flip flop, gathers D triggerings under the control of sampling control signal The input signal of device is to output terminal Q, the output as sample circuit.
- The integrated circuit 4. a kind of ring for multichannel time measurement according to claim 1 shakes, it is characterised in that：It is described Each ring shake 1 delay circuit inside unit and M sample circuit it is wide, and along the alignment of domain coordinate system y direction, phase Adjacent two sample circuits are placed in the same direction.
- The integrated circuit 5. a kind of ring for multichannel time measurement according to claim 1 shakes, it is characterised in that：It is described Each ring shake 1 delay circuit inside unit and M sample circuit it is wide, and along the alignment of domain coordinate system y direction, phase Adjacent two sample circuits are with parallel to the placement of the center line mirror image of coordinate system transverse axis.
- The integrated circuit 6. a kind of ring for multichannel time measurement according to claim 1 shakes, it is characterised in that：It is described Externally input sampling control signal to each ring shake the corresponding sample circuit of unit sampling control signal input terminal according to balance The mode cabling of tree so that the externally input sampling control signal to 2N-1 ring shake unit corresponding sample circuit control The time delay of signal input part is identical.
- The integrated circuit 7. a kind of ring for multichannel time measurement according to claim 1 shakes, it is characterised in that：It is described Each ring shake cell delay circuit output end to the data input pin of M sample circuit the cabling in the way of balanced tree so that Each ring shake delay circuit output terminal in unit to the data input pin of M sample circuit to walk wire delay identical.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111539176A (en) * | 2019-03-29 | 2020-08-14 | 成都海光集成电路设计有限公司 | Multi-instance time budget for integrated circuit design and fabrication |
| CN111723539A (en) * | 2020-05-14 | 2020-09-29 | 天津大学 | Design and manufacture of TDC chip with double time measuring modes |
| CN111983423A (en) * | 2020-07-28 | 2020-11-24 | 成都华微电子科技有限公司 | Chip routing time delay built-in detection circuit and detection method |
| CN114896936A (en) * | 2022-02-16 | 2022-08-12 | 上海先楫半导体科技有限公司 | Ring oscillator and layout wiring structure thereof |
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| CN111539176A (en) * | 2019-03-29 | 2020-08-14 | 成都海光集成电路设计有限公司 | Multi-instance time budget for integrated circuit design and fabrication |
| CN111723539A (en) * | 2020-05-14 | 2020-09-29 | 天津大学 | Design and manufacture of TDC chip with double time measuring modes |
| CN111723539B (en) * | 2020-05-14 | 2024-03-22 | 天津大学 | Design method of double time-measurement mode TDC chip |
| CN111983423A (en) * | 2020-07-28 | 2020-11-24 | 成都华微电子科技有限公司 | Chip routing time delay built-in detection circuit and detection method |
| CN111983423B (en) * | 2020-07-28 | 2023-08-29 | 成都华微电子科技股份有限公司 | Chip wiring delay built-in detection circuit and detection method |
| CN114896936A (en) * | 2022-02-16 | 2022-08-12 | 上海先楫半导体科技有限公司 | Ring oscillator and layout wiring structure thereof |
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