CN114759911A

CN114759911A - Low-kickback-noise comprehensive dynamic voltage comparator

Info

Publication number: CN114759911A
Application number: CN202210267490.6A
Authority: CN
Inventors: 程旭; 李敏; 曾晓洋
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2022-03-17
Filing date: 2022-03-17
Publication date: 2022-07-15

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a low kickback noise comprehensive dynamic voltage comparator. The synthesizable dynamic voltage comparator of the present invention includes a clock delay module, an input compare stage, and an output latch stage circuit. The dynamic voltage comparator operates in two phases: a reset phase and a compare phase. The reset phase simultaneously samples the input voltage and latches the comparison result, and the comparison phase amplifies the difference between the two input voltages to the potentials of logic 1 and logic 0. The dynamic voltage comparator is composed of digital standard units, is compatible with automatic process design, shortens circuit design time and facilitates process migration.

Description

Low-kickback-noise comprehensive dynamic voltage comparator

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a low-kickback-noise comprehensive dynamic voltage comparator circuit in an integrated circuit.

Background

Most of traditional Complementary Metal Oxide Semiconductor (CMOS) analog circuits are realized by MOS tubes with customized sizes, analog circuit layout design is completed through manual layout and wiring, and layout and design iteration time is long. When an analog circuit completed under a specific process CMOS process is transferred to other CMOS processes, the circuit needs to be built again and layout wiring is completed, and the traditional analog circuit is difficult to realize rapid transfer among the CMOS processes.

The analog circuit which can be synthesized is realized by a digital standard unit and can be automatically generated by a digital layout tool. The analog circuit capable of being integrated needs to use a digital standard unit to replace a CMOS transistor in the traditional analog circuit, and a digital circuit layout generation tool can be used for automatically laying out and wiring in the layout generation stage, so that the layout design speed is greatly improved. In addition, the difference of the digital standard units of each process is small, and the same type of units can be used for quickly replacing the original circuit during process migration, so that the rapid migration of the analog circuit among different processes is realized.

The voltage comparator is used for comparing the magnitude of two input voltages, the output value is logic 1 or logic 0, and the voltage comparator is an indispensable module in the successive approximation type analog-to-digital converter. Compared with a static comparator, the dynamic comparator has no static power consumption, and has higher speed due to positive feedback, so that the application range is wider. Meanwhile, compared with a static comparator, the dynamic comparator is easier to realize comprehensively. Kickback noise is one of the non-ideal factors that affect the performance of the comparator. Therefore, it is very attractive to design a synthesizable dynamic voltage comparator with low kickback noise.

Disclosure of Invention

The invention aims to solve the technical problem of providing a comprehensive dynamic voltage comparator which is short in circuit design time, convenient for process migration, low in kickback noise and completely built by a digital standard unit.

The invention provides a low-kickback noise comprehensive dynamic voltage comparator, which comprises a clock delay module, an input comparison stage circuit and an output latch stage circuit; the input port is a pair of positive and negative signal ports and a clock port; the output ports are a pair of complementary logic signal output ports; wherein:

(1) the clock delay module consists of a delay unit; the port of the delay unit comprises a signal input end and a signal output end; the signal input end of the delay unit is connected with the clock input, and the signal output end of the delay unit is connected with the delayed clock signal;

(2) the input comparison stage circuit consists of a pair of input units; the port of each input unit comprises four signal input ends and a signal output end; the first signal input end of the signal input units is respectively connected with the positive input end and the negative input end, the second signal input end is connected with the delayed clock signal, the fourth signal input end is connected with the input clock signal, and the third signal input end of one input unit is respectively connected with the signal output end of the other input unit; the signal output ends are respectively connected to the intermediate regeneration signals;

(3) the output latch stage circuit consists of a pair of inverters and a pair of NOR gates; the port of the NOR gate comprises two signal input ends and a signal output end; the signal input end of one NOR gate is respectively connected with the inverted signal of the intermediate regeneration signal through a pair of inverters, and the other signal input end of the NOR gate is respectively connected with the signal output end of the other NOR gate; the signal output ends are respectively connected to the latch output ports.

The invention provides a low-kickback noise comprehensive dynamic voltage comparator, wherein a pair of input units work in two modes under the control of an input clock signal: a reset mode and a compare mode; in the reset mode, a clock signal is input to reset the intermediate regeneration signal to a power supply voltage; in the comparison mode, the input comparison stage circuit has a positive feedback function, so that intermediate regeneration signals compete with each other and finally converge to logic 0 and logic 1 voltages respectively.

The invention provides a low kickback noise synthesizable dynamic voltage comparator, which is controlled by an input clock signal of an output latch stage circuit (namely an SR latch) to work in two modes: a latch mode and an update mode; in the latch mode, the intermediate regeneration signal is power voltage, and zero level (VSS) is obtained after phase inversion, so that the output signal is kept unchanged; when updating the mode, if S is high level and R is low level, the output signals are respectively low level and high level; on the contrary, if S is low level and R is high level, the output signal is high level and low level respectively.

The circuit of the low kickback noise comprehensive dynamic voltage comparator provided by the invention works in two phases;

(1) resetting the phase: resetting the clock to a turn-off level; the intermediate regeneration signal is reset to the supply voltage; the input signal is sampled at this time; the output latch stage circuit is in a latch mode, and the output signal keeps the original state;

(2) comparing phases: resetting the clock to a conducting level; the input comparison stage circuit is in a comparison mode, the intermediate regeneration signal starts to discharge at different speeds according to different magnitudes of the input signals, when one end of the intermediate regeneration signal discharges to enable the PMOS tube at the other end to be conducted, a positive feedback mechanism is triggered, and finally, the intermediate regeneration signal converges to different logic levels 0 or 1 respectively due to cross positive feedback.

The low kickback noise comprehensive dynamic voltage comparator provided by the invention comprises a clock delay module, an input comparison stage circuit and an output latch stage circuit which can be realized by a digital standard unit.

Drawings

FIG. 1 is a circuit diagram of a conventional NAND gate based synthesizable dynamic voltage comparator.

FIG. 2 is a block diagram of a low kickback noise synthesizable dynamic voltage comparator according to the present invention.

FIG. 3 is a gate level circuit diagram of an embodiment of a low kickback noise synthesizable dynamic voltage comparator according to the present invention.

FIG. 4 is a circuit diagram of a transistor level of a pair of input cells in an embodiment of a low kickback noise synthesizable dynamic voltage comparator of the present invention.

FIG. 5 is a circuit diagram of a transistor stage of two NOR gates in an output latch stage circuit of an embodiment of a low kickback noise synthesizable dynamic voltage comparator of the present invention.

FIG. 6 is a circuit diagram of a transistor level circuit of a clock delay module and an inverter in an embodiment of a low kickback noise synthesizable dynamic voltage comparator of the present invention.

Detailed Description

As shown in fig. 1, in the conventional nand-gate based synthesizable dynamic voltage comparator, VINP and VINN are input signals, and control input pair transistors MNA1_1, MNA1_2, MPA1_1 and MPA1_2 gate terminals; CLK is a comparison enable signal that controls the gate terminals of MNA3_1, MNA3_2, MPA3_1 and MPA3_ 2. When CLK is logic 0, MNA3_1 and MNA3_2 are off, MPA3_1 and MPA3_2 are on, and nodes POUT _ NAND3 and NOUT _ NAND3 are charged to the supply voltage, so that MNA2_1 and MNA2_2 are on. When the CLK is logic 1, the MNA3_1 and MNA3_2 are turned on, the MPA3_1 and MPA3_2 are turned off, and at this time, the nodes POUT _ NAND3 and NOUT _ NAND3 start to discharge at different speeds according to the difference between VINP and VINN, when POUT _ NAND3 falls to turn on the MPA2_2 or NOUT _ NAND3 falls to turn on the MPA1_2, the positive feedback structure composed of two end-to-end inverters MPA2_1, MNA2_1, MPA2_2 and MNA2_2 starts to operate, and finally, NOUT _ NAND3 converges to logic 1 and POUT _ NAND3 converges to logic 0 or vice versa. The result of this convergence is then latched by the SR latch, resulting in the final VOUTP and VOUTN.

Traditional nand-based synthesizable dynamic voltage comparators are precharged by PMOS and discharged by NMOS. However, the discharge node is located at the drain terminal of the input pair transistor, and the voltage variation of the node can be coupled to the input node through the gate-drain parasitic capacitance of the input pair transistor, so that the interference to the voltage of the input node is caused, and the interference is called kickback noise. The traditional MOS-based dynamic voltage comparator can reduce kickback noise by inserting an isolation tube between the drain end of an input geminate transistor and a regeneration node, but the integratable comparator is based on a standard unit and cannot be directly inserted into an MOS tube.

FIG. 2 is an inventive low kickback noise synthesizable dynamic voltage comparator. FIG. 3 is a circuit diagram of an example of a low kickback noise synthesizable dynamic voltage comparator according to the present invention. Comprises a clock delay module (100), an input comparison stage circuit (200) and an output latch stage circuit (300); the input ports are a pair of positive and negative signal ports (VINP and VINN) and a clock port (CLK); the output ports are a pair of complementary logic signal output ports (VOUTN and VOUTP).

(1) The clock delay module consists of a delay unit (100); the ports of the delay unit comprise a signal input end (IN) and a signal output end (OUT); the signal input of the delay unit is connected to the clock input (CLK) and the signal output is connected to the delayed clock signal (CLKD).

(2) The input comparison stage circuit (200) is composed of a pair of input units (210 and 220); the port of each input cell includes four signal inputs (a 1, a2, A3, and a 4) and one signal Output (OUT); in the pair of signal input units (112 and 120), a first signal input terminal (A1) is connected to positive and negative inputs (VINP and VINN), respectively, a second signal input terminal (A2) is connected to a delayed clock signal (CLKD), a fourth signal input terminal (A4) is connected to an input clock signal (CLK), and a third signal input terminal (A3) of one input unit is connected to a signal output terminal (NOUT or POUT) of the other input unit, respectively; the signal output terminals (OUT) are connected to the intermediate regenerative signals (POUT and NOUT), respectively.

(3) The output latch stage circuit (300) is composed of an SR latch (310); the ports of the SR latch include two signal inputs (S and R) and two signal outputs (Q and QN); two signal input terminals (S and R) are respectively connected with the intermediate regeneration signals (POUT and NOUT) after being inverted; the two signal outputs (Q and QN) are connected to the output ports (VOUTP and VOUTN) of the comparator, respectively.

FIG. 4 is a transistor level circuit for an example of a pair of input cells of a low kickback noise synthesizable dynamic voltage comparator for use in the present invention. The input comparison stage circuit works in two modes under the control of an input clock signal; in the reset mode, a clock signal is input to reset the intermediate regeneration signal to a power supply voltage; in the comparison mode, the input comparison stage circuit has a positive feedback function, so that intermediate regeneration signals compete with each other and finally converge to logic 0 and logic 1 voltages respectively.

Fig. 5 is a transistor stage circuit of two nor gate examples in an output latch stage applied to the dynamic voltage comparator of the present invention. The SR latch works in two modes; in the latch mode, the output signal keeps the original state; when the mode is updated, the output signal changes correspondingly along with the input change and is latched.

The circuit of the comprehensive dynamic voltage comparator works in two phases;

(1) resetting the phase: resetting the clock to a turn-off level; the intermediate regeneration signal is reset to the power supply voltage; the input signal is sampled at this time; the output latch stage circuit is in a latch mode, and the output signal keeps the original state;

Fig. 6 is an example circuit using a delay module and an inverter.

The above embodiments are merely illustrative of the technical concept and features of the present invention, and the clock delay module, the input comparing stage and the output latching stage can all be implemented by other circuit structures to achieve the same functions, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention accordingly, and not to limit the scope of the present invention. All modifications made according to the spirit of the main technical scheme of the invention are covered in the protection scope of the invention.

Claims

1. A low kickback noise synthesizable dynamic voltage comparator includes a clock delay block (100), an input comparator stage circuit (200) and an output latch stage circuit (300); the input ports are a pair of positive and negative signal ports (VINP and VINN) and a clock port (CLK); the output ports are a pair of complementary logic signal output ports (VOUTN and VOUTP); wherein:

(1) the clock delay module consists of a delay unit; the ports of the delay unit comprise a signal input end (IN) and a signal output end (OUT); the signal input end of the delay unit is connected with a clock input (CLK), and the signal output end of the delay unit is connected with a delayed clock signal (CLKD);

(2) the input comparison stage circuit (200) is composed of a pair of input units (210 and 220); the port of the input unit includes four signal input terminals (a 1, a2, A3 and a 4) and one signal output terminal (OUT); the pair of signal input units (210 and 220) has first signal input terminals (a 1) connected to positive and negative inputs (VINP and VINN), respectively, a second signal input terminal (a 2) connected to a delayed clock signal (CLKD), a fourth signal input terminal (a 4) connected to an input clock signal (CLK), and a third signal input terminal (A3) connected to a signal output terminal of another input unit, respectively; the signal output terminals (OUT) are connected to the intermediate regenerative signals (POUT and NOUT), respectively;

2. A low kickback noise synthesizable dynamic voltage comparator as claimed in claim 1 wherein a pair of input cells (210 and 220) operates in two modes under control of an input clock signal (CLK): a reset mode and a compare mode;

in a reset mode, an input clock signal (CLK) resets the intermediate regeneration signals (POUT and NOUT) to a power supply Voltage (VDD);

in the comparison mode, the input comparator stage circuit (200) exhibits a positive feedback function, and causes the intermediate regenerative signals (POUT and NOUT) to compete with each other and eventually converge to logic 1 and logic 0 voltages, respectively.

3. The low kickback noise synthesizable dynamic voltage comparator as claimed in claim 1, wherein the SR latch (310) operates in two modes under control of the input clock signal (CLK): a latch mode and an update mode;

in the latch mode, the intermediate regenerative signals (POUT and NOUT) are the power supply Voltage (VDD), and both are zero level (VSS) after inversion, so that the output signals (VOUTN and VOUTP) keep the original state;

in the refresh mode, if S is high and R is low, the output signals (VOUTN and VOUTP) are low and high, respectively, whereas if S is low and R is high, the output signals (VOUTN and VOUTP) are high and low, respectively.

4. The low kickback noise synthesizable dynamic voltage comparator as claimed in claim 1, wherein said dynamic voltage comparator operates in two phases: a reset phase and a compare phase;

when the phase is reset: resetting a Clock (CLK) to an OFF level; the intermediate regeneration signals (POUT and NOUT) are reset to the power supply Voltage (VDD); the input signals (VINP and VINN) are sampled at this time; the output latch stage circuit (300) is in a latch mode, and output signals (VOUTP and VOUTN) keep the original state unchanged;

when the phases are compared: resetting the Clock (CLK) to a conducting level; the input comparison stage circuit (200) is in a comparison mode, the intermediate regeneration signals (POUT and NOUT) start to discharge at different speeds according to the difference of the magnitudes of the input signals (VINP and VINN), when one end of the discharging speed discharges to enable the PMOS tube at the other end to be conducted, a positive feedback mechanism is triggered, and finally the positive feedback converges to different logic levels 0 or 1 respectively due to cross positive feedback.

5. The low kickback noise synthesizable dynamic voltage comparator according to claim 1, wherein the clock delay block (100), the input comparison stage circuit (200) and the output latch stage circuit (300) are all implemented by digital standard cells.