CN106067817B - 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter - Google Patents
1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter Download PDFInfo
- Publication number
- CN106067817B CN106067817B CN201610411806.9A CN201610411806A CN106067817B CN 106067817 B CN106067817 B CN 106067817B CN 201610411806 A CN201610411806 A CN 201610411806A CN 106067817 B CN106067817 B CN 106067817B
- Authority
- CN
- China
- Prior art keywords
- dynamic
- capacitor
- controllable
- comparator
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
- H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The invention belongs to technical field of integrated circuits, the gradual approaching A/D converter that 1.5 redundancy bits specially based on controllable asymmetric dynamic comparator accelerate.Analog-digital converter structure provided by the invention includes two identical boot-strapped switch, one group of symmetrical N binary capacitor array, two controllable asymmetric dynamic comparators, the Digital Logical Circuits module of common a dynamic comparer and SAR ADC.Present invention introduces 1.5 redundancy bits acceleration techniques, shorten former of waiting and establish the complete time, accelerate the conversion rate of analog-digital converter, increase redundancy, reduce error code, lose code, improve precision.Compared to traditional technology, circuit scale can significantly be simplified, especially omit generating circuit from reference voltage, then the power consumption and area of analog-digital converter are reduced, equivalent reference voltage value is established in variation rapidly, accelerate the conversion speed of analog-digital converter, and there is universality, can be applied to the application scenarios of other 0.5 bits.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of 1.5 based on controllable asymmetric dynamic comparator
Redundancy bits accelerate successive approximation digital analog converter.
Background technique
The technology of 1.5 bits is widely used in flow-line modulus converter, it is used increase redundancy come eliminate by
Precision of A/D converter caused by static offset error declines by a small margin.And 1.5 apply in Approach by inchmeal for the first time than trick
In type analog-to-digital converter or Chun-Cheng Liu and Soon-Jyh Chang in 2010 in super large-scale integration
Issued for the first time in meeting (Symposium on VLSI circuits), although at that time without propose 1.5 bits concept,
The redundancy approach wherein implemented is strictly the way of 1.5 bits.It is that Chun-Cheng Liu is delivered in the meeting shown in Fig. 1
First four are compared the 10MS/s of foundation, the structure of the gradual approaching A/D converter of 10bit top plate sampling using 1.5 bits
Schematic diagram.Fig. 1 mainly includes two boot-strapped switch 101, the climax with input signal and 10 binary capacitor arrays 102
Plate and node 103,104 connect；10 binary capacitor arrays 102, the top plate of capacitor array link together and dynamic ratio
Compared with the structure that device 105,106,107 is connected to node 103,104 and traditional top plate sampling gradual approaching A/D converter
It compares, first four of the capacitor array 102 of Fig. 1 are split into two parts of equivalent, and the steering of sole plate level is individually controlled；
Dynamic comparer 105,106,107, the dynamic comparer quantity of figure one is no longer one in traditional structure, and is extended to three
It is a, wherein 106,107 compare foundation for 1.5 bits；One six seat digital analog converter 108 is overturn by capacitor sole plate
The reference voltage that every grade of 1.5 bits compare foundation is generated, this partial circuit is that traditional Approach by inchmeal analog-digital converter does not have
's；SAR ADC application of logic circuit module 109, clock producing method, control level conversion direction and output code combinational logic and tradition
Gradual approaching A/D converter is also different.
Preceding four 1.5 bits of structure shown in Fig. 1 are turned by two dynamic comparers 106,107 and a six seat digital-to-analogues
What parallel operation was realized.Two dynamic comparers 106,107 connect the top plate and six seat digital-to-analogues of symmetrical 10 capacitor arrays respectively
Converter 108, i.e., the input terminal of two dynamic comparers 106,107 are separately connected node 103,110 and node 104,110.Six
Position sub-adc converter 108 generate reference voltage range be common-mode voltage half to common-mode voltage 16/
15, when two capacitor array top crown voltages are all higher than reference voltage, the low pole plate of the capacitance group of this is not overturn；When two
Capacitor array top crown voltage one be lower than reference voltage, one be higher than reference voltage when, the capacitance group sole plate earthing of high side,
The capacitance group sole plate of downside connects reference voltage.
The working method of foregoing circuit is as follows.When CK is high level, boot-strapped switch 101 is opened, input signal is adopted
On sample to the top plate of the binary capacitor array 102 of analog-digital converter, capacitance group C at this time1a~C4aSole plate earthing, remaining
Capacitance group (C1b~C4bAnd C5~C9) reference voltage is connect, dynamic comparer 105,106,107 is turned off, and analog-digital converter is in and adopts
The sample stage.When CK is low level, boot-strapped switch 101 is turned off, and capacitor array 102 is hanging, and the quantity of electric charge is constant, the failing edge moment
Input signal be just held on capacitor array 102, analog-digital converter is in quantization stage.The input signal of holding is distinguished
By two dynamic comparers 106,107 compared with reference voltage, the data of comparator are transferred to the application of logic circuit module of SAR ADC
In 109, combined logic generates logic control signal, controls first capacitance group C1aAnd C1bThe reverses direction of sole plate, through one
After the foundation of section time is complete, start the comparison of next 1.5 bit, until the 4th.After 4th bit comparison, dynamic ratio
It will be off compared with device 106,107 until next quantization period, the 4th foundation terminates, and dynamic comparer 105 is opened, and completes it
Six comparisons afterwards, until the tenth.Dynamic comparer 105,106,107 quantifies data out in the logic circuit of SAR ADC
Pass through the binary code that digital logical operation generates ten in module 109, is stored in register, in next external sampling
The rising edge of clock exports.
By foregoing teachings it is found that preceding four 1.5 bits of Chun-Cheng Liu building compare the 10MS/s of foundation,
The gradual approaching A/D converter main purpose of 10bit top plate sampling is to reduce overturning probability, since reduce power consumption, and it is fast
It does not raise speed on degree, the redundancy that can increase is also extremely limited.And the technique that the design uses is 0.18um CMOS work
Skill, unit capacitance values 5fF.And with technological development, the linearity of metal wire is more preferable, constructs under 65nm C MOS technique
Unit capacitance values are essentially 1fF, this just illustrates that the total capacitance value of the capacitor array of identical digit is reduced to 1/5th, and level is built
It is greatly shortened between immediately, so using ten successive approximation comparators of four 1.5 bits, the consumption and delay of hardware are more
Greatly.The design generates reference voltage using a six seat digital analog converters 108, not only consumes certain area and power consumption, and
The level being easy to interfere on the capacitor array 102 of successive approximation comparator is established, it is possible to introduce imbalance, at high frequencies
It influences bigger.This also limits the rate of the successive approximation comparator under this structure.
Summary of the invention
It is an object of the invention to propose a kind of novel 1.5 redundancy bits acceleration based on controllable asymmetric dynamic comparator
The structure of gradual approaching A/D converter.It is characterized in that the technology of 1.5 redundancy bits acceleration is introduced after first,
After the capacitor sole plate level overturning of MSB, capacitor array top plate level not yet completely set up when by top plate level
Intersect two controllable asymmetric dynamic comparators of input, be compared, is selected the sole plate of this group of capacitor connecing ginseng according to result
It examines voltage high level, reference voltage low level or maintains common mode electrical level.Present invention introduces 1.5 redundancy bits accelerate skill
Art not only shortens former of waiting and establishes the complete time, accelerates the conversion rate of analog-digital converter, and also add
Redundancy reduces error code, loses code, improves precision.
1.5 redundancy bits provided by the invention based on controllable asymmetric dynamic comparator accelerate successive approximation modulus to turn
Parallel operation, structure are as shown in Figure 2.Its circuit includes: two identical boot-strapped switch 201, one group of symmetrical N binary system
Capacitor array 202, two controllable asymmetric dynamic comparators 205,206, a common dynamic comparer 207 and SAR ADC's
Digital Logical Circuits module 208；Wherein:
Boot-strapped switch 201 contains a signal input part, an input end of clock, an output end；
The capacitor of group containing N in N binary capacitor arrays 202, wherein N group capacitance is equal with N-1 group capacitance,
For unit capacitor, from N-1 group to first group, two times of capacitance equal than being incremented by；The top plate of each group of capacitor is mutually coupled with node
203,204, the sole plate of each group of capacitor connects three groups of transmission gate switches 210,211；
Each transmission gate 210,211 includes a n type field effect transistor and a p type field effect transistor, and the two channel is flat
Row arrangement, the drain electrode end of the two are interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission gate electricity
The source terminal on road, the gate terminal of n type field effect transistor constitute the N gate terminal of transmission gate circuit, the grid of p type field effect transistor
The extreme P-gate for constituting transmission gate circuit is extreme；
Each controllable asymmetric dynamic comparator 205,206 has a positive input terminal, a negative input end, a clock defeated
Enter end, a positive output end and a negative output terminal；
Each common dynamic comparer 207 is there are two regardless of polar input terminal, and a Clock control end, there are two opposite
The output end answered；
The Digital Logical Circuits module 208 of SAR ADC includes:
Clock generation module generates clock signal 222,223 according to the data flow of three comparators；
Digital Logic processing module, for generating the logic control of 202 sole plate level of N binary capacitor arrays overturning
Signal 220,221 and register module store output data code；
In the present invention, two boot-strapped switch signal inputs connect differential signal input respectively, and input end of clock connects whole
The external of a successive approximation comparator controls clock, and sampling keeps clock, and output terminates symmetrical N binary capacitor battle array
The top plate and node 203,204 of column 202, switch is disconnected after sample phase acquires input signal on capacitor array top plate
It opens, voltage value is stored on the top plate of capacitor array；
In the present invention, the top plate of each group of capacitor is mutually coupled with boot-strapped switch in N binary capacitor arrays 202
201, the input terminal 207 and section of the input terminal of two controllable asymmetric dynamic comparators 205,206, one common dynamic comparers
Point 203,204；The sole plate of each group of capacitor connects three groups of transmission gate switches 210,211, by the application of logic circuit module of SAR ADC
208 logic controls generated connect reference voltage high level, reference voltage low level or common mode electrical level；In this way, each capacitor battle array
The comparison result of column top plate level generates the overturning of capacitor sole plate level via the processing of application of logic circuit module 208 of SAR ADC
Signal 220,221 is controlled, control connects reference voltage high level, reference voltage low level or common mode when the sole plate of the capacitance group of position
Level, to generate the comparative level of next bit on capacitor array top plate；
In the present invention, the positive-negative input end of two controllable asymmetry dynamic comparers 205,206 intersect the input position N two into
Two top plate voltages of capacitor array 202 processed, and intersect access node 203,204；Clock input connects the logic electricity of SAR ADC
The control signal 220,221 that road module 208 generates, controls cut-offfing for controllable asymmetry dynamic comparer 205,206；It is controllable non-
Symmetry comparator 205,206 is using asymmetric or comparator the input of load of latch in comparator to pipe threshold
It is asymmetric, in the side input signal of comparator be superimposed an adjustable reference voltage, such connection be equivalent to by the position N two into
The differential voltage of 202 two top plates of capacitor array processed generates the output code of 1.5 bits compared with adjustable reference voltage, realizes
1.5 redundancy bits accelerate；The code of output is transferred to the application of logic circuit module 208 of SAR ADC, generates the control clock of comparator
222,223 and capacitor sole plate level overturning control signal 220,221；
In the present invention, two climaxs of the common input of a dynamic comparer 207 N binary capacitor array 202 of termination
Plate voltage and access node 203,204；Clock input connect SAR ADC application of logic circuit module 208 generate control signal 220,
221, control cut-offfing for common dynamic comparer 207；Two top plate voltages of N binary capacitor arrays 202 are being controlled
Compare, generates the output code of 1 bit；The code of output is transferred to the application of logic circuit module 208 of SAR ADC, generates the control of comparator
Clock 222,223 and capacitor sole plate level overturning control signal 220,221 processed；
In the present invention, first is triggered next bit compared with M to N comparisons are by common dynamic comparer 207 and built
It is vertical, and compared in second to M comparisons by two controllable asymmetric dynamic comparators 205,206 and trigger next bit and build
It is vertical；
In the present invention, the Digital Logical Circuits module 208 of SAR ADC generates clock according to the data flow of three comparators
The logic control signal 220,221 of 202 sole plate level of signal 222,223, N binary capacitor array overturning and storage are defeated
Numeric data code out；
The present invention further provides 1.5 redundancy bits based on controllable asymmetric dynamic comparator to accelerate gradual approaching
The workflow of number converter, specific as follows:
When CK is high level, boot-strapped switch 201 is opened, and input signal is sampled to the binary system electricity of analog-digital converter
On the top plate for holding array 202, the sole plate of every group of capacitance group of capacitor array meets common mode electrical level V at this timecm, common Dynamic comparison
Device 207 and controllable asymmetric comparator 205,206 are turned off, and analog-digital converter is in sample phase；
When CK is low level, boot-strapped switch 201 is turned off, and capacitor array 202 is hanging, and the quantity of electric charge is constant, when failing edge
The input signal at quarter is just held on capacitor array 202, and analog-digital converter is in quantization stage；
The control for the clock signal 222,223 that common dynamic comparer 207 is generated in the application of logic circuit module 208 of SAR ADC
The input signal of holding is compared under system, the data of dynamic comparer 207 are transferred to the application of logic circuit module of SAR ADC
In 208, combined logic generates logic control signal 220,221, controls first capacitance group by three groups of transmission gate switches 210
The symmetrical reverses direction of sole plate, reference voltage high level or reference voltage low level；Delay through one section of short time, at this time
One level foundation is not yet completed, and two controllable asymmetric dynamic comparators start the comparison of 1.5 bits, symmetrical top plate
Level cross inputs two controllable asymmetric dynamic comparators 205,206, i.e., it is controllably non-node 203,204 to be intersected access two
The positive input terminal and negative input end of symmetric dynamic comparator 205,206, when the application of logic circuit module 208 of SAR ADC generates
It is compared under the control of clock signal 222,223 to establishing signal, two controllable asymmetric dynamic comparators 205,206 data pass
In the defeated application of logic circuit module 208 to SAR ADC, combined logic generates logic control signal 220,221, passes through three groups of transmission
The sole plate of second group of capacitor is connect reference voltage high level, reference voltage low level and either maintained altogether by the control of door switch 210
Mould level repeats the step, until last 1.5 bit-level of position；
After last 1.5 bit-level of position compares, controllable asymmetric dynamic comparator 205,206 be will be off under
In one quantization period, after which establishes completely, common dynamic comparer 207 is opened, the comparison of digit after completion, until
N；
Dynamic comparer 205,206,207 quantifies data out in the application of logic circuit module 208 of SAR ADC by number
Logical operation generates N binary codes, is stored in register, exports in the rising edge of next external sampling clock.
It is as shown in Figure 3 for realizing the controllable asymmetric dynamic comparator of 1.5 bits in the present invention.It is controllable asymmetric dynamic
State comparator realize there are two ways to, the controllable asymmetric dynamic comparator of different implementation methods it is slightly different in structure.
The first is that dynamic comparer latch load is controllably asymmetric, is N-type transistor in Fig. 3 comprising input to pipe 301,302
M1,M2；Tail current source capsule 303 is N-type transistor M3 in Fig. 3；Latch 304, two end to end phase inverters are constituted,
It is made of in Fig. 3 P-type transistor M6, M7 and N-type transistor M4, M5；Reset transistor 305,306,307,308, in Fig. 3
It is P-type transistor M9, M10, M11, M12；Output buffer 309A, 309B are by P-type transistor M14, M15 and N in Fig. 3
What transistor npn npn M12, M13 were constituted；The latch output node 310,311 of controllable asymmetric dynamic comparator；312A, 312B are
The latch of controllable asymmetric dynamic comparator exports controlled capacitance array.Implementation is as follows: the latch of dynamic comparer
304 are connected to node 310,311 with capacitive load array 312A, 312B of belt switch, pass through the logical of control switch 331,332
Disconnected, the payload size difference at construction acquisition 304 both ends of latch produces the overturning threshold of latch by the tripe systems of payload size
The difference of threshold voltage, it is equivalent to arrive input terminal, the mismatch of input threshold value is artificially produced, produces and is superimposed in input signal at one end
The effect of one reference voltage.And the difference by adjusting the load of 304 both ends of comparator latch, it is adjustable of different sizes out
Reference voltage effect.Second of implementation method is exactly that dynamic comparer input is controllably asymmetric to pipe threshold voltage, comprising defeated
Enter to pipe 301,302, is N-type transistor M1, M2 in Fig. 3；Tail current source capsule 303 is N-type transistor M3 in Fig. 3；It latches
Device 304, two end to end phase inverters are constituted, are made of in Fig. 3 P-type transistor M6, M7 and N-type transistor M4, M5；It is multiple
Bit transistor 305,306,307,308 is P-type transistor M9, M10, M11, M12 in Fig. 3；Output buffer 309A, 309B,
It is to be made of P-type transistor M14, M15 and N-type transistor M12, M13 in Fig. 3；The lock of controllable asymmetric dynamic comparator
Storage output node 310,311；The input of controllable asymmetric dynamic comparator is external to the body end voltage 320,321 of pipe.It realizes
Mode is as follows: body end of the input to pipe 301,302 being drawn, external voltage, by the voltage difference for changing metal-oxide-semiconductor source and body end
Input is adjusted to the threshold voltage of pipe 301,302, produces the effect for being superimposed a reference voltage in input signal at one end.And
By adjusting input to tube end voltage difference, the effect of adjustable reference voltage of different sizes out.But there is any to need to infuse
Meaning, being needed to input using second method to pipe is P-type transistor either deep trap N-type transistor.Method provided by the invention
Though accurate reference voltage value cannot be constructed, can explain in detail later, in 1.5 redundancy bits accelerating circuits, reference voltage
Value does not need especially accurately, need to only meet in a certain range.This 1.5 ratios based on controllable asymmetric dynamic comparator
Two four input comparators needed for special implementation method is realized compared to 1.5 traditional bits add corresponding reference voltage or two two
Input comparator adds redundant reference voltage generation circuit, can significantly simplify circuit scale, reference voltage is especially omitted
Generation circuit then reduces the power consumption and area of analog-digital converter, can change rapidly and establish equivalent reference voltage value (if needed
Want), accelerate the conversion speed of analog-digital converter, and there is universality, can be applied to the application scenarios of other 0.5 bits.
Foregoing teachings substantially describe feature and technological merit of the invention, embodiment are cited below particularly out, to brighter
Illustrate thought of the invention clearly.Any those of ordinary skill in the art are it will be understood that can be revealed according to the present invention
The framework for realizing the identical purpose of the present invention is designed in idea and specific embodiment modification, and such same framework is without departing from this hair
Spirit and scope defined in bright appended claims.
Detailed description of the invention
Fig. 1 is the gradual approaching A/D converter for preceding four 1.5 bits that Chun-Cheng Liu was delivered in 2010
Structural schematic diagram.
Fig. 2 provides 1.5 redundancy bits based on controllable asymmetric dynamic comparator for the present invention and accelerates gradual approaching
The structural schematic diagram of number converter.
Fig. 3 is the circuit diagram of controllable asymmetric dynamic comparator provided by the invention.
Fig. 4 is example provided by the invention, and second is the gradual approaching A/D converter amount that 1.5 redundancy bits accelerate
Top plate Voltage Establishment schematic diagram during change.
Fig. 5 is example provided by the invention, and second is the gradual approaching A/D converter that 1.5 redundancy bits accelerate
Digital calibration logic.
Figure label:
101 be the gradual approaching A/D converter for preceding four 1.5 bits that Chun-Cheng Liu was delivered in 2010
Two boot-strapped switch 101；102 be 10 binary capacitor arrays of the SAR ADC, the top of 103,104 capacitor arrays
Pole plate links together the node connecting with dynamic comparer；105,106,107 be the SAR ADC three dynamic comparers,
Wherein 106,107 compare foundation for 1.5 bits；108 be the six seat digital analog converters of the SAR ADC, passes through capacitor sole
Plate overturning generates the reference voltage that every grade of 1.5 bits compare foundation；108 be the application of logic circuit module of the SAR ADC.
201 be that 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter
Two identical boot-strapped switch；202 be the position the N binary capacitor array of the invention；203, the top plate of 204 capacitor arrays
Link together the node connecting with dynamic comparer；205,206 be the invention two controllable asymmetric dynamic comparators；
207 be a common dynamic comparer of the invention；208 be the Digital Logical Circuits module of the SAR ADC of the invention；210,
211 be the sole plate transmission gate switch of the position the N binary capacitor of the invention；220,221 be that the number of SAR ADC of the invention is patrolled
Collect the logic control signal that circuit module generates；222, what the Digital Logical Circuits module of the SAR ADC of 223 inventions generated is dynamic
State comparator clock signal.
301,302 be controllable asymmetric dynamic comparator provided by the invention input to pipe, be body end voltage in Fig. 3
Deep trap N-type transistor M1, M2 being brought out；303 be the tail current source capsule of controllable asymmetric dynamic comparator, N-type transistor M3；
304 be the latch of controllable asymmetric dynamic comparator；305,306,307,308 be controllable asymmetric dynamic comparator reset
Transistor, P-type transistor M9, M10, M11, M12；309A, 309B are the output buffers of controllable asymmetric dynamic comparator；
310,311 be controllable asymmetric dynamic comparator latch output node；312A, 312B are controllable asymmetric dynamic comparators
Latch export controlled capacitance array；320,321 be controllable asymmetric dynamic comparator body end voltage of the input to pipe.
401 be the top plate Voltage Establishment schematic diagram of the gradual approaching A/D converter of traditional top plate sampling, wherein
410 be the redundancy of first foundation of the gradual approaching A/D converter of traditional top plate sampling；402 be offer of the present invention
Example, second be 1.5 redundancy bits accelerate gradual approaching A/D converter quantizing process in top plate Voltage Establishment
Schematic diagram, wherein 411 be the superfluous of first foundation that second is the gradual approaching A/D converter that 1.5 redundancy bits accelerate
Remaining, 412 be the redundancy that the second that second is the gradual approaching A/D converter that 1.5 redundancy bits accelerate is established；
403 be example provided by the invention, and second is the Dynamic comparison for the gradual approaching A/D converter that 1.5 redundancy bits accelerate
Device group, 413 be controllable asymmetric dynamic comparator, and 414 be common dynamic comparer；404 be example provided by the invention, second
Position is the control clock of the dynamic comparer group for the gradual approaching A/D converter that 1.5 redundancy bits accelerate, wherein 415 be control
The clock of two controllable asymmetric dynamic comparators is made, 416 be the clock for controlling dynamic comparer.
501 be example provided by the invention, and second is in the gradual approaching A/D converter that 1.5 redundancy bits accelerate
The data of one bit of single-stage；502 be second be 1.5 redundancy bits accelerate gradual approaching A/D converter in 1.5 bits
Every grade of data；503 be the output data that second is the gradual approaching A/D converter that 1.5 redundancy bits accelerate.
Specific embodiment
Bearing calibration provided by the invention is described in detail with reference to the accompanying drawing.It is worth noting that, the present invention mentions
The gradual approaching A/D converter that 1.5 redundancy bits supplied accelerate has different an index and performance implementation method, in the present invention
1.5 bits based on controllable asymmetric dynamic comparator are realized can also be there are many application scenarios.Following examples is the present invention
One typical realization circuit is provided, formation and use of the invention is only to illustrate, is not intended to limit the invention.
1.5 redundancy bits provided by the invention based on controllable asymmetric dynamic comparator accelerate primary and secondary approach type modulus to turn
Parallel operation example, implementation goal are to realize that a 1.5 redundancy bits of second accelerate the 150MS/s sample rate of top plate sampling, 10
The gradual approaching A/D converter of position precision, concrete structure diagram are as shown in Figure 2.The structure includes comprising two identical grid
Pressure bootstrapped switch 201, one group of symmetrical 10 binary capacitor array 202, two controllable asymmetric dynamic comparators 205,
206, the Digital Logical Circuits module 208 of common a dynamic comparer 207 and SAR ADC；Wherein:
Two boot-strapped switch signal inputs connect differential signal input respectively, and input end of clock connects entire Approach by inchmeal
The external of type comparator controls clock, and sampling keeps clock, and output terminates the top of symmetrical 10 binary capacitor arrays 202
Pole plate, the input terminal of two controllable asymmetric dynamic comparators 205,206, common dynamic comparer 207 input terminal and
Node 203,204, switch disconnects after sample phase acquires input signal on capacitor array top plate, and voltage value is stored in electricity
On the top plate for holding array；The sole plate of each group of capacitor of 10 binary capacitor arrays 202 connects three groups of transmission gate switches
210,211, the logic control 220,221 generated by the application of logic circuit module 208 of SAR ADC connects reference voltage high level, reference
Voltage low level or common mode electrical level；The positive-negative input end of two controllable asymmetry dynamic comparers 205,206 intersects input N
Two top plate voltages of binary capacitor array 202, and intersect access node 203,204；Clock input connects patrolling for SAR ADC
The control signal 222,223 that circuit module 208 generates is collected, cut-offfing for controllable asymmetry dynamic comparer 205,206 is controlled；It can
Load asymmetric or comparator input of the asymmetry comparator 205,206 using latch in comparator is controlled to pipe threshold
What is be worth is asymmetric, and an adjustable reference voltage is superimposed in the side input signal of comparator, and such connection is equivalent to 10
The differential voltage of position 202 two top plates of binary capacitor array generates the output of 1.5 bits compared with adjustable reference voltage
Code realizes that 1.5 redundancy bits accelerate；The code of output is transferred to the application of logic circuit module 208 of SAR ADC, generates the control of comparator
Clock 222,223 and capacitor sole plate level overturning control signal 220,221 processed.First and third are to ten in this example
Comparison triggering next bit compared by common dynamic comparer 207 establish, and it is controllable non-right by two in deputy comparison
Claim dynamic comparer 205,206 to compare triggering next bit to establish；
The working sequence of the dynamic comparer of the example is as shown in Fig. 4 415,416, in conjunction with timing diagram to its course of work
It does as described below:
(1) above-mentioned 1.5 redundancy bits of second based on controllable asymmetric dynamic comparator accelerate successive approximation modulus
For converter when CK is high, CK is high level, and boot-strapped switch 201 is opened, and input signal is sampled analog-digital converter
On the top plate of binary capacitor array 202, the sole plate of every group of capacitance group of capacitor array meets common mode electrical level V at this timecm, commonly
Dynamic comparer 207 and controllable asymmetric comparator 205,206 are turned off, and analog-digital converter is in sample phase；
(2) when CK is low level, boot-strapped switch 201 is turned off, and capacitor array 202 is hanging, and the quantity of electric charge is constant, failing edge
The input signal at moment is just held on capacitor array 202, and analog-digital converter is in quantization stage.Common dynamic comparer
207 under the control of clock signal 222,223 that the application of logic circuit module 208 of SAR ADC generates and when 416 high level of signal, right
The input signal of holding is compared, and the data of dynamic comparer 207 are transferred in the application of logic circuit module 208 of SAR ADC, warp
Combinational logic generates logic control signal 220,221, controls first capacitance group sole plate by three groups of transmission gate switches 210
Symmetrical reverses direction, reference voltage high level or reference voltage low level；
(3) delay through one section of short time, primary level foundation is not yet completed at this time, two controllable asymmetric dynamics
Comparator starts the comparison of deputy 1.5 bit, and symmetrical top plate level cross inputs two controllable asymmetric dynamic ratios
Compared with device 205,206, i.e., node 203,204 is intersected to the positive input terminal of two controllable asymmetric dynamic comparators 205,206 of access
And negative input end, SAR ADC application of logic circuit module 208 generate clock signal 222,223 control under and signal 415
It when high level, is compared to signal is established, two controllable asymmetric dynamic comparators 205,206 data are transferred to SAR ADC
Application of logic circuit module 208 in, combined logic generates logic control signal 220,221, passes through three groups of transmission gate switches 210 and controls
The sole plate of second group of capacitor is connect reference voltage high level, reference voltage low level or maintains common mode electrical level by system, controllably
Asymmetric dynamic comparator 205,206 will be off until next quantization period；
(4) it is delayed after a period of time, after the second bit level is established completely, when 416 high level of signal, common Dynamic comparison
Device 207 is opened, and is compared to signal is established, the data of dynamic comparer 207 are transferred to the application of logic circuit module of SAR ADC
In 208, combined logic generates logic control signal 220,221, controls first capacitance group by three groups of transmission gate switches 210
The symmetrical reverses direction of sole plate, reference voltage high level or reference voltage low level；
(5) data B2H and B2L that dynamic comparer 205,206 quantifies, 207 quantify data B1 out, and B3 ~ B10 is in SAR
According to the logical calculation method operation in Fig. 5 in the application of logic circuit module 208 of ADC, 10 binary codes are generated, is stored in and posts
In storage, exported in the rising edge of next external sampling clock.
Although the contents of the present invention and advantage disclose as above in detail, it should be noted that, the scope of the present invention is simultaneously
The specific embodiments such as method and step described in this description are not only restricted to, without departing from the spirit and scope of the present invention,
Any those of ordinary skill in the art all revealed content can make many deformations and modification according to the present invention, these should also be regarded
For protection scope of the present invention.
Claims (5)
1. a kind of 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter, special
Sign is that circuit includes: two identical boot-strapped switch (201), one group of symmetrical N binary capacitor array
(202), two controllable asymmetric dynamic comparators (205,206), the number of common dynamic comparer (207) and SAR ADC
Word application of logic circuit module (208)；Wherein:
Boot-strapped switch (201) contains a signal input part, an input end of clock, an output end；
The capacitor of group containing N in N binary capacitor arrays (202), wherein N group capacitance is equal with N-1 group capacitance,
For unit capacitor, from N-1 group to first group, two times of capacitance equal than being incremented by；The top plate of each group of capacitor is mutually coupled with two
Node (203,204), the sole plate of each group of capacitor connect three groups of transmission gate switches (210,211)；
Each transmission gate switch (210,211) includes a n type field effect transistor and a p type field effect transistor, the two channel
The drain electrode end of parallel arrangement, the two is interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission gate
The source terminal of circuit, the gate terminal of n type field effect transistor constitute the N gate terminal of transmission gate circuit, p type field effect transistor
The P-gate that gate terminal constitutes transmission gate circuit is extreme；
Each controllable asymmetric dynamic comparator (205,206) has a positive input terminal, a negative input end, a clock input
End, a positive output end and a negative output terminal；
Each common dynamic comparer (207) is there are two regardless of polar input terminal, and a Clock control end, there are two corresponding
Output end；
The Digital Logical Circuits module (208) of SAR ADC includes:
Clock generation module generates clock signal (222,223) according to the data flow of three comparators；
Digital Logic processing module, for generating the logic control letter of N binary capacitor array (202) sole plate level overturnings
Number (220,221) and register module store output data code；
Two boot-strapped switch signal inputs connect differential signal input respectively, and input end of clock connects entire successive approximation ratio
External compared with device controls clock, and sampling keeps clock, and output terminates the climax of symmetrical N binary capacitor array (202)
Plate and two nodes (203,204), switch disconnects after sample phase acquires input signal on capacitor array top plate, voltage
Value is stored on the top plate of capacitor array；
In N binary capacitor arrays (202) top plate of each group of capacitor be mutually coupled with boot-strapped switch (201), two can
Control the input terminal (205,206) of asymmetric dynamic comparator, the input terminal (207) and node of common dynamic comparer
(203,204)；The sole plate of each group of capacitor connects three groups of transmission gate switches (210,211), by the application of logic circuit module of SAR ADC
(208) logic control generated connects reference voltage high level, reference voltage low level or common mode electrical level；In this way, each capacitor
The comparison result of array top plate level generates capacitor sole plate level via application of logic circuit module (208) processing of SAR ADC
Overturning control signal (220,221), control connect reference voltage high level, reference voltage low level when the sole plate of the capacitance group of position
Or common mode electrical level, to generate the comparative level of next bit on capacitor array top plate.
2. 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching as described in claim 1
Number converter, which is characterized in that the positive-negative input end of two controllable asymmetry dynamic comparers (205,206) intersects input N
Two top plate voltages of position binary capacitor array (202), and intersect two nodes (203,204) of access；Clock input connects
The control signal (220,221) that the application of logic circuit module (208) of SAR ADC generates, controls controllable asymmetry dynamic comparer
(205,206) are cut-off；Controllable asymmetry comparator (205,206) using the load of latch in comparator it is asymmetric or
Be comparator input to the asymmetric of pipe threshold, an adjustable reference voltage is superimposed in the side input signal of comparator,
Such connection is equivalent to the differential voltage of (202) two top plates of N binary capacitor arrays and adjustable reference voltage ratio
Compared with the output code of 1.5 bits of generation realizes that 1.5 redundancy bits accelerate；The code of output is transferred to the logic circuit mould of SAR ADC
Block (208) generates control clock (222,223) and capacitor sole plate level overturning control signal (220,221) of comparator.
3. 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching as claimed in claim 2
Number converter, which is characterized in that the two of common dynamic comparer (207) input N binary capacitor array (202) of termination
A top plate voltage, and two nodes (203,204) of access；The application of logic circuit module (208) that clock input meets SAR ADC generates
Control signal (220,221), control cut-offfing for common dynamic comparer (207)；To N binary capacitor arrays (202)
Two top plate voltages compare in control, generate the output code of 1 bit；The code of output is transferred to the logic circuit mould of SAR ADC
Block (208) generates control clock (222,223) and capacitor sole plate level overturning control signal (220,221) of comparator.
4. 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching as claimed in claim 3
Number converter, which is characterized in that first compared with M to N comparisons are by common dynamic comparer (207) trigger it is next
Position is established, and compares triggering next bit by two controllable asymmetric dynamic comparators (205,206) in second to M comparisons
It establishes.
5. 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching as claimed in claim 4
Number converter, which is characterized in that its workflow is as follows:
When CK is high level, boot-strapped switch (201) is opened, and input signal is sampled to the binary capacitor of analog-digital converter
On the top plate of array (202), the sole plate of every group of capacitance group of capacitor array meets common mode electrical level V at this timecm, common Dynamic comparison
Device (207) and two controllable asymmetric comparators (205,206) are turned off, and analog-digital converter is in sample phase；
When CK is low level, boot-strapped switch (201) shutdown, vacantly, the quantity of electric charge is constant for binary capacitor array (202), under
It drops the input signal along the moment to be just held on capacitor array (202), analog-digital converter is in quantization stage；
Two clock signals that common dynamic comparer (207) is generated in the application of logic circuit module (208) of SAR ADC (222,
223) input signal of holding is compared under control, the data of common dynamic comparer (207) are transferred to SAR ADC's
In application of logic circuit module (208), combined logic generates two logic control signals (220,221), is opened by three groups of transmission gates
Close the symmetrical reverses direction that (210) control first capacitance group sole plate, reference voltage high level or reference voltage low level；Through
The delay of one section of short time, at this time primary level foundation are not yet completed, two controllable asymmetric dynamic comparators (205,
206) start the comparison of 1.5 bits, symmetrical top plate level cross input two controllable asymmetric dynamic comparators (205,
206) two nodes (203,204), i.e., are intersected to the positive input terminal of two controllable asymmetric dynamic comparators (205,206) of access
And negative input end, SAR ADC application of logic circuit module (208) generate two clock signals (222,223) control under pair
It establishes signal to be compared, two controllable asymmetric dynamic comparator (205,206) data are transferred to the logic circuit of SAR ADC
In module (208), combined logic generates two logic control signals (220,221), is controlled by three groups of transmission gate switches (210)
The sole plate of second group of capacitor is connect reference voltage high level, reference voltage low level or maintains common mode electrical level by system, is repeated
The step, until last 1.5 bit-level of position；
After last 1.5 bit-level of position compares, two controllable asymmetric dynamic comparators (205,206) be will be off, directly
To next quantization period；After the bit level is established completely, common dynamic comparer (207) is opened, the ratio of digit after completion
Compared with until N；
Two controllable asymmetric dynamic comparators (205,206), common dynamic comparers (207) quantify data out in SAR
Pass through the binary code that digital logical operation generates N in the application of logic circuit module (208) of ADC, is stored in register, under
The rising edge output of one external sampling clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610411806.9A CN106067817B (en) | 2016-06-14 | 2016-06-14 | 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610411806.9A CN106067817B (en) | 2016-06-14 | 2016-06-14 | 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106067817A CN106067817A (en) | 2016-11-02 |
| CN106067817B true CN106067817B (en) | 2019-02-26 |
Family
ID=57420256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610411806.9A Active CN106067817B (en) | 2016-06-14 | 2016-06-14 | 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106067817B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395205B (en) * | 2017-06-22 | 2020-06-19 | 西安电子科技大学 | Successive approximation type analog-digital converter based on asymmetric differential capacitor array |
| CN109995368B (en) * | 2017-12-29 | 2023-06-02 | 钜泉光电科技(上海)股份有限公司 | Successive approximation type analog-to-digital converter |
| CN108777580B (en) * | 2018-05-24 | 2020-02-21 | 西安电子科技大学 | Method for controlling SAR ADC level switch by mixed capacitance overturning technology |
| CN110198167B (en) * | 2019-04-17 | 2021-01-08 | 西安电子科技大学 | Asymmetric SAR ADC capacitance switch sequential circuit and method |
| CN110166045B (en) * | 2019-04-25 | 2021-06-04 | 复旦大学 | Snapshot circuit for extracting signal change edge |
| CN111091818A (en) * | 2019-12-24 | 2020-05-01 | 广东美的白色家电技术创新中心有限公司 | Voice recognition circuit, voice interaction equipment and household appliance |
| CN111478704A (en) * | 2020-04-17 | 2020-07-31 | 北方工业大学 | Low-power consumption analog-digital converter |
| CN111865319A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Ultra-low power consumption successive approximation type analog-to-digital converter based on four-input comparator |
| CN111865320B (en) * | 2020-07-30 | 2024-02-09 | 楚天龙股份有限公司 | Low-power-consumption successive approximation type analog-to-digital converter |
| CN112737584B (en) * | 2020-12-31 | 2023-08-01 | 中国电子科技集团公司第十四研究所 | On-chip full-integrated capacitance mismatch calibration circuit |
| TWI779960B (en) * | 2021-12-09 | 2022-10-01 | 瑞昱半導體股份有限公司 | Analog-to-digital conversion circuit and method having speed-up comparison mechanism |
| CN113922819B (en) * | 2021-12-14 | 2022-04-12 | 之江实验室 | One-step two-bit successive approximation type analog-to-digital converter based on background calibration |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639169A (en) * | 2015-02-12 | 2015-05-20 | 西安交通大学 | Two-step conversion gradual approach type analog-to-digital conversion circuit structure |
| CN104967451A (en) * | 2015-07-31 | 2015-10-07 | 中国科学院电子学研究所 | Successive approximation type analog-to-digital converter |
-
2016
- 2016-06-14 CN CN201610411806.9A patent/CN106067817B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639169A (en) * | 2015-02-12 | 2015-05-20 | 西安交通大学 | Two-step conversion gradual approach type analog-to-digital conversion circuit structure |
| CN104967451A (en) * | 2015-07-31 | 2015-10-07 | 中国科学院电子学研究所 | Successive approximation type analog-to-digital converter |
Non-Patent Citations (2)
| Title |
|---|
| 一种12bit 50-MS/s 4-mW带比较器失调校正的逐次逼近型模数转换器;林涛 等;《复旦学报（自然科学版）》;20130630;第52卷(第3期);第314-320页 |
| 一种具有2-bit/cycle结构的400-MS/s 8-bit逐次逼近型模数转换器设计;代国宪 等;《复旦学报（自然科学版）》;20140831;第53卷(第4期);第446-451页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106067817A (en) | 2016-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106067817B (en) | 1.5 redundancy bits based on controllable asymmetric dynamic comparator accelerate gradual approaching A/D converter | |
| CN104811203B (en) | A kind of 2bits per circle high speed gradual approaching A/D converters | |
| WO2020173225A1 (en) | High-speed digital logic circuit for sar_adc, and sampling adjustment method | |
| CN206164507U (en) | Successive approximation type adc with segmentation capacitor array | |
| CN107835021B (en) | Variable-delay asynchronous time sequence control circuit and control method | |
| CN104124971B (en) | Two-stage flow-line modulus converter based on Approach by inchmeal principle | |
| CN104967451B (en) | Gradual approaching A/D converter | |
| CN107425852B (en) | Successive approximation type analog-to-digital converter based on binary weighted charge redistribution | |
| CN104796148A (en) | High-speed low-power-loss successive approximation type analog-digital converter | |
| CN105897272A (en) | Successive approximation register analog-to-digital converter and control method thereof | |
| CN106921391A (en) | System-level error correction SAR analog-digital converters | |
| CN110190854B (en) | Two-step SAR ADC-oriented shared reference voltage realization circuit and method | |
| CN103152050A (en) | High-speed successive approximation type analog-to-digital converter | |
| CN107888190A (en) | Gradual approaching A/D converter based on asymmetric differential capacitance array | |
| CN104320141A (en) | Low-power-consumption 12-bit assembly line successive approximation analog-digital converter | |
| CN110535470A (en) | A kind of comparator clock generation circuit and high speed gradual approaching A/D converter | |
| CN103199864B (en) | A kind of gradual approaching A/D converter | |
| CN203708221U (en) | Broadband sample hold circuit used for front end of successive-approximation analog-to-digital converter | |
| CN107968656B (en) | Successive approximation type analog-digital converter and application switching method thereof | |
| CN108111171A (en) | Suitable for differential configuration gradual approaching A/D converter dullness formula method of switching | |
| CN1561000B (en) | Pipeline structure analogue/digital converter of controlling input common-mode drift | |
| CN106603077A (en) | Successive approximation fully differential analog-digital converter and working process thereof | |
| CN107395205B (en) | Successive approximation type analog-digital converter based on asymmetric differential capacitor array | |
| CN107483054A (en) | High speed gradual approaching A/D converter based on Charge scaling | |
| CN201243275Y (en) | Digital/analog converting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |