CN111478704A - Low-power consumption analog-digital converter - Google Patents
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- 230000007306 turnover Effects 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The embodiment of the application provides a low-power consumption analog-digital converter, which comprises a sampling switch module, a first voltage-to-digital conversion module and a second voltage-to-digital conversion module, wherein the sampling switch module comprises a first grid voltage bootstrap switch and a second grid voltage bootstrap switch; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array which are symmetrically distributed, wherein an upper electrode plate between the highest-order capacitor and the next-highest-order capacitor of the P-end capacitor array is connected with a P-end isolating switch, and an upper electrode plate between the highest-order capacitor and the next-highest-order capacitor of the N-end capacitor array is connected with an N-end isolating switch; the same-direction end of the comparator module is connected with the tail end capacitor of the P-end capacitor array, and the reverse end of the comparator module is connected with the tail end capacitor of the N-end capacitor array; and the digital control logic module is connected with the output end of the comparator module and is used for turning the level of the lower electrode plate of the capacitor array module according to the output data of the comparator module. According to the application, the P-end isolating switch and the N-end isolating switch are arranged, so that the capacitance number of the capacitor array in the subsequent conversion process is reduced, and the power consumption is reduced.
Description
Technical Field
The application relates to the technical field of analog-to-digital converters, in particular to a low-power-consumption analog-to-digital converter.
Background
The analog-to-digital converter builds a bridge in the digital field and the analog field, and is a computer and all terminal equipment Is an indispensable part for interacting with the nature. Currently, various electronic products are developed in the direction of being light, thin and easy to carry, the area of a chip is continuously reduced along with the continuous reduction of integrated circuit process nodes, the integration of the chip is beneficial to realizing the target, but the capacity of a battery is limited by the volume, and the development of the electronic products in the direction of being light, thin and easy to carry is hindered. Particularly, wearable devices and some implantable biomedical devices which are popular at present need to detect various body characteristics of people at any time, have high requirements on battery endurance, and can meet the requirements only by reducing the power consumption of electronic product chips, such as ADC (analog-to-digital converter) power consumption. The SAR ADC (successive approximation Analog-to-Digital Converter) is an integrated chip, and has the advantages of simple structure and small area, and the Digital logic and dynamic conversion characteristics of the SAR ADC can reduce the power consumption of the SAR ADC to a nanowatt level, so that the SAR ADC is widely concerned by people. However, the requirement for the accuracy of the ADC is continuously increased, and increasing the accuracy of the ADC increases the capacitance array, thereby increasing the conversion energy, and the charge redistribution process of the capacitance array occupies the greatest proportion of the overall power consumption, so that the power consumption of the sar ADC is significantly increased. In the related art, the energy consumption of the SAR ADC can be effectively improved by optimizing a conversion algorithm of a capacitor array, such as a tri-level scheme, a hybrid scheme and the like, and the energy consumption is 42.42CVref 2And 15.88CVref 2However, this still does not meet the human power consumption requirements for SAR ADCs.
Disclosure of Invention
To solve the above technical problem, the present application provides a low power consumption analog-to-digital converter.
The low-power consumption analog-digital converter provided by the embodiment of the application comprises:
The sampling switch module comprises a first grid voltage bootstrap switch and a second grid voltage bootstrap switch, wherein the first grid voltage bootstrap switch inputs a P-end analog signal, and the second grid voltage bootstrap switch inputs an N-end analog signal;
The capacitor array module comprises a P-end capacitor array and an N-end capacitor array which are symmetrically distributed, wherein an upper electrode plate between the highest-order capacitor and the next-highest-order capacitor of the P-end capacitor array is connected with a P-end isolating switch, and an upper electrode plate between the highest-order capacitor and the next-highest-order capacitor of the N-end capacitor array is connected with an N-end isolating switch;
The same-direction end of the comparator module is connected with the tail end capacitor of the P-end capacitor array, and the reverse end of the comparator module is connected with the tail end capacitor of the N-end capacitor array;
And the digital control logic module is connected with the output end of the comparator module and is used for overturning the level of the lower electrode plate of the capacitor array module according to the output data of the comparator module.
Optionally, the P-end capacitor array includes a first capacitor array and a second capacitor array, the capacitors of the first capacitor array are arranged between the sub-high capacitors and the unit capacitors according to binary weights, the second capacitor array is a capacitor array of a C-2C structure, and a tail end of the first capacitor array is connected to a head end of the second capacitor array.
Optionally, the first capacitor array includes a unit capacitor Cup, and the second capacitor array includes a unit capacitor Cup, a two-unit capacitor 2Cup, and a dummy capacitor Cdp.
Optionally, the last polar plate of 2Cup of two unit capacitance in the second capacitor array is connected the last polar plate of P end capacitor array, unit capacitance Cup in the second capacitor array and the last polar plate of dummy capacitance Cdp are connected the bottom plate of P end capacitor array, unit capacitance Cup in the second capacitor array is used for control the level control switch of the inferior low level bottom plate of P end capacitor array, dummy capacitance in the second capacitor array is used for control the level control switch of the lowest level bottom plate of P end capacitor array.
Optionally, the unit capacitance Cup and the dummy capacitance Cdp have the same size.
Optionally, the P-end capacitor array is correspondingly connected with one level control switch from the lower plate of the highest-order capacitor to the lower plate of the dummy capacitor Cdp.
Optionally, the level control switch is connected to a Vref terminal or a Vcm terminal or a gnd terminal.
The application provides the beneficial effects of the low-power consumption analog-digital converter, including:
The embodiment of the application is based on a hybrid conversion scheme, and the first three bits of conversion of the SAR ADC do not consume energy; the upper electrode plate between the highest-order capacitor and the second highest-order capacitor of the P-end capacitor array is connected with the P-end isolating switch, and the upper electrode plate between the highest-order capacitor and the second highest-order capacitor of the N-end capacitor array is connected with the N-end isolating switch, so that after the conversion of the first three positions is finished, the first two positions are isolated from the rest capacitors for the highest-order capacitor at one end of the capacitor array participating in the turnover, the capacitor number of the capacitor array in the subsequent conversion process is reduced, and the power consumption is reduced.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without any creative effort.
Fig. 1 is a schematic structural diagram of a low power consumption analog-to-digital converter according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of an isolation switch according to an embodiment of the present disclosure;
Fig. 3 is a schematic flowchart of a capacitor array conversion method according to an embodiment of the present disclosure;
Fig. 4 is a schematic diagram illustrating comparison of energy consumption simulation results provided in the embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a structural diagram of a low power consumption analog-to-digital converter provided in an embodiment of the present application, and as shown in fig. 1, the low power consumption analog-to-digital converter provided in the embodiment of the present application includes a sampling switch module, a capacitor array module, a comparator module, and an overall structure of the low power consumption analog-to-digital converter is a differential structure.
The sampling switch module comprises two sampling switches which are respectively a first grid voltage bootstrap switch and a second grid voltage bootstrap switch, and the first grid voltage bootstrap switch inputs a P-end analog signal V ip，VipCan be DACP signal, and the second grid voltage bootstrap switch inputs N-terminal analog signal V in，VinMay be a DACN signal. The first grid voltage bootstrap switch and the second grid voltage bootstrap switch are two switches with the same structure.
The capacitor array module is used for holding and redistributing charges, and mainly comprises 256Cu total capacitors (wherein Cu represents a unit capacitor), one half of the total capacitors are positioned in a P-end capacitor array, the other half of the total capacitors are positioned in an N-end capacitor array, and the P-end capacitor array and the N-end capacitor array are symmetrically distributed.
And the upper polar plate of the P-end capacitor array is connected with the drain end of the first grid voltage bootstrap switch. The P-end capacitor array comprises a first capacitor array and a second capacitor array, wherein the capacitance of the Most Significant Bit (MSB) of the first capacitor array is 64Cup, and Cup is the unit capacitance of the P end. The upper polar plate between the highest capacitor and the second highest capacitor of the first capacitor array is connected with a P-end isolating switch S pcFIG. 2 is a schematic diagram of a structure of a P-terminal isolation switch S pcthis can be achieved with the classical transmission gate shown in fig. 2. in fig. 2, C L KS is the clock signal.
The secondary high-order capacitor and the unit capacitor of the first capacitor array are arranged according to binary weighted capacitors, and are sequentially 32Cup, 16Cup, 8Cup, 4Cup, 2Cup and Cup. The second capacitor array is a capacitor array of a C-2C structure and comprises a unit capacitor Cup, two unit capacitors 2Cup and a dummy capacitor Cdp. The lower plates of the two unit capacitors 2Cup are connected in parallel with the unit capacitors Cup and the dummy capacitors Cdp. The tail end of the first capacitor array is connected with the head end of the second capacitor array, the tail end of the first capacitor array is Cup, and the head end of the second capacitor array is two-unit capacitor 2 Cup.
The upper pole plates of the second high-order capacitor 32Cup to the unit capacitor Cup of the first capacitor array and the two unit capacitors 2Cup of the second capacitor array are connected, and the upper pole plate of the highest-order capacitor of the first capacitor array is connected with the upper pole plate of the second capacitor array through a P-end isolating switch S pcAnd the upper electrode plate of the second highest capacitor of the first capacitor array is connected. The P-end capacitor array is respectively and correspondingly connected with a level control switch from the lower pole plate of the highest-order capacitor to the lower pole plate of the dummy capacitor Cdp, and the level control switches are S in sequence p8...Sp0. The level control switches are connected to the terminals of the reference voltage Vref or Vcm or gnd.
And the upper polar plate of the N-end capacitor array is connected with the drain end of the second grid voltage bootstrap switch. The N-end capacitor array comprises a third capacitor array and a fourth capacitor array, the highest-order capacitor of the third capacitor array is 64Cun, and Cun is a unit capacitor of the N end. The upper polar plate between the highest capacitor and the second highest capacitor of the third capacitor array is connected with an N-end isolating switch S ncN-terminal isolating switch S ncIt can also be implemented with a classical transmission gate as shown in fig. 2.
The secondary high-order capacitor and the unit capacitor of the third capacitor array are arranged according to binary weighted capacitors, and are sequentially 32Cun, 16Cun, 8Cun, 4Cun, 2Cun and Cun. The fourth capacitor array is a capacitor array with a C-2C structure and comprises a unit capacitor Cun, two unit capacitors 2Cun and a dummy capacitor Cdn. The lower polar plate of the two unit capacitors 2Cun is connected with the unit capacitor Cun and the dummy capacitor Cdn in parallel. The tail end of the third capacitor array is connected with the head end of the fourth capacitor array, the tail end of the third capacitor array is Cun, and the head end of the fourth capacitor array is two-unit capacitor 2 Cun.
In addition, C is up＝Cun＝Cdp＝Cdn＝CuAnd Cu is the unit capacitance of the capacitor array module.
The sub-high capacitor 32Cun of the third capacitor array to the upper plate of the unit capacitor Cun, and the two unit capacitors of the fourth capacitor array The upper polar plates of the 2Cun capacitors are connected, and the upper polar plate of the highest capacitor of the third capacitor array is connected with the upper polar plate of the highest capacitor of the third capacitor array through an N-end isolating switch S ncAnd the upper electrode plate of the second highest capacitor of the third capacitor array is connected. The N-end capacitor array is respectively and correspondingly connected with a level control switch from the lower plate of the highest-order capacitor to the lower plate of the dummy capacitor Cdn, and the level control switches are S in sequence n8...Sn0. The level control switches are connected to the terminals of the reference voltage Vref or Vcm or gnd.
And the same-direction end of the comparator module is connected with the tail end capacitor of the P-end capacitor array, and the reverse end of the comparator module is connected with the tail end capacitor of the N-end capacitor array.
And the digital control logic module is connected with the output end of the comparator module and comprises a control register group, the control register group takes the output data of the comparator module as the input data of the control register group, the output of the control logic is taken as a control signal of a level control switch of a lower polar plate in the capacitor array module, and the level control switch can overturn the level of the lower polar plate of the capacitor array module, so that correct reference voltage is selected.
The embodiment of the application adopts the isolating switch S pcThe highest capacitor 64C upAnd a second highest capacitor 32C upIsolating, isolating switch S ncThe highest capacitor 64C unAnd a second highest capacitor 32C unIsolated so as to allow the highest bit capacitance to roll over as little as possible in the designed conversion scheme.
Since the capacitor array switching scheme is a fully differential and uniform structure, the operation of the two capacitor arrays is complementary, and thus this example will only discuss V for simplicity ip>VinThe case (1).
Fig. 3 shows a flow diagram of a level shifting method, which may comprise the steps of:
Step S101: in the sampling phase, S is set p8＝gnd，Sp7＝……＝Sp0＝Vcm，VDACP(1)＝Vip，Sn8＝gnd，Sn7＝……＝Sn0＝Vcm，VDACN(1)＝Vin。
Step S102: and (4) judging whether the VDACP (1) is larger than the VDACN (1).
Step S103: if VDACP (1) is greater than VDACN (1), S n8＝Vcm，Sn7＝……＝Sn0＝Vref。
Step S104: and (4) judging whether the VDACP (2) is larger than the VDACN (2).
Step S105: if VDACP (2) is greater than VDACN (2), S n8＝Vref，Sn7＝……＝Sn0＝Vref。
Step S106: s pcAnd (5) disconnecting.
Step S107: and judging whether the VDACP (j) is larger than the VDACN (j).
Step S108: if VDACP (j) is greater than VDACN (j), S p(9-j)＝gnd。
Step S109: if VDACP (j) is less than or equal to VDACN (j), S p(9-j)＝Vref。
Step S110: it is determined whether j is greater than 8.
Step S111: if j is greater than 8, determine whether VDACP (9) is greater than VDACN (9).
Step S112: if VDACP (9) is greater than VDACN (9), S n0＝Vcm，SP0＝gnd。
Step S113: if VDACP (9) is less than or equal to VDACN (9), S n0＝Vcm。
Step S114: if VDACP (2) is less than or equal to VDACN (2), S n8＝Vcm，Sn7＝……＝Sn0＝Vcm。
Step S115: s pcAnd (5) disconnecting.
Step S116: and judging whether the VDACP (j) is larger than the VDACN (j).
Step S117: if VDACP (j) is greater than VDACN (j), S p(9-j)＝gnd。
Step S118: if VDACP (j) is less than or equal to VDACN (j), S p(9-j)＝Vref。
Step S119: it is determined whether j is greater than 8.
Step S120: if j is greater than 8, determine whether VDACP (9) is greater than VDACN (9).
Step S121: if it is not VDACP (9) is greater than VDACN (9), S n0＝Vref。
Step S122: if VDACP (9) is less than or equal to VDACN (9), S n0＝gnd。
As can be seen from the above analysis, when j is 1, the comparator performs the comparison of the first bit without converting any capacitance. Subsequently, the lower plate of the capacitor array receiving the lower input voltage is switched to the sequence V cmVref.....Vref]The corresponding upper plate voltage rises by V refHowever, the capacitor array receiving the higher input voltage remains unchanged.
When the sampling level is low level, in the sampling stage, the lower electrode plates of the highest-order capacitors of the P-end capacitor array and the N-end capacitor array are initialized to gnd, and other capacitors are initialized to V cmThat is, in the capacitor array module, the lower plate is initialized to [ gnd V ] cm......Vcm]。
The input analog signal is sampled to the upper plate while S pcAnd S ncAnd (5) closing.
According to the assumption V ip>VinThe first digital code D1 is 1, so VDACP (1) is larger than VDACN (1), and the bottom plate switch S is set to the bottom plate switch S n8Is connected to V cmAnd the lower polar plate switch S n7～Sn0Is connected to V refDue to all lower plates rising by V refV2 however the capacitance of the upper plate remains unchanged DACNAscending V ref/2。
Based on the result of the MSB-1 bit, the corresponding voltage will rise or fall V ref/4. When V is DACP>VDACND2 ═ 1, bottom plate switch S n8Is connected to V refThe sequence of lower plates is converted into [ V ] refVref....Vref]，VDACNAscending V ref(ii)/4; otherwise, D2 is equal to 0, and the bottom plate switch S n7～Sn0Is connected to V cmThe sequence of lower plates is converted into [ V ] cmVcm......Vcm]，VDACNDescent V ref/4。
Then, S pcIs disconnected, thereby P end 64C upDisconnected from the rest of the capacitor and maintained in this state until the 10 th bit conversion process is completed, at which time the bottom plate switch S p7～Sp0Is connected to V cm。
For the 4 th bit conversion, when D3 is 1, the bottom plate switch S p6From V cmSwitch to gnd, otherwise, bottom plate switch S p6From V cmConversion to V refThis can give rise to V DACP±Vref(iii) a variation of/8.
The 5 th to 9 th bits are switched in a similar manner to the 4 th bit, and thus, the bottom plate switch S p5～Sp0Sequentially from V according to previous results cmConversion to V refOr gnd.
For an SAR ADC with N (N is more than or equal to 5) bits, the conversion process of the j bit (j is more than or equal to 4 and less than or equal to N-1) can be completed by a similar method.
The conversion process of the 10 th bit can refer to the results of the first two bits and the result of the 9 th bit.
Since the 64C capacitor of DACP is disconnected from other capacitors, the P-side capacitor array cannot generate V refVoltage change amount of/512.
the method of obtaining L SB (L east Significant Bit) can be divided into two cases.
Assume that the N-terminal capacitor array holds V after the first three bits transition refVref......Vref]And V is DACP>VDACNLower polar plate switch S n0Is converted to V cmAt the same time S p0Is also converted to gnd, V DACNBy lowering V ref512 and V DACPReduce V ref/256，VDACNCompared with V DACPGo up and rise to V ref/512, otherwise, the lower polar plate S n0Is connected to V cmThereby V DACNDown is V ref/512。
DACN holds V after the first three-bit transition is over cmVcm......Vcm]Provided that V is DACP>VDACNLower polar plate S n0Is converted to V refAnd V DACNAscending V ref/512, otherwise S n0Is converted to gnd and V DACNDescent V ref/512。
fig. 4 shows a comparison diagram of energy consumption simulation results, and it can be seen that the energy consumption MAT L AB modeling analysis results of several different conversion schemes in fig. 4 are compared, and the capacitor array conversion method provided in the embodiment of the present application has lower energy consumption, and for a 10-bit SAR ADC, the energy consumption is only 6.9CV ref 2About 99.5% energy is saved compared to the conventional structure.
As can be seen from the above embodiments, the embodiments of the present application are based on the hybrid conversion scheme, and the first three bits of conversion of the SAR ADC do not consume energy; the upper electrode plate between the highest-order capacitor and the second highest-order capacitor of the P-end capacitor array is connected with the P-end isolating switch, and the upper electrode plate between the highest-order capacitor and the second highest-order capacitor of the N-end capacitor array is connected with the N-end isolating switch, so that after the conversion of the first three positions is finished, the first two positions are isolated from the rest capacitors for the highest-order capacitor at one end of the capacitor array participating in the turnover, the capacitor number of the capacitor array in the subsequent conversion process is reduced, and the power consumption is reduced. In the embodiment of the application, the C-2C structure is used for replacing the lowest two unit capacitors, so that the overall capacitance value of the capacitor array is reduced by half, and the overall conversion energy is reduced by less capacitors; further, the reduction of the number of capacitors brought by the optimization of the capacitor array optimizes the area and power consumption of the whole SAR ADC.
Since the above embodiments are all described by referring to and combining with other embodiments, the same portions are provided between different embodiments, and the same and similar portions between the various embodiments in this specification may be referred to each other. And will not be described in detail herein.
It is noted that, in this specification, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a circuit structure, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such circuit structure, article, or apparatus. Without further limitation, the presence of an element identified by the phrase "comprising an … …" does not exclude the presence of other like elements in a circuit structure, article or device comprising the element.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims. The above-described embodiments of the present application do not limit the scope of the present application.
Claims (7)
1. A low power analog to digital converter, comprising:
The sampling switch module comprises a first grid voltage bootstrap switch and a second grid voltage bootstrap switch, wherein the first grid voltage bootstrap switch inputs a P-end analog signal, and the second grid voltage bootstrap switch inputs an N-end analog signal;
The capacitor array module comprises a P-end capacitor array and an N-end capacitor array which are symmetrically distributed, wherein an upper electrode plate between the highest-order capacitor and the next-highest-order capacitor of the P-end capacitor array is connected with a P-end isolating switch, and an upper electrode plate between the highest-order capacitor and the next-highest-order capacitor of the N-end capacitor array is connected with an N-end isolating switch;
The same-direction end of the comparator module is connected with the tail end capacitor of the P-end capacitor array, and the reverse end of the comparator module is connected with the tail end capacitor of the N-end capacitor array;
And the digital control logic module is connected with the output end of the comparator module and is used for overturning the level of the lower electrode plate of the capacitor array module according to the output data of the comparator module.
2. The low power consumption analog-digital converter according to claim 1, wherein the P-side capacitor array comprises a first capacitor array and a second capacitor array, the capacitors of the first capacitor array are arranged between the second highest order capacitor and the unit capacitor according to binary weight, the second capacitor array is a capacitor array of a C-2C structure, and the tail end of the first capacitor array is connected with the head end of the second capacitor array.
3. The low power consumption analog-to-digital converter according to claim 2, wherein the first capacitor array comprises a unit capacitor Cup, and the second capacitor array comprises a unit capacitor Cup, two unit capacitors 2Cup, and a dummy capacitor Cdp.
4. The ADC of claim 3, wherein the upper plates of two unit capacitors (2 Cup) in the second capacitor array are connected to the upper plate of the P-end capacitor array, the upper plates of the unit capacitors (Cup) and the dummy capacitors (Cdp) in the second capacitor array are connected to the lower plate of the P-end capacitor array, the unit capacitors (Cup) in the second capacitor array are used for controlling the level control switch of the lower plate of the P-end capacitor array, and the dummy capacitors in the second capacitor array are used for controlling the level control switch of the lower plate of the lower position of the P-end capacitor array.
5. The ADC of claim 3, wherein the unit capacitor Cup and dummy capacitor Cdp have the same size.
6. The ADC of claim 3, wherein the P-side capacitor array is connected with a level control switch from the lower plate of the highest capacitor to the lower plate of the dummy capacitor Cdp.
7. The ADC of claim 6, wherein the level control switch is connected to Vref terminal or Vcm terminal or gnd terminal.
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