CN113258931B - SAR ADC circuit - Google Patents

SAR ADC circuit Download PDF

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CN113258931B
CN113258931B CN202110650602.1A CN202110650602A CN113258931B CN 113258931 B CN113258931 B CN 113258931B CN 202110650602 A CN202110650602 A CN 202110650602A CN 113258931 B CN113258931 B CN 113258931B
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capacitor
array module
dac
electrically connected
switches
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CN113258931A (en
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刘森
李建平
刘兴龙
罗建富
符韬
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Micro Niche Guangzhou Semiconductor Co Ltd
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Micro Niche Guangzhou Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

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Abstract

The invention provides an SAR ADC circuit, which comprises a sampling switch circuit, a first DAC capacitor array module, a second DAC capacitor array module, a comparator and a logic control circuit, by additionally extending and introducing a first DAC capacitor array module in the SAR ADC circuit, and because the capacitance value of the capacitance corresponding to the weight bit of the capacitance in the first DAC capacitance array module is the capacitance value of the capacitance corresponding to the lowest weight bit in the second DAC capacitance array module, so that the actual output of the comparator corresponding to the lowest weight bit in the second DAC capacitor array module can be corrected by the first DAC capacitor array module, and may derive the comparator output to a 0.5LSB weight that the second DAC capacitor array module does not have, therefore, the bottleneck problem of the SAR ADC with high integration level, high speed and high precision in design can be solved, the design difficulty of the comparator is greatly reduced, and the overall conversion precision of the SAR ADC is directly improved.

Description

SAR ADC circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an SAR ADC circuit.
Background
With the rapid development of technologies such as integrated circuits, internet of things, sensor networks and the like and the urgent need of people for services such as smart homes, smart medical services and the like, various miniaturized and low-power-consumption sensors are increasingly regarded as bridges for connecting the physical world and various intelligent devices. The sensor can sense various Analog signals of the world, the Analog signals can be converted into Digital signals through an Analog-to-Digital converter (ADC), the Digital signals are sent into a Digital circuit system at the rear end, operation processing can be carried out, and then the control equipment reacts, wherein the ADC is used as an interface of an Analog circuit and a Digital circuit and is an important bridge between the Analog signals and the Digital signals.
Among many types of ADCs, a high-precision Successive Approximation analog-to-digital converter (SAR ADC) has become popular in ADC research due to its excellent performance, such as simple structure, high digitization degree, convenient application, low delay and power consumption, and is also widely applied in various fields, especially to some high-speed high-precision low-power consumption applications, such as MCU.
The main module of the SAR ADC is divided into three parts: the digital control circuit comprises a digital control logic module, a comparator and a DAC capacitor array module. The DAC capacitor array module and the comparator belong to a digital-analog hybrid circuit, and the digital control logic module is a pure digital circuit, wherein the digital circuit mainly plays a role in controlling the on and off of the switch. The digital circuit generally has no precision requirement and only has a speed requirement, and the high-speed requirement can be realized by using a low-threshold short-channel transistor, so the system speed is not limited, but the analog hybrid circuit consisting of a comparator and a DAC capacitor array module has strict requirements on speed and precision, because the speed and the precision of the whole ADC system are determined, but the speed and the precision are generally spearheads, and a long time is needed to establish if the high-precision signal is used.
With the requirements of applications, the requirements on the accuracy and speed of the SAR ADC are more and more strict, and the design of the SAR ADC circuit also faces many challenges. For example, in three modules of the SAR ADC, designing a comparator with high speed and high precision is one of the cores of preparing the SAR ADC with high speed and high precision, and is also the main direction of current research, but the high precision means that a signal to be identified by the comparator is very small, so that the comparator is required to have a large gain, the high speed means that the comparison time of the comparator is very short, the bandwidth of the preamplifier realizing the high gain is inevitably reduced, especially in the comparison process of a low weight bit, the signal equivalent to the input end of the comparator is very weak, and the influence of noise is considered, so in the design, the gain, the bandwidth and the noise of the comparator must be optimized, the design difficulty is greatly improved, the corresponding current consumption and the chip area are also increased, and the design becomes a bottleneck of designing the SAR ADC with high integration level, high speed and high precision.
Therefore, it is necessary to provide a new SAR ADC circuit.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a SAR ADC circuit for solving the bottleneck problem encountered in the prior art for manufacturing a SAR ADC with high integration, high speed and high precision.
To achieve the above and other related objects, the present invention provides a SAR ADC circuit, comprising:
a sampling switch circuit, the first end of which inputs a differential input signal VipA differential input signal V is input to the second end of the sampling switch circuitin；
A first DAC capacitor array module, a first end of the first DAC capacitor array module being electrically connected to the third end of the sampling switch circuit, a second end of the first DAC capacitor array module being electrically connected to the fourth end of the sampling switch circuit;
a second DAC capacitor array module, wherein a first end of the second DAC capacitor array module is electrically connected with a third end of the first DAC capacitor array module, a second end of the second DAC capacitor array module is electrically connected with a fourth end of the first DAC capacitor array module, and a capacitance value of a capacitor corresponding to a weight bit of a capacitor in the first DAC capacitor array module is a capacitance value of a capacitor corresponding to a lowest weight bit in the second DAC capacitor array module;
a comparator, a first terminal of the comparator being electrically connected to the third terminal of the second DAC capacitor array module, a second terminal of the comparator being electrically connected to the fourth terminal of the second DAC capacitor array module;
and the first end of the logic control circuit is electrically connected with the third end of the comparator, the second end of the logic control circuit is electrically connected with the fifth ends of the first DAC capacitor array module and the second DAC capacitor array module respectively, and the third end of the logic control circuit is electrically connected with the sixth ends of the first DAC capacitor array module and the second DAC capacitor array module respectively.
Optionally, the first DAC capacitive array module comprises:
the first capacitor bank comprises a plurality of first capacitors, and the first end of each first capacitor is electrically connected with the third end of the sampling switch circuit;
first switchA switch group including a plurality of first switches, wherein a first end of each first switch is electrically connected to a second end of the corresponding first capacitor, and a second end of each first switch is selectively connected to a ground level VGNDOr reference level VREF；
The second capacitor group comprises a plurality of second capacitors, and the first end of each second capacitor is electrically connected with the fourth end of the sampling switch circuit;
a second switch group including a plurality of second switches, and a first terminal of each of the second switches is electrically connected to a second terminal of the corresponding second capacitor, and a second terminal of each of the second switches is selectively connected to a ground level VGNDOr reference level VREF。
Optionally, the parameters of the first capacitor and the second capacitor are the same, and the capacitance values of the capacitors corresponding to the weight bits of the first capacitor and the second capacitor are the capacitance values of the capacitors corresponding to the lowest weight bit in the second DAC capacitor array module.
Optionally, n first capacitors and n second capacitors are included, and n is an odd number.
Optionally, the second DAC capacitive array module includes:
a third capacitor bank, wherein the third capacitor bank comprises a plurality of third capacitors, and a first end of each third capacitor is electrically connected with a third end of the first DAC capacitor array module;
a third switch group including a plurality of third switches, and a first end of each of the third switches is electrically connected to a second end of the corresponding third capacitor, and a second end of each of the third switches is selectively connected to a ground level VGNDOr reference level VREF；
A fourth capacitor bank comprising a plurality of fourth capacitors, wherein a first end of each fourth capacitor is electrically connected to the fourth end of the first DAC capacitor array module;
a fourth switch group, the fourth switch groupThe four-switch group comprises a plurality of fourth switches, the first end of each fourth switch is electrically connected with the second end of the corresponding fourth capacitor, and the second end of each fourth switch is selectively connected to the ground level VGNDOr reference level VREF。
Optionally, the third capacitor and the fourth capacitor have the same parameters, and the capacitance values of the capacitors corresponding to the binary weight bits are respectively Cu、Cu、2Cu……2N-1CuN +1 capacitors, where N is less than or equal to 18.
Optionally, the first DAC capacitor array module and the second DAC capacitor array module are capacitive array modules or capacitance-resistance combined array modules.
Optionally, the sampling switch circuit comprises:
a first input sampling switch, a first end of which inputs the differential input signal Vip；
A second input sampling switch, the first end of which inputs the differential input signal Vin。
As described above, the SAR ADC circuit of the present invention comprises the sampling switch circuit, the first DAC capacitor array module, the second DAC capacitor array module, the comparator and the logic control circuit, the first DAC capacitor array module is additionally extended and introduced into the SAR ADC circuit, and since the capacitance value of the capacitor corresponding to the weight bit of the capacitor in the first DAC capacitor array module is the capacitance value of the capacitor corresponding to the lowest weight bit in the second DAC capacitor array module, the actual output of the comparator corresponding to the lowest weight bit in the second DAC capacitor array module can be corrected by the first DAC capacitor array module, and the output of the comparator corresponding to the weight of 0.5LSB which is not included in the second DAC capacitor array module can be derived, so that the bottleneck problem encountered in the design of the SAR ADC with high integration, high speed and high precision can be solved, and the design difficulty of the comparator is greatly reduced, the integral conversion precision of the SAR ADC is directly improved.
Drawings
Fig. 1 is a block diagram showing the general structure of the SAR ADC circuit according to the embodiment of the present invention.
Fig. 2 is a schematic diagram showing a specific structure of the SAR ADC circuit according to the embodiment of the present invention.
Fig. 3 is a diagram illustrating a weight output mapping relationship according to an embodiment of the present invention.
Description of the element reference numerals
1-a sampling switch circuit; 2-a first DAC capacitive array module; 3-a second DAC capacitive array module; 4-a comparator; 5-a logic control circuit; 111-a first input sampling switch; 112-a second input sampling switch; 211-a first capacitor bank; 221-a first switch set; 212-a second capacitor bank; 222-a second switch set; 311-a third capacitor bank; 321-a third switch group; 312-a fourth capacitor bank; 322-fourth switch set.
Detailed Description
For a conventional SAR ADC circuit, in the conversion process, the comparison of the weight of the last bit, namely the lowest weight bit (1 LSB weight) is the most critical, once the bit comparison is wrong, the precision of the whole SAR ADC circuit is directly reduced by 6dB, and the corresponding effective output is reduced by 1 bit. The reasons why it is error prone include: firstly, the voltage difference between the positive end and the negative end of the comparator to be analyzed corresponding to the lowest weight bit is minimum (near the weight of 1 LSB), and the comparator is easily interfered by noise or other non-ideal factors; secondly, the voltage difference corresponding to the lowest weight bit is too small, the comparator is established too slowly, and the comparator is easy to enter a metastable state.
Therefore, the application provides a novel SAR ADC circuit, by additionally extending and introducing the first DAC capacitor array module in the SAR ADC circuit, and because the capacitance value of the capacitance corresponding to the weight bit of the capacitance in the first DAC capacitor array module is the capacitance value of the capacitance corresponding to the lowest weight bit in the second DAC capacitor array module, the actual output of the comparator corresponding to the lowest weight bit in the second DAC capacitor array module can be corrected through the first DAC capacitor array module, that is, by additionally adding the lowest weight bit, that is, in addition to the conventional conversion comparison of the lowest weight bit, adding the same second conversion comparison of the lowest weight bit, and then obtaining the conversion result of the lowest weight bit of the final output according to the comprehensive analysis of the comparison result of the conventional lowest weight bit (1 LSB weight) and the comparison result of the additionally added lowest weight bit, the SAR ADC circuit can even be expanded to be below 1LSB weight, such as 0.5LSB weight, on the conversion result of the lowest weight bit (1 LSB weight), so that the SAR ADC circuit can finish high-precision comparison on the premise of not designing a comparator with a complex structure, and the performance of the SAR ADC circuit with high precision can be realized.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1-2, it should be noted that the drawings provided in the present embodiment are only schematic illustrations of the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, number and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a SAR ADC circuit, which includes a sampling switch circuit 1, a first DAC capacitor array module 2, a second DAC capacitor array module 3, a comparator 4, and a logic control circuit 5.
Wherein, the first end of the sampling switch circuit 1 inputs a differential input signal VipA differential input signal V is input to the second end of the sampling switch circuit 1in(ii) a The first end of the first DAC capacitor array module 2 is electrically connected with the third end of the sampling switch circuit 1, and the second end of the first DAC capacitor array module 2 is electrically connected with the fourth end of the sampling switch circuit 1; the first end of the second DAC capacitor array module 3 is electrically connected with the third end of the first DAC capacitor array module 2, and the second end of the second DAC capacitor array module 3 is electrically connected with the third end of the first DAC capacitor array module 2The fourth end is electrically connected, and the capacitance value of the capacitance corresponding to the weight bit of the capacitance in the first DAC capacitance array module 2 is the capacitance value of the capacitance corresponding to the lowest weight bit in the second DAC capacitance array module 3; a first terminal of the comparator 4 is electrically connected with a third terminal of the second DAC capacitor array module 3, and a second terminal of the comparator 4 is electrically connected with a fourth terminal of the second DAC capacitor array module 3; the first end of the logic control circuit 5 is electrically connected with the third end of the comparator 4, the second end of the logic control circuit 5 is electrically connected with the fifth ends of the first DAC capacitor array module 2 and the second DAC capacitor array module 3, respectively, and the third end of the logic control circuit 5 is electrically connected with the sixth ends of the first DAC capacitor array module 2 and the second DAC capacitor array module 3, respectively.
As an example, the sampling switch circuit 1 includes:
a first input sampling switch 111, a first end of the first input sampling switch 111 inputting the differential input signal Vip；
A second input sampling switch 112, a first end of the second input sampling switch 112 inputs the differential input signal Vin。
As an example, the first DAC capacitive array module 2 and the second DAC capacitive array module 3 are capacitive array modules or capacitance-resistance combination type array modules.
Specifically, in this embodiment, in order to form the SAR ADC circuit with high precision, the first DAC capacitor array module 2 and the second DAC capacitor array module 3 both preferably adopt a capacitive array module, but are not limited thereto, and the first DAC capacitor array module 2 and the second DAC capacitor array module 3 may also adopt a capacitance-resistance combination type array module as required, which is not limited herein.
As an example, the first DAC capacitive array module 2 comprises:
a first capacitor group 211, where the first capacitor group 211 includes a plurality of first capacitors, and a first end of each of the first capacitors is electrically connected to a third end of the sampling switch circuit 1;
first switch group221, the first switch group 221 includes a plurality of first switches, and a first end of each of the first switches is electrically connected to a second end of the corresponding first capacitor, and a second end of each of the first switches is selectively connected to a ground level VGNDOr reference level VREF；
A second capacitor group 212, where the second capacitor group 212 includes a plurality of second capacitors, and a first end of each of the second capacitors is electrically connected to a fourth end of the sampling switch circuit 1;
a second switch set 222, the second switch set 222 comprising a plurality of second switches, and a first terminal of each of the second switches being electrically connected to a second terminal of the corresponding second capacitor, and a second terminal of each of the second switches being selectively connected to a ground level VGNDOr reference level VREF。
As an example, the second DAC capacitive array module 3 comprises:
a third capacitor bank 311, where the third capacitor bank 311 includes a plurality of third capacitors, and a first end of each of the third capacitors is electrically connected to a third end of the first DAC capacitor array module 2;
a third switch group 321, the third switch group 321 including a plurality of third switches, and a first end of each of the third switches being electrically connected to a second end of the corresponding third capacitor, and a second end of each of the third switches being selectively connected to a ground level VGNDOr reference level VREF；
A fourth capacitor bank 312, wherein the fourth capacitor bank 312 comprises a plurality of fourth capacitors, and a first end of each fourth capacitor is electrically connected to the fourth end of the first DAC capacitor array module 2;
a fourth switch group 322, the fourth switch group 322 comprising a plurality of fourth switches, and a first terminal of each of the fourth switches is electrically connected to a second terminal of the corresponding fourth capacitor, and a second terminal of each of the fourth switches is selectively connected to the ground level VGNDOr reference level VREF。
Specifically, as shown in fig. 2, in the SAR ADC circuit,the sampling switch circuit 1 includes: a first input sampling switch 111 and a second input sampling switch 112, wherein the differential input signal V is input to a first end of the first input sampling switch 111ipThe first terminal of the second input sampling switch 112 inputs the differential input signal Vin. The first capacitor bank 211 in the first DAC capacitor array module 2 comprises a plurality of the first capacitors, the third capacitor bank 311 in the second DAC capacitor array module 3 comprises a plurality of the third capacitors, and the upper plates of the first and third capacitors are electrically connected to the second terminal of the first input sampling switch 111 and the first input terminal, i.e., P terminal, of the comparator 4, respectively; the second capacitor bank 212 of the first DAC capacitor array module 2 comprises a plurality of the second capacitors, the fourth capacitor bank 312 of the second DAC capacitor array module 3 comprises a plurality of the fourth capacitors, and the upper plates of the second and fourth capacitors are electrically connected to the second terminal of the second input sampling switch 112 and the second input terminal of the comparator 4, i.e., N terminals, respectively. The first switch group 221 in the first DAC capacitor array module 2 comprises a plurality of first switches, and a first end of each first switch is connected to a lower plate of the corresponding first capacitor, and a second end of each first switch is selectively connected to a ground level VGNDOr reference level VREFThe third switch group 321 in the second DAC capacitor array module 3 comprises a plurality of third switches, and a first end of each third switch is connected to a lower plate of the corresponding third capacitor, and a second end of each third switch is selectively connected to a ground level VGNDOr reference level VREF. The logic control circuit 5 is connected to a third end, namely an output end, of the comparator 4, a second end of the logic control circuit 5 is electrically connected to fifth ends of the first DAC capacitor array module 2 and the second DAC capacitor array module 3, respectively, a third end of the logic control circuit 5 is electrically connected to sixth ends of the first DAC capacitor array module 2 and the second DAC capacitor array module 3, respectively, so as to output a digital signal based on a comparison result output by the comparator 4 and generate a signal corresponding to the first DAC capacitor array moduleThe control signals of the relevant switches in the capacitor array module 2 and the second DAC capacitor array module 3 are used for sampling and successive comparison control to adjust the switch states of the corresponding switches, so as to approach the input voltage successively.
As an example, the parameters of the first capacitor and the second capacitor are the same, and the capacitance values of the capacitors corresponding to the weight bits of the first capacitor and the second capacitor are the capacitance values of the capacitors corresponding to the lowest weight bits in the second DAC capacitor array module 3.
As an example, the parameters of the third capacitor and the fourth capacitor are the same, and the capacitance values of the capacitors corresponding to the binary weight bits are respectively Cu、Cu、2Cu……2N-1CuN +1 capacitors, where N is less than or equal to 18.
Specifically, referring to fig. 2, in this embodiment, the second DAC capacitor array module 3 in the SAR ADC circuit is a 4-bit DAC capacitor array module, and preferably, the parameters of the third capacitor and the fourth capacitor are the same, and the capacitance values of the capacitors corresponding to binary weight bits are C respectivelyu、Cu、2Cu、4CuAnd 4 capacitors. The first DAC capacitor array module 2 introduces an extra 5-bit capacitor value which is the lowest weight bit in the second DAC capacitor array module 3, namely the capacitor value CuThe first DAC capacitor array module 2 is used as an extension module of the second DAC capacitor array module 3 to form an extension bit, so that a capacitor of the lowest weight bit of 5 units can be additionally added to the corresponding circuit. The parameters of the first capacitor and the second capacitor are preferably the same, and the first capacitor and the second capacitor preferably comprise odd numbers of the first capacitor and the second capacitor, so that the design of the SAR ADC circuit with high precision is realized, and simultaneously the design of the SAR ADC circuit with high speed is realized. In the embodiment, the first capacitor and the second capacitor may not be too many or too few, too few results in an insignificant calibration effect, and too much takes too much conversion time, so that in the first DAC capacitor array module 2, the first capacitor and the second capacitor respectively have the same capacitance value and occupy too much conversion timeIs CuThe number of the first capacitors and the second capacitors is not limited to this, and may also be 3, 7, etc., and the second DAC capacitor array module 3 may also adopt DAC capacitor array modules of other bits, which is not limited herein.
Regarding the application of the SAR ADC circuit, when the first input sampling switch 111 and the second input sampling switch 112 are opened during sampling, the differential input signal VipThe first capacitance corresponding to the first DAC capacitance array module 2 and the third capacitance corresponding to the second DAC capacitance array module 3 are sampled to the upper plate, that is, the DACP upper plate. The differential input signal VinThe first ends of the second capacitor corresponding to the first DAC capacitor array module 2 and the fourth capacitor corresponding to the second DAC capacitor array module 3, that is, the upper plate of DACN, are sampled. The DACP upper electrode plate is electrically connected with the input P end corresponding to the comparator 4, the DACN upper electrode plate is electrically connected with the input N end corresponding to the comparator 4, and the first DAC capacitor array module 2 and the second DAC capacitor array module 3 are used for comparing the differential input signal VipAnd said differential input signal VinSampling is performed.
After the sampling is finished, the first input sampling switch 111 and the second input sampling switch 112 are turned off, and the differential input signal V is obtainedipAnd said differential input signal VinThe charges are stored in the first capacitor group 211, the second capacitor group 212, the third capacitor group 311, and the fourth capacitor group 312, and the first capacitor group 211 and the third capacitor group 311 output VpTo the first, P, terminal of said comparator 4; the second capacitor bank 212 and the fourth capacitor bank 312 output VnTo the second, N, terminal of the comparator 4, and the comparator 4 couples the output signal VpAnd VnCarrying out the first comparison, recording the comparison result as D1, and then controlling the connection of the high weight bit in the second DAC capacitor array module 3 according to the comparison result D1, that is, the capacitance value is 4CuE.g. D1= when the DACP voltage is greater than the DACN voltage1, meaning that the P terminal of the comparator 4 is higher than the N segment, the comparator 4 outputs the Most Significant Bit (MSB) of 1, and the capacitance value in the fourth capacitor bank 312 corresponding to the N terminal is 4CuThe corresponding switch SW1 is conductively connected to VREFIf the capacity value is 4CuAfter the charging of the lower electrode plate of the capacitor is finished, the voltage of the DACN end changes towards the positive direction, then the comparator 4 continues to carry out comparison, the comparison result is output and recorded as D2, the switch SW2 is controlled according to the output of the comparison result D2 of the comparator 4, and the capacitance value is changed to be 2CuThen according to the capacitance value of 2CuAfter the capacitance connection is changed, the switch SW3 is controlled by the output comparison result D3 of the comparator 4 to change the capacitance value to CuThen the comparator 4 compares again, and the comparison result of this time output is recorded as D4 as the lowest weight bit result, i.e. the process of gradually changing from the high weight to the low weight is obtained, and the process is finished by changing to this point according to the conventional design. However, in the embodiment, due to the existence of the first DAC capacitor array module 2, the conversion can still continue downwards to change the connection manner of the additionally added 5-bit capacitor, so that the 5-bit capacitor in the extension bit can also obtain the comparison output corresponding to the comparator 4, wherein the comparison outputs can be respectively marked as E1, E1, E3, E4, and E5.
Based on the above analysis, the output result D4 in the second DAC capacitor array module 3 should be the result of the lowest weight bit (1 LSB weight), but the comparison of this weight bit is prone to error due to noise and the limitations of the comparison speed and accuracy of the comparator 4. So that the presence of the extension bits, i.e. the 5 lowest weight bits (1 LSB weights) in the first DAC capacitor array module 2 can be used to verify and complement the result of the lowest weight bits to suppress the effect of noise by 5 additional switching comparisons.
Experiments prove that the signal-to-noise ratio of the SAR ADC circuit of the present embodiment can be improved by about 7dB, and random errors can be reduced, and at the same time, the possibility of metastable state of the comparator 4 can be greatly reduced. Therefore, the final more accurate low-bit weight bit conversion output can be obtained by using the results E1-E5 of the extension bit in the first DAC capacitor array module 2 and the final bit result D4 of the second DAC capacitor array module 3, and even according to the results of E1, E2, E3, E4 and E5, the 0.5LSB weight lower than 1LSB weight can be deduced. The corresponding relationship is shown in FIG. 3.
The above table is used for verifying the output corresponding value of the lowest weight bit 1LSB weight according to probability distribution statistics and deducing the output value corresponding to the 0.5LSB weight, and according to the results of the above table, not only the actual weight output corresponding to the 1LSB weight can be corrected, but also the precision can be improved to the decimal 0.5LSB weight, so that the more reliable and higher-precision output of the SAR ADC circuit can be realized.
In summary, the SAR ADC circuit of the present invention includes the sampling switch circuit, the first DAC capacitor array module, the second DAC capacitor array module, the comparator and the logic control circuit, the first DAC capacitor array module is additionally extended and introduced into the SAR ADC circuit, and since the capacitance value of the capacitor corresponding to the weight bit of the capacitor in the first DAC capacitor array module is the capacitance value of the capacitor corresponding to the lowest weight bit in the second DAC capacitor array module, the actual output of the comparator corresponding to the lowest weight bit in the second DAC capacitor array module can be corrected by the first DAC capacitor array module, and the output of the comparator corresponding to the weight of 0.5LSB that the second DAC capacitor array module does not have can be derived, so that the bottleneck problem encountered in the design of the SAR ADC with high integration, high speed and high precision can be solved, and the design difficulty of the comparator is greatly reduced, the integral conversion precision of the SAR ADC is directly improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (6)

1. A SAR ADC circuit, comprising:
a sampling switch circuit, the first end of which inputs a differential input signal VipA differential input signal V is input to the second end of the sampling switch circuitin；
A first DAC capacitor array module, a first end of which is a first input port and a third end of which is an output differential input signal VipIs electrically connected with the second end of the first DAC capacitor array module, i.e. the second input port, and the fourth end of the sampling switch circuit, i.e. the output differential input signal VinIs electrically connected with the fourth output port; wherein the first DAC capacitive array module comprises:
the first capacitor bank comprises a plurality of first capacitors, and the first end of each first capacitor is electrically connected with the third end of the sampling switch circuit;
a first switch group including a plurality of first switches, and a first end of each of the first switches is electrically connected to a second end of the corresponding first capacitor, and a second end of each of the first switches is selectively connected to a ground level VGNDOr reference level VREF；
The second capacitor group comprises a plurality of second capacitors, and the first end of each second capacitor is electrically connected with the fourth end of the sampling switch circuit;
a second switch group including a plurality of second switches, and a first terminal of each of the second switches is electrically connected to a second terminal of the corresponding second capacitor, and a second terminal of each of the second switches is selectively connected to a ground level VGNDOr reference level VREF；
A second DAC capacitive array module, a first end of the second DAC capacitive array module being electrically connected to a first input port of the third DAC capacitive array module being electrically connected to a third output port of the first DAC capacitive array module being connected to the first end of the first capacitor, a second end of the second DAC capacitive array module being electrically connected to a second input port of the fourth DAC capacitive array module being electrically connected to a fourth output port of the first DAC capacitive array module being connected to the first end of the second capacitor, wherein the second DAC capacitive array module comprises:
a third capacitor bank, wherein the third capacitor bank comprises a plurality of third capacitors, and a first end of each third capacitor is electrically connected with a third end of the first DAC capacitor array module;
a third switch group including a plurality of third switches, and a first end of each of the third switches is electrically connected to a second end of the corresponding third capacitor, and a second end of each of the third switches is selectively connected to a ground level VGNDOr reference level VREF；
A fourth capacitor bank comprising a plurality of fourth capacitors, wherein a first end of each fourth capacitor is electrically connected to the fourth end of the first DAC capacitor array module;
a fourth switch group including a plurality of fourth switches, and a first terminal of each of the fourth switches is electrically connected to a second terminal of the corresponding fourth capacitor, and a second terminal of each of the fourth switches is selectively connected to a ground level VGNDOr reference level VREF；
The capacitance value of the capacitor corresponding to the weight position of the first capacitor in the first capacitor bank is the capacitance value of the third capacitor corresponding to the lowest weight position in the third capacitor bank, and the capacitance value of the capacitor corresponding to the weight position of the second capacitor in the second capacitor bank is the capacitance value of the fourth capacitor corresponding to the lowest weight position in the fourth capacitor bank;
a comparator, a first terminal of which is a P input port, is electrically connected to a third terminal of the second DAC capacitor array module, i.e., a third output port connected to the first terminal of the third capacitor, and a second terminal of which is an N input port is electrically connected to a fourth terminal of the second DAC capacitor array module, i.e., a fourth output port connected to the first terminal of the fourth capacitor;
a logic control circuit, a first end of the logic control circuit, namely a first input port, is electrically connected to a third end of the comparator, namely an output port, a second end of the logic control circuit, namely a second output port, is electrically connected to fifth ends of the first and second DAC capacitor array modules, namely the first and third switches, respectively, and a third end of the logic control circuit, namely a third output port, is electrically connected to sixth ends of the first and second DAC capacitor array modules, namely the second and fourth switches, respectively, so as to output a digital signal based on a comparison result of the comparator, and generate a control signal corresponding to a relevant switch in the first and second DAC capacitor array modules.
2. The SAR ADC circuit of claim 1, wherein: the parameters of the first capacitor and the second capacitor are the same, and the capacitance values of the capacitors corresponding to the weight bits of the first capacitor and the second capacitor are the capacitance values of the capacitors corresponding to the lowest weight bit in the second DAC capacitor array module.
3. The SAR ADC circuit of claim 1, wherein: the circuit comprises n first capacitors and n second capacitors, and n is an odd number.
4. The SAR ADC circuit of claim 1, wherein: the parameters of the third capacitor and the fourth capacitor are the same, and the capacitance values of the capacitors corresponding to the binary weight bits are respectively Cu、Cu、2Cu……2N-1CuN +1 capacitors, where N is less than or equal to 18.
5. The SAR ADC circuit of claim 1, wherein: the first DAC capacitor array module and the second DAC capacitor array module are capacitance type array modules or capacitance resistance combination type array modules.
6. The SAR ADC circuit of claim 1, wherein the sampling switch circuit comprises:
a first input sampling switch, a first end of which inputs the differential input signal Vip；
A second input sampling switch, the first end of which inputs the differential input signal Vin。
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