TWI521888B - Successive approximation register analog-to-digital converter and associate control method - Google Patents

Description

Continuous approximation temporary analog analog digital converter and control method thereof

The present invention relates to a Continuous Approximation Register Analog-to-Digital Converter (SAR ADC), and more particularly to a continuous approximation temporary analog analog digital conversion that can perform background calibration. And its control method.

In the continuous approximation of the temporary analog analog-to-digital converter, the capacitance value of each bit capacitor in the bit capacitor array may be deviated from the original design due to process error, ambient temperature variation or incomplete symmetry/matching. The capacitance value causes an error in the digital output, which in turn affects the linearity of the successive approximation of the temporary analog digital converter. In order to solve this problem, it is usually necessary to calibrate the bit capacitance. However, some current calibration methods have some problems, such as affecting the working speed of the continuous approximation temporary analog digital converter, or the need to limit the input signal. The swing is prevented from exceeding the coding range of the analog digital converter...etc., thus causing confusion for the designer and the operational flaws.

Therefore, one of the objects of the present invention is to provide a continuous approximation temporary analog digital converter and a control method thereof, wherein the method of calibrating the bit capacitance can be a complete background calibration without affecting the continuous approximation. The operating speed of the analog analog converter; in addition, it is not necessary to limit the swing of the input signal, that is, the input signal is allowed to be full Input to increase the voltage range of the input signal that can be processed.

According to an embodiment of the invention, a continuous approximation temporary analog digital converter includes a first bit capacitor array, a second bit capacitor array, a comparator, and a processing circuit. The first bit capacitor array is configured to receive a first input signal, wherein the first bit capacitor array includes a plurality of first bit capacitors, and at least one high bit capacitor in the first bit capacitor array is The plurality of secondary capacitors are configured, and each of the secondary capacitors is selectively connected to a first reference signal, a second reference signal or a common mode voltage by a corresponding switch; the second bit capacitor array is configured to receive a a second input signal, wherein the second bit capacitor array comprises a plurality of second bit capacitors, and at least one high bit capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor The comparator is selectively coupled to the first reference signal, the second reference signal, or the common mode voltage; the comparator is coupled to the first bit capacitor array and the second bit capacitor array, And comparing the output of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; the processing circuit is coupled to the comparator, and configured to control the first bit capacitor array and the second Capacitance capacitor array switching element, and generates a digital output scratch pad analog-digital converter of the SAR.

In accordance with another embodiment of the present invention, a method of controlling a continuous approximation temporary analog digital converter is disclosed, wherein the continuous approximation temporary analog digital converter includes a first bit capacitor array and a second bit capacitor The first bit capacitor array is configured to receive a first input signal, wherein the first bit capacitor array includes a plurality of first bit capacitors, and at least one high bit capacitor in the first bit capacitor array is The second sub-capacitor is configured to be selectively connected to a first reference signal, a second reference signal or a common mode voltage by a switch; the second bit capacitor array is used for Receiving a second input signal, wherein the second bit capacitor array comprises a plurality of second bit capacitors, and at least one high bit capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors, and each The secondary capacitor is independently selectively switched by a switch Connected to the first reference signal, the second reference signal, or the common mode voltage; in addition, the method includes: comparing the output of the first bit capacitor array and the second bit capacitor array to generate a comparison signal Determining, according to the comparison signal, a weight value corresponding to each of the first bit capacitors or each of the second bit capacitors, wherein a capacitance value of the at least one high-order capacitor in the first bit capacitor array Corresponding weight values are obtained by respectively calibrating the plurality of sub-capacitors, and the weight values corresponding to the capacitance values of the at least one high-order capacitors in the second bit capacitor array are respectively determined by the plurality of The secondary capacitor is calibrated; and based on the comparison signal and the determined plurality of weight values to generate a digital output of the continuous approximation temporary analog digital converter.

In accordance with another embodiment of the present invention, a continuous approximation temporary analog digital converter includes a first bit capacitor array, a second bit capacitor array, a comparator, and a processing circuit. The first bit capacitor array is configured to receive a first input signal, where the first bit capacitor includes a plurality of first bit capacitors, and the at least one high bit capacitor in the first bit capacitor array is formed by a plurality of sub-capacitors; a second bit capacitor array for receiving a second input signal, comprising a plurality of second bit capacitors, wherein at least one high bit capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors; Comparing the output of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; and the processing circuit is coupled to the comparator for controlling the first bit capacitor array and The capacitance of the second bit capacitor array is switched, and an N-bit digital output is generated according to the comparison signal; wherein, in the first bit capacitor array, the capacitance value is greater than a first bit capacitance of a redundant capacitor The capacitor is composed of a plurality of sub-capacitors, and the capacitance of each sub-capacitor is less than a redundant capacitor, wherein the redundant capacitor is defined as a unit capacitor and the plurality of first-bit capacitors in the first-bit capacitor array of The difference between the sum of the capacitance values and the capacitance of the lowest bit capacitance is 2 ^(N-1) times.

100,400‧‧‧Continuous approximation of temporary analog analog converter

110, 410‧‧‧ first bit capacitor array

120, 420‧‧‧ second bit capacitor array

130, 430‧‧‧ comparator

140, 440‧‧‧ multiplier

150, 450‧‧‧ processing circuits

CP00, CN00‧‧‧ unit capacitor

CP0~CP13, CN0~CN13‧‧‧ bit capacitance

_{CP 13,0 ~ CP 13,4, CN 13,0} ~ CN 13,4 ‧‧‧ capacitor Ci

CKS‧‧ switch

Dout‧‧‧ digital output

K‧‧‧ pseudo-random sequence

Vc‧‧‧ control signal

Vip‧‧‧first input signal

Vin‧‧‧second input signal

Vrefp‧‧‧ first reference voltage

Vrefn‧‧‧second reference voltage

V _CM ‧‧‧ Common mode voltage

V _CMP , V _CMN ‧‧‧ endpoint

700~706‧‧‧Steps

1 is a schematic diagram of a continuous approximation temporary analog digital converter in accordance with an embodiment of the present invention.

Figure 2 is a schematic diagram of the background calibration of the primary capacitor during the sampling phase of the continuous approximation temporary analog digital converter shown in Figure 1.

Figure 3 is a schematic diagram of the background calibration of the primary capacitor when the continuous approximation temporary analog digital converter shown in Figure 1 maintains the signal phase.

4 is a schematic diagram of a continuous approximation temporary analog digital converter in accordance with another embodiment of the present invention.

Figure 5 is a schematic diagram of the background calibration of the primary capacitor during the sampling phase of the continuous approximation temporary analog digital converter shown in Figure 4.

Figure 6 is a schematic diagram of the background calibration of the primary capacitor when the continuous approximation temporary analog digital converter shown in Figure 4 maintains the signal phase.

7 is a flow chart of a method of controlling a continuous approximation temporary analog analog-to-digital converter in accordance with an embodiment of the present invention.

In the continuous approximation of the temporary analog analog-to-digital converter, the linearity is limited by the matching degree of the bit capacitance (that is, the degree of capacitance of the bit capacitance described in the prior art deviates from the originally designed capacitance value). Therefore, the conventional design must select a sufficiently large capacitance value to ensure a certain degree of accuracy, and thus needs to be realized with a relatively large area and power. For example, it may be necessary to use four times the area to double the accuracy. Therefore, if you reduce the requirement for bit capacitance matching, you can get four times the area reduction benefit for every two times reduction. . Therefore, in order to reduce the requirement for bit capacitance matching, the continuous approximation of the temporary analog digital converter has adopted some mechanisms for calibrating the bit capacitance to save the area of the capacitor in the wafer and reduce the power of the chip. Consume, increase operating speed, and improve some of the quality metrics of continuous approximation of the temporary analog digital converter, such as Integral Non-Linearity (INL), Differential Non-Linearity (DNL), no parasitic Spurious Free Dynamic Range (SFDR) and Signal-to-Noize & Distortion Ratio (SNDR)...etc.

The continuous approximation temporary analog analog-to-digital converter provided by the invention calibrates the bit capacitance by using a complete background calibration method to accurately know the weight value of each bit capacitance, wherein the weight value is This refers to the ratio of the bit capacitance to the lowest bit capacitance, and since it does not need to interrupt the operation of the digital converter during the calibration process, it can automatically adapt to factors such as changes in the ambient temperature, component aging, etc., so that the capacitance value can be changed. In the case of greatly improving the linearity and dynamic characteristics, the efficiency of the continuous approximation of the temporary analog digital converter is also considered.

In addition, the bit capacitance in the continuous approximation temporary analog digital converter provided by the present invention does not adopt a standard binary capacitance value design, but uses a capacitance value design with a redundant capacitor, and the N-bit continuous approximation is temporarily suspended. In the case of a memory analog converter, the "redundant capacitance" can be defined in the present invention as the difference between the sum of the capacitance values of the unit capacitance and the bit capacitance and the capacitance value of the lowest bit capacitance by 2 ^(N-1) times. Wherein N is preferably a positive integer. In addition, the present invention also splits the high-order capacitor of the continuous approximation analog-type digital converter into a plurality of sub-capacitors, and the capacitance value of each sub-capacitor is smaller than the redundant capacitor, so that the background is performed. There is also no need to limit the swing of the input signal during calibration, that is, the input signal can be full swing input to increase the voltage range of the input signal that can be processed. Details of the implementation of the continuous approximation temporary analog digital converter of the present invention will be detailed below.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a continuous approximation temporary analog digital converter 100 according to an embodiment of the invention. As shown in FIG. 1 , the continuous approximation analog digital converter 100 includes a first bit capacitor array 110 , a second bit capacitor array 120 , a comparator 130 , a multiplier 140 , and a processing circuit 150 . And two unit capacitors CP00 and CN00, wherein the first bit capacitor array 110 includes a plurality of bit capacitors CP0~CP13, and each of the bit capacitors CP0~CP13 can be selectively connected to the first by a switch a reference voltage Vrefp, a second reference voltage Vrefn, and a common mode voltage V _CM , and in this embodiment, the bit capacitances CP10~CP13 are separated into a plurality of sub-capacitors (such as the bit capacitance CP13 shown in FIG. 1) Split into multiple sub-capacitors CP _13,0 , CP _13,1 , CP _13,2 , CP _13,3 , CP _13,4 ), and each sub-capacitor can be independently controlled by a switch Connected to the first reference voltage Vrefp, the second reference voltage Vrefn, and the common mode voltage V _CM ; the second bit capacitor array 120 includes a plurality of bit capacitors CN0~CN13, and each bit capacitor CN0~CN13 can be used by one The switch is selectively coupled to a first reference voltage Vrefp, a second reference voltage Vrefn, and a common mode voltage V _CM In the embodiment, the bit capacitors CN10~CN13 are separated into a plurality of sub-capacitors (for example, the bit capacitor CN13 shown in FIG. 1 is split into a plurality of sub-capacitors CN13, 0, CN ₁₃ , 1 and CN. ₁₃ , 2, CN ₁₃ , ₃ , CN ₁₃ , ₄ ), and each sub-capacitor can be independently connected to the first reference voltage Vrefp, the second reference voltage Vrefn, and the common mode voltage V by a switch _CM . In one embodiment, the first reference voltage Vrefp is a positive reference voltage, and the second reference voltage Vrefn is a negative reference voltage, which are symmetric with respect to the common mode voltage V _CM , that is, V _CM =0.5 (Vrefp+Vrefn). In addition, the switching of all the switches shown in FIG. 1 is controlled by a plurality of control signals Vc generated by the processing circuit 150.

In this embodiment, the continuous approximation temporary analog digital converter 100 is a 12-bit continuous approximation temporary analog digital converter, that is, the continuous approximation temporary analog digital converter 100 receives the first input signal. The Vip and the second input signal Vin are used to generate a 12-bit digital output Dout. In one embodiment, the first input signal Vip is a positive input voltage, and the second input signal Vin is a negative output voltage, and the two are symmetric to a voltage. Level. In addition, although the first bit capacitor array 110 and the second bit capacitor array 120 shown in FIG. 1 each include 14 bit capacitors, the first bit capacitor array 110 and the second bit capacitor are designed. The number of bit capacitors in array 120 can also be 12 or 13, etc., and these design variations are all within the scope of the present invention.

In the present embodiment, it is assumed that the continuous approximation temporary analog-to-digital converter 100 is an N-bit continuous approximation temporary analog digital converter (N is 12 in the embodiment of FIG. 1), and the first bit capacitor array 110 The number of bit capacitances in the second bit capacitor array 120 is P (P is 14 in the embodiment of FIG. 1), where P needs to be greater than (N-1), and each bit capacitance is labeled C0, C1. C2,..., C(P-1), where C0 is the lowest bit capacitance, and the capacitance values of all other bit capacitors (C1~C(P-1)) are integer multiples of C0. In addition, in this embodiment, part of the high-order capacitor is split into a plurality of secondary capacitors, for example, the bit capacitor Ci is split into M secondary capacitors, that is, . In addition, in the preferred embodiment of the present embodiment, the following three conditions must be met in the design of the capacitor: (1) , that is, the capacitance value of any bit capacitor is not greater than the sum of the capacitance values of all lower bit capacitors; (2) , that is, the sum of the capacitance values of the unit capacitor and the bit capacitor is not less than 2 ^(N-1) times the capacitance value of the lowest bit capacitor; (2) That is, the capacitance value of each sub-capacitor is less than a redundant capacitor, wherein the redundant capacitor is defined as the sum of the capacitance value of the unit capacitor and the bit capacitor and the capacitance value of the lowest bit capacitor 2 ^(N-1) The difference of the double, that is, the redundant capacitance is defined as . In the above symbols, C0 represents the lowest bit capacitance, and Ci represents the capacitance value of the first bit capacitor array 110 or the second bit capacitor array 120 where the capacitance value is the i-th highest bit capacitance.

Referring to the above three conditions, the capacitance values of the bit capacitors in the first bit capacitor array 110 and the second bit capacitor array 120 of the embodiment shown in FIG. 1 can be designed as shown in Table 1 below. The unit of the medium capacitance value is C0:

In Table 1, the redundant capacitor is Therefore, the sub-capacitor after the splitting is only required to be less than 297*C0. The following Table 2 is a split example of C13, C12, C11, and C10 (C13, C12, C11, and C10 correspond to CN13 of Figure 1 respectively). /CP13, CN12/CP12, CN11/CP11, CN10/CP10), where the capacitance value unit in Table 2 is C0:

In this embodiment, since the redundant capacitor is 297*C0, the bit capacitance of the capacitor value less than 297*C0 may not need to be split into multiple sub-capacitors, but if the splitting does not affect the continuous approximation temporary storage The operation of analog digital converter 100. For example, the capacitance of the bit capacitor C10 in Table 2 is 256*C0. Therefore, the bit capacitor C10 does not need to be split into two sub-capacitors C10, 0 and C10, 1.

In addition, in an embodiment, the capacitance values of all the sub-capacitors constituting the one-element capacitor should be the same as possible. In a preferred case, the capacitance values of all the sub-capacitors constituting the one-element capacitor are completely the same. For example, the bit capacitors C11 and C10 in Table 2.

It should be noted that the capacitance values in Tables 1 and 2 above are design values, which is the ideal value for the designer to design the continuous approximation of the temporary analog digital converter 100. However, due to the values in Tables 1 and 2 The capacitance value deviates from the originally designed capacitance value due to process error, ambient temperature variation, etc., so the processing circuit 150 needs to calibrate these bit capacitances to obtain the actual capacitance value. In the following description, the weight value Wi is the ratio of the bit capacitance Ci to the lowest bit capacitance C0 (the meaning of the weight value Wi is also equal to the value of each bit capacitance in the above Table 1), that is, Wi=Ci/C0. And W _ij is the ratio of the sub-capacitance C _i,j to the lowest bit capacitance C0, that is, W _i,j =C _i,j /C0, and the processing circuit 150 mainly calculates each bit capacitance Ci. Actual weight value.

Please refer to FIG. 2 and FIG. 3, which is a schematic diagram of background calibration of the primary capacitor by the continuous approximation temporary analog digital converter 100. FIG. 2 depicts the sampling phase, and FIG. 3 depicts Maintain the signal phase. Please refer to FIG. 2 first. In the sampling phase shown in FIG. 2, the switch CKS is turned on, and the first input signal Vip and the second input signal Vin are respectively sampled to the endpoints V _CMP and V _CMN of the figure. Assume that the secondary capacitors CP _{13, 2} and CN ₁₃ , 2 are currently calibrated, and when the pseudo-random sequence K = 1, the endpoints of the secondary capacitors CP _{13, 2} and CN ₁₃ , 2 to be calibrated are respectively connected to the The second reference voltage Vrefn and the first reference voltage Vrefp; on the other hand, when the pseudo-random sequence K=(-1), the end points of the secondary capacitors CP _{13, 2} and CN ₁₃ , 2 to be calibrated are respectively connected to the A reference voltage Vrefp and a second reference voltage Vrefn. All other sub-capacitors and bit capacitors that do not participate in this calibration at this time will be connected to the common-mode voltage V _CM .

Then, after the sampling phase ends, the hold signal phase shown in FIG. 3 is entered, and in the hold signal phase, the switch CKS is disabled, and the secondary capacitors CP ₁₃ , 2 to be calibrated and the end points of CN ₁₃ , 2 It will be connected to the common mode voltage V _CM , so that the dithering signal (K*W _{13, 2} ) will be superimposed on the input signal. After that, the input signal plus the jitter signal is continuously approximated by the temporary analog digital converter 100, and the quantized digital code is multiplied by the pseudo-random sequence K, and then accumulated and averaged to obtain the W. The value of _13,2 .

The following details how to obtain the weight value W _{13,2 of} the secondary capacitor C _13,2 : assume that the input signal is VIN, where VIN = Vip - Vin, and assume that the output of the temporary analog digital converter 100 is continuously approached at this time. The digit code is DIN, then VIN=DIN+Q _N , where Q _N is the quantization error; since the input signal will superimpose the jitter signal, the input signal plus the jitter signal is recorded as VIN+(K*W _13,2 ), The value of the pseudo-random sequence K is 1 or (-1), and at this time, the digital code outputted by the successive approximation analog digital converter 100 is Dout, then VIN+(K*W _13,2 )=Dout+ QN; multiply the above Dout by K and accumulate the average: As long as the pseudo-random sequence K is sufficiently long, the above "e" value will approach 0, so that W _13,2 can be obtained.

Based on the same calculation method, the successive approximation temporary analog-to-digital converter 100 can perform similar operations on other sub-capacitors C _13,0 , C _13,1 , . . . , respectively, to obtain corresponding weight values. In the subsequent operation of the continuous approximation analog digital converter 100, the disassembled capacitors are used as a whole, that is, all the sub-capacitors C _i,j are treated as one bit capacitors. Ci to use, for example, times the capacitance _{C 13,0, C 13,1, C 13,2} , C 13,3, C 13,4 will be as a whole bit capacitor C13 to operate. As for the switching direction of the subsequent bit capacitance, the conventional continuous approximation temporary analog digital converter is determined according to the output of the comparator 130 to achieve negative feedback convergence, which should be understood by those having ordinary knowledge in the field. Continuous approximation of the associated operation of the temporary analog digital converter in this respect, so the details will not be described here.

In addition, in the present embodiment, during the continuous approximation of the operation of the temporary analog digital converter 100, all of the secondary capacitors are continuously calibrated to update their weight values at any time, and are then generated by the processing circuit 150. Digital output Dout. However, in another embodiment of the present invention, all of the sub-capacitors can be calibrated only for a period of time during which the successive approximation of the temporary analog-to-digital converter 100 begins to operate, and the calibration can be stopped after the weight value of the sub-capacitor is stabilized. Operation, these Changes in design are all within the scope of the invention.

In addition, the digital output Dout generated by the processing circuit 150 can be calculated by the following formula (but the invention is not limited thereto): Where b _i is the code of the i-th output of the comparator, P is the number of bit capacitances in the first bit capacitor array 110 (P is 14 in the embodiment of Fig. 1), Q _N is quantization error.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a continuous approximation temporary analog digital converter 400 according to another embodiment of the present invention. As shown in FIG. 4 , the continuous approximation analog digital converter 400 includes a first bit capacitor array 410 , a second bit capacitor array 420 , a comparator 430 , a multiplier 440 , and a processing circuit 450 . And two unit capacitors CP00 and CN00, wherein the first bit capacitor array 410 includes a plurality of bit capacitors CP0~CP13, and each of the bit capacitors CP0~CP13 can be selectively connected to a first by a switch An input voltage Vip, a first reference voltage Vrefp, a second reference voltage Vrefn, and a common mode voltage V _CM , and in this embodiment, the bit capacitances CP12~CP13 are split into multiple sub-capacitors (as shown in FIG. 4 The bit capacitor CP13 shown is split into a plurality of sub-capacitors CP _13,0 , CP _13,1 , CP _13,2 , CP _13,3 ), and each sub-capacitor can be independently selected by a switch Connected to the first input voltage Vip, the first reference voltage Vrefp, the second reference voltage Vrefn and the common mode voltage V _CM ; the second bit capacitor array 420 includes a plurality of bit capacitors CN0~CN13, each bit capacitor CN0~CN13 can be selectively connected to a second input voltage Vin by a switch Reference voltages Vrefp, Vrefn second reference voltage and the common-mode voltage V _CM, and in this embodiment, the bit line capacitance CN12 ~ CN13 split into a plurality of sub-capacitors (as shown in Figure 4. The bit split capacitor CN13 It is a plurality of secondary capacitors CN _13,0 , CN _13,1 , CN _13,2 , CN _13,3 ), and each secondary capacitor can be independently connected to the second input voltage Vin by a switch The first reference voltage Vrefp, the second reference voltage Vrefn, and the common mode voltage V _CM . In addition, the switching of all the switches shown in FIG. 4 is controlled by a plurality of control signals Vc generated by the processing circuit 450.

In this embodiment, the continuous approximation temporary analog digital converter 400 is a 12-bit continuous approximation temporary analog digital converter, that is, the continuous approximation temporary analog digital converter 400 receives the first input signal. The Vip and the second input signal Vin generate a 12-bit digital output Dout. In addition, although the first bit capacitor array 410 and the second bit capacitor array 420 shown in FIG. 4 each include 14 bit capacitors, the first bit capacitor array 410 and the second bit capacitor are designed. The number of bit capacitors in array 420 can also be 12 or 13, etc., and these design variations are all within the scope of the present invention.

In the present embodiment, it is assumed that the continuous approximation temporary analog digital converter 400 is an N-bit continuous approximation temporary analog digital converter (N is 12 in the embodiment of FIG. 4), and the first bit capacitor array 410 The number of bit capacitances in the second bit capacitor array 420 is P (P is 14 in the embodiment of FIG. 4), where P needs to be greater than (N-1), and each bit capacitance is labeled C0, C1. C2, ..., C(P-1), where C0 is the lowest bit capacitance, and the capacitance values of all other bit capacitances (C1~C(P-1)) are integer multiples of C0. In addition, in this embodiment, part of the high-order capacitor is split into a plurality of secondary capacitors, for example, the bit capacitor Ci is split into M secondary capacitors, that is, . In addition, in the preferred embodiment of the present embodiment, the following three conditions must be met in the design of the capacitor: (1) , that is, the capacitance value of any bit capacitor is not greater than the sum of the capacitance values of all lower bit capacitors; (2) , that is, the sum of the capacitance values of the bit capacitors is not less than 2 ^(N-1) times the capacitance value of the lowest bit capacitor; (3) That is, the capacitance value of each sub-capacitor is less than a redundant capacitor, wherein the redundant capacitor is defined as the sum of the capacitance value of the unit capacitor and the bit capacitor and the capacitance value of the lowest bit capacitor 2 ^(N-1) The difference of the double, that is, the redundant capacitance is defined as . In the above symbols, C0 represents the lowest bit capacitance, and Ci represents the capacitance value of the first bit capacitor array 110 or the second bit capacitor array 120 where the capacitance value is the i-th highest bit capacitance.

Referring to the above three conditions, the capacitance values of the bit capacitors in the first bit capacitor array 410 and the second bit capacitor array 420 of the embodiment shown in FIG. 4 can be designed as shown in Table 3 below. The unit of the medium capacitance value is C0:

In Table 3, the redundant capacitor is Therefore, the secondary capacitance after the splitting is only required to be less than 273*C0. The following Table 4 is a split example of C13 and C12 (C13 and C12 correspond to CN13/CP13 and CN12/CP12 of Figure 4, respectively). The unit of capacitance value in Table 4 is C0:

In this embodiment, since the redundant capacitor is 273*C0, the bit capacitance of the capacitance value less than 273*C0 may not need to be split into multiple sub-capacitors, but if it is split, it does not affect the connection. The operation of the temporary analog digital converter 400 is continued.

In addition, in an embodiment, the capacitance values of all the sub-capacitors constituting the one-element capacitor should be the same as possible. In a preferred case, the capacitance values of all the sub-capacitors constituting the one-element capacitor are completely the same. For example, the bit capacitors C13 and C12 in Table 4.

It should be noted that the capacitance values in Tables 3 and 4 above are design values, which is the ideal value for the designer to design a continuous approximation of the temporary analog analog converter 400. However, due to the values in Tables 3 and 4 The capacitance value deviates from the originally designed capacitance value due to process error, ambient temperature variation, etc., so the processing circuit 450 will need to calibrate these bit capacitances to obtain the actual capacitance value. In the following description, the weight value Wi is the ratio of the bit capacitance Ci to the lowest bit capacitance C0 (the meaning of the weight value Wi is also equal to the value of each bit capacitance in the above Table 1), that is, Wi=Ci/C0. And W _i,j is the ratio of the secondary capacitance Ci,j to the lowest bit capacitance C0, that is, W _i,j =C _i,j /C0, and the processing circuit 450 mainly calculates each bit capacitance Ci The actual weight value.

Please refer to FIG. 5 and FIG. 6 , which are schematic diagrams of the background calibration of the primary capacitor by the continuous approximation temporary analog-to-digital converter 400. FIG. 5 depicts the sampling phase, and FIG. 6 depicts Maintain the signal phase. Please refer to Figure 5 first. In the sampling phase shown in Figure 5, the switch CKS is turned on, and the common mode voltage V _CM is sampled onto the V _CMP and V _CMN of the figure. Assume that the secondary capacitors CP _{13, 2} and CN ₁₃ , 2 are currently calibrated, and when the pseudo-random sequence K = 1, the endpoints of the secondary capacitors CP _{13, 2} and CN ₁₃ , 2 to be calibrated are respectively connected to the The second reference voltage Vrefn is coupled to the first reference voltage Vrefp, and the endpoints of all other bit capacitors in the first bit capacitor array 410 are connected to the first input signal Vip, and all bits in the second bit capacitor array 420 The end point of the metacapacitor is connected to the second input signal Vin; on the other hand, when the pseudo random sequence K=(-1), the end points of the sub-capacitors CP13, 2 and CN ₁₃ , 2 to be calibrated are respectively Connected to the first reference voltage Vrefp and the second reference voltage Vrefn, and the endpoints of all other bit capacitors in the first bit capacitor array 410 are connected to the first input signal Vip, and the second bit capacitor array 420 The endpoints of all other bit capacitors are connected to the second input signal Vin.

Then, after the end of the sampling phase, the hold signal phase shown in FIG. 6 is entered, and in the hold signal phase, the switch CKS is disabled, and the secondary capacitors CP ₁₃ , 2 to be calibrated and the end points of CN ₁₃ , 2 The endpoints of all other bit capacitors/ _{subcapacitors} are reverted to the common mode voltage V _CM , so that the dithering signal (K*W _{13, 2} ) is superimposed on the input signal. Then, the input signal plus the jitter signal is continuously approximated by the temporary analog digital converter 400, and the quantized digital code is multiplied by the pseudo-random sequence K, and then accumulated and averaged to obtain the W. The value of _13,2 .

The following details how to obtain the weight value W _{13,2 of} the secondary capacitor C _13,2 : assume that the input signal is VIN, where VIN = Vip - Vin, and assume that the output of the temporary analog digital converter 100 is continuously approached at this time. The digit code is DIN, then VIN=DIN+Q _N , where Q _N is the quantization error; since the input signal will superimpose the jitter signal, the input signal plus the jitter signal is recorded as VIN+(K*W _13,2 ), The value of the pseudo-random sequence K is 1 or (-1), and at this time, the digital code outputted by the successive approximation analog digital converter 100 is Dout, then VIN+(K*W _13,2 )=Dout+ Q _N ; multiply the above Dout by K and accumulate the average: As long as the pseudo-random sequence K is sufficiently long, the above "e" value will approach 0, so that W _13,2 can be obtained.

Based on the same calculation method, the continuous approximation temporary analog-to-digital converter 400 can perform similar operations on other sub-capacitors C _13,0 , C _13,1 , . . . , respectively, to obtain corresponding weight values. Subsequent to the continuous approximation of the temporary analog digital converter 400, the removed capacitors are used as a whole, that is, all secondary capacitors C _i,j are treated as one bit capacitors. Ci is used, for example, sub-capacitors C _13,0 , C _13,1 , C _13,2 , C _13,3 are operated as bit capacitor C13 as a whole. As for the switching direction of the subsequent bit capacitance, the conventional continuous approximation temporary analog digital converter is determined according to the output of the comparator 440 to achieve negative feedback convergence, which should be understood by those having ordinary knowledge in the field. Continuous approximation of the associated operation of the temporary analog digital converter in this respect, so the details will not be described here.

Moreover, in the present embodiment, during the continuous approximation of the operation of the temporary analog digital converter 400, all of the secondary capacitances are continuously calibrated to update their weight values at any time and for subsequent processing circuits 450 to generate Digital output Dout. However, in another embodiment of the present invention, all of the sub-capacitors can be calibrated only for a period of time during which the continuous approximation of the temporary analog-to-digital converter 400 begins to operate, and the calibration can be stopped after the weight value of the sub-capacitor is stabilized. Operation, these design changes are subject to the scope of the present invention.

In addition, the digital output Dout generated by the processing circuit 450 can be calculated by the following formula (but the invention is not limited thereto): , b _i (b1 to bp+1) is the code of the output of the comparator i times, and P is the number of bit capacitances in the first bit capacitor array 410 (in the embodiment of Fig. 4, P is 14), Q _N is the quantization error.

Please refer to FIG. 7. FIG. 7 is a flowchart of a method for controlling a continuous approximation temporary analog digital converter according to an embodiment of the present invention. Referring to the above descriptions of FIGS. 1 and 4, FIG. The flow of the process is as follows: Step 700: Providing a continuous approximation temporary analog analog-to-digital converter, comprising: a first bit capacitor array for receiving a first input signal, wherein the first bit capacitor array Included in the plurality of first bit capacitors, the at least one high bit capacitance in the first bit capacitor array is formed by a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first by a corresponding switch a reference voltage, a second reference voltage or a common mode voltage; and a second bit capacitor array for receiving a second input signal, wherein the second bit capacitor array comprises a plurality of second bit cells The at least one high-order capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage and the second reference by a corresponding switch. a voltage or the common mode voltage; step 702: comparing the output of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; step 704: determining each first bit according to the comparison signal a meta-capacitor or a weight value corresponding to each of the second bit capacitors; step 706: generating a digital output of the continuous approximation temporary analog-to-digital converter according to the comparison signal and the determined plurality of weight values .

In summary, the continuous approximation temporary analog digital converter of the present invention has the following advantages: (1) The bit capacitance of the present invention is a true background calibration, and does not affect the continuous approximation of the temporary analog digital conversion. The working speed of the device; (2) the capacitor participating in the calibration can continue to participate in the subsequent continuous approximation of the temporary analog digital converter, and the continuous approximation of the temporary analog digital converter works the same as the conventional one, so there is no extra Adding too much complexity; (3) In the continuous approximation temporary analog digital converter of the present invention, as long as the bit capacitance of the capacitance value larger than the redundant capacitance is split into multiple sub-capacitors, due to these sub-capacitors In the continuous redundancy approximation of the coded redundancy range of the temporary analog digital converter, the input signal can be used without the need to limit the swing, that is, the full swing input, and the jitter signal superimposed on the input signal can be completely solved by redundancy. (4) Calibration of all secondary capacitors can be performed separately by sequential switching, so the calibration circuits in the processing circuit can be shared, so the relevant circuit area in the wafer can be large Decreases.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Continuous approaching temporary analog analog converter

110‧‧‧First bit capacitor array

120‧‧‧Secondary Capacitor Array

130‧‧‧ comparator

140‧‧‧Multiplier

150‧‧‧Processing circuit

CP00, CN00‧‧‧ unit capacitor

CP0~CP13, CN0~CN13‧‧‧ bit capacitance

_{CP 13,0 ~ CP 13,4, CN 13,0} ~ CN 13,4 ‧‧‧ capacitor Ci

CKS‧‧ switch

Dout‧‧‧ digital output

K‧‧‧ pseudo-random sequence

Vc‧‧‧ control signal

Vip‧‧‧first input signal

Vin‧‧‧second input signal

Vrefp‧‧‧ first reference voltage

Vrefn‧‧‧second reference voltage

V _CM ‧‧‧ Common mode voltage

V _CMP , V _CMN ‧‧‧ endpoint

Claims (15)

A successive approximation register analog-to-digital converter (SAR ADC) includes: a first bit capacitor array for receiving a first input signal, wherein the first bit The metacapacitor array includes a plurality of first bit capacitors, and at least one high bit capacitor in the first bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected by a corresponding switch a first reference voltage, a second reference voltage or a common mode voltage; a second bit capacitor array for receiving a second input signal, wherein the second bit capacitor array comprises a plurality of second bit capacitors At least one high-order capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage and the second reference voltage by a corresponding switch Or the common mode voltage; a comparator coupled to the first bit capacitor array and the second bit capacitor array for comparing the first bit capacitor array and the second bit The output of the array is configured to generate a comparison signal; and a processing circuit coupled to the comparator for controlling capacitance switching between the first bit capacitor array and the second bit capacitor array, and generating the continuous approximation a digital output of the analog analog converter; wherein the processing circuit is in the process of receiving the first input signal and the second input signal to generate the digital output by the continuous approximation temporary analog digital converter The plurality of sub-capacitors of the at least one high-order capacitor in the one-element capacitor array are respectively calibrated to generate a weight value corresponding to the plurality of sub-capacitors, and then determined according to the weight values of the plurality of sub-capacitors a weight value of the at least one high-order capacitor in the first bit capacitor array; and the processing circuit separately calibrates the plurality of sub-capacitors of the at least one high-bit capacitor in the second bit capacitor array to generate Corresponding to the weight value of the plurality of secondary capacitors, and further determining the second bit capacitor array according to the weight value of the plurality of secondary capacitors The weight value of at least one high-order capacitor. The continuous approximation temporary analog digital converter according to claim 1, wherein the capacitance values of the plurality of sub-capacitors in the at least one high-order capacitor in the first bit capacitor array are the same. The continuous approximation temporary analog analog-to-digital converter according to claim 1, wherein the continuous approximation temporary analog digital converter is an N-bit continuous approximation temporary analog analog digital converter, the plurality of The arrangement of the one-element capacitor is non-binary, and the capacitance value of any one of the plurality of first-bit capacitors is not greater than the sum of the capacitance values of all the lower-bit capacitors, and the first-bit capacitor array is The sum of the capacitance values of the plurality of first bit capacitors is not less than 2 ^(N-1) times the capacitance value of the lowest bit capacitance. The continuous approximation analog analog-to-digital converter according to claim 3, wherein in the first bit capacitor array, the first bit capacitance of the capacitance value greater than a redundant capacitor is composed of multiple sub-capacitors The capacitance value of each sub-capacitor is smaller than the redundant capacitor, wherein the redundant capacitor is defined as a unit capacitance and a sum of capacitance values of the plurality of first bit capacitors in the first bit capacitor array The difference from the 2 ^(N-1) times the capacitance of the lowest bit capacitor. The continuous approximation temporary analog analog-to-digital converter according to claim 4, wherein the continuous approximation temporary analog digital converter receives the first input signal and the second input signal to generate the digital output. In the process, for each first bit capacitor composed of a plurality of sub-capacitors, the processing circuit separately calibrates the sub-capacitors to generate weight values corresponding to the sub-capacitors, and then according to the times The weight value of the capacitor determines a weight value of the first bit capacitor; and for each second bit capacitor formed by the plurality of sub-capacitors, the processing circuit separately calibrates the capacitors to generate a corresponding The weight value of the capacitors, and then The weight values of the capacitors are used to determine the weight value of the second bit capacitor. The continuous approximation temporary analog digital converter according to claim 1, wherein the continuous approximation temporary analog digital converter allows the first input signal and the second input signal to be input at a rail-to-rail. A method for controlling a continuous approximation of a temporary analog analog-to-digital converter, wherein the continuous approximation temporary analog digital converter comprises: a first bit capacitor array for receiving a first input signal, wherein the first The bit capacitor array includes a plurality of first bit capacitors, and at least one high bit capacitor in the first bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected by a corresponding switch a first reference voltage, a second reference voltage, or a common mode voltage; and a second bit capacitor array for receiving a second input signal, wherein the second bit capacitor array includes a plurality of second bits a metacapacitor, the at least one high bit capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage by the corresponding switch, the second a reference voltage or the common mode voltage; the method includes: comparing an output of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; according to the comparison signal Determining a weight value corresponding to each of the first bit capacitors or each of the second bit capacitors; generating the continuous approximation temporary analog digital converter according to the comparison signal and the determined plurality of weight values a digital output; wherein the continuous approximation temporary analog digital converter receives the first input signal and the second input signal to generate the digital output, the at least one of the first bit capacitor array The plurality of sub-capacitors of the high-order capacitor are respectively calibrated to generate corresponding a weight value of the plurality of secondary capacitors, and further determining, according to a weight value of the plurality of secondary capacitors, a weight value of the at least one high-order capacitor in the first bit capacitor array; and the second bit capacitor array The plurality of sub-capacitors of the at least one high-order capacitor are respectively calibrated to generate a weight value corresponding to the plurality of sub-capacitors, and then determining the second bit according to the weight value of the plurality of sub-capacitors A weight value of the at least one high bit capacitor in the capacitor array. The method of claim 7, wherein the capacitance values of the plurality of sub-capacitors in the first bit capacitor array that constitute the at least one high-order capacitor are the same. The method of claim 7, wherein the continuous approximation temporary analog digital converter is an N-bit continuous approximation temporary analog digital converter, and the arrangement of the plurality of first bit capacitances is non- Binary, the capacitance value of any one of the plurality of first bit capacitors is not greater than the sum of the capacitance values of all the lower bit capacitors, and the plurality of first bit capacitors in the first bit capacitor array The sum of the capacitance values is not less than 2 ^(N-1) times the capacitance of the lowest bit capacitance. The method of claim 9, wherein in the first bit capacitor array, a first bit capacitor having a capacitance greater than a redundant capacitor is composed of a plurality of sub-capacitors, and each sub-capacitor The capacitance value is smaller than the redundant capacitance, wherein the redundant capacitance is defined as a unit capacitance and a capacitance value of the plurality of first bit capacitances and a capacitance value of the lowest bit capacitance in the first bit capacitance array. The difference of 2 ^(N-1) times. The method of claim 7, wherein the first input signal and the second input signal are allowed to be input at a rail-to-rail. A successive approximation register analog-to-digital converter (SAR ADC) includes: a first bit capacitor array for receiving a first input signal, which includes a plurality of a one-element capacitor, wherein at least one high-order capacitor in the first-bit capacitor array is composed of a plurality of sub-capacitors; and a second-bit capacitor array is configured to receive a second input signal, which includes a plurality of a two-bit capacitor, wherein at least one high-order capacitor in the second-bit capacitor array is composed of a plurality of sub-capacitors; a comparator for comparing the first bit capacitor array and the second bit capacitor array The output is coupled to generate a comparison signal; and a processing circuit coupled to the comparator for controlling capacitance switching of the first bit capacitor array and the second bit capacitor array, and generating a N according to the comparison signal Bit digital output; wherein, in the first bit capacitor array, the first bit capacitance of the capacitance value greater than a redundant capacitance is composed of a plurality of sub-capacitors, and the electric power of each sub-capacitor The capacitance value is less than redundancy, wherein the capacitance of the redundancy bit line is defined as a first sum of the capacitance of the capacitor and the capacitance value of a unit capacitor and capacitor array of the first bit of the plurality of capacitors lowest bits of 2 ^{( N-1)} difference. The continuous approximation temporary analog digital converter according to claim 12, wherein the arrangement of the plurality of first bit capacitors is non-binary, and any one of the plurality of first bit capacitors The capacitance value is not greater than the sum of the capacitance values of all the lower bit capacitances, and the sum of the capacitance values of the plurality of first bit capacitances in the first bit capacitance array is not less than the capacitance value of the lowest bit capacitance 2 ^{(N- 1)} times. A continuous approximation temporary analog analog-to-digital converter includes: a first bit capacitor array for receiving a first input signal, wherein the first bit capacitor array The column includes a plurality of first bit capacitors, and at least one high bit capacitor in the first bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first by a corresponding switch a reference voltage, a second reference voltage or a common mode voltage; a second bit capacitor array for receiving a second input signal, wherein the second bit capacitor array comprises a plurality of second bit capacitors, At least one high-order capacitor in the second bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage, the second reference voltage, or the corresponding switch The common mode voltage is coupled to the first bit capacitor array and the second bit capacitor array for comparing the output of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; and a processing circuit coupled to the comparator for controlling capacitance switching between the first bit capacitor array and the second bit capacitor array, and generating the continuous approximation temporary analog digital conversion A digital output; wherein the first capacitor array of bits constituting the at least one high-capacitance element in the capacitance value of the plurality of capacitors are the same views. A method for controlling a continuous approximation of a temporary analog analog-to-digital converter, wherein the continuous approximation temporary analog digital converter comprises: a first bit capacitor array for receiving a first input signal, wherein the first The bit capacitor array includes a plurality of first bit capacitors, and at least one high bit capacitor in the first bit capacitor array is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected by a corresponding switch And a capacitance value of the first reference voltage, a second reference voltage, or a common mode voltage, and the plurality of sub-capacitors in the at least one high-order capacitor in the first bit capacitor array are the same; a two-element capacitor array for receiving a second input signal, wherein the second bit capacitor array comprises a plurality of second bit capacitors, at least one high bit in the second bit capacitor array The capacitor is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage, the second reference voltage or the common mode voltage by a corresponding switch; the method includes: comparing the And outputting the first bit capacitor array and the second bit capacitor array to generate a comparison signal; determining the weight corresponding to each of the first bit capacitors or each of the second bit capacitors according to the comparison signal And a digital output based on the comparison signal and the determined plurality of weight values to generate a digital output of the continuous approximation temporary analog digital converter.