CN115967403A - Successive approximation register type analog-digital conversion device and signal conversion method - Google Patents
Successive approximation register type analog-digital conversion device and signal conversion method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The application relates to a successive approximation register type analog-digital conversion device and a signal conversion method. The successive approximation register analog-to-digital conversion device includes first and second digital-to-analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching circuit. The first and second DAC circuits sample an input signal. The comparator circuit and the controller circuit generate a plurality of first and second bits based on outputs of the first and second DAC circuits. The dynamic element matching circuit encodes the first bit to generate a third bit to refresh the first DAC circuit. The controller circuit also resets a portion of the second bits after the first DAC circuit is refreshed. The comparator circuit generates a plurality of comparison results based on the outputs of the first and second DAC circuits after the partial bit is reset. The controller circuit generates a plurality of fourth bits according to the comparison result and generates a digital output according to the first, second and fourth bits.
Description
Technical Field
The present invention relates to analog-to-digital converters, and more particularly, to a successive approximation register analog-to-digital conversion apparatus and a signal conversion method using dynamic element matching and statistical operations.
Background
In the successive approximation register adc, since the capacitance of each capacitor in the capacitor array may be mismatched due to process error, environmental temperature variation, etc., the digital output will have error, and the linearity of the successive approximation register adc is affected. In conventional designs, to solve this problem, it is often necessary to use a larger capacitor to reduce the mismatch. However, the use of a larger capacitor results in a significant increase in the overall area of the circuit. On the other hand, if the circuit technique of over sampling (over sampling) is used in the successive approximation register adc to reduce the error, the available frequency of the input signal is reduced.
Disclosure of Invention
In some embodiments, the successive approximation register analog-to-digital conversion device includes a first digital-to-analog converter circuit, a second digital-to-analog converter circuit, a comparator circuit, a controller circuit, and a dynamic element matching circuit. The second digital-to-analog converter circuit is used for cooperating with the first digital-to-analog converter circuit to sample an input signal. The comparator circuit is used for generating a plurality of first comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit. The controller circuit is used for generating a plurality of first bits and a plurality of second bits according to the first comparison results and storing the first bits and the second bits, wherein the second bits are used for switching the second digital-to-analog converter circuit. The dynamic element matching circuit is used for encoding the first bits to generate a plurality of third bits so as to refresh the first digital-to-analog converter circuit. The controller circuit is further configured to reset a portion of the second bits after the first DAC circuit is refreshed. The comparator circuit is further configured to generate a plurality of second comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit after the partial bits are reset, and the controller circuit is further configured to generate a plurality of fourth bits according to the second comparison results and generate a digital output according to the first bits, the second bits and the fourth bits.
In some embodiments, the signal conversion method comprises the following operations: sampling an input signal by a first digital-to-analog converter circuit and a second digital-to-analog converter circuit in cooperation to generate a plurality of first comparison results according to an output of the first digital-to-analog converter circuit and an output of the second digital-to-analog converter circuit; generating a plurality of first bits and a plurality of second bits according to the first comparison results, and storing the first bits and the second bits, wherein the second bits are used for switching the second digital-to-analog converter circuit; encoding the first bits to generate a plurality of third bits to refresh the first digital-to-analog converter circuit; resetting a portion of the second bits after the first DAC circuit is refreshed; after the partial bit is reset, generating a plurality of second comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit; generating a plurality of fourth bits according to the second comparison results; and generating a digital output according to the first bits, the second bits and the fourth bits.
The features, implementations and functions of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 illustrates a successive approximation register analog-to-digital converter device according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of a plurality of DAC circuits of FIG. 1 according to some embodiments of the present disclosure; and
FIG. 3 is a flow chart of a signal conversion method according to some embodiments of the present disclosure.
Detailed Description
All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries are provided, and any use examples of the words discussed herein in this disclosure are merely examples, and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the disclosure is not limited to the various embodiments shown in this specification.
As used herein, the terms "coupled" or "connected," may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements are in operation or act with each other. As used herein, the term "circuitry" may be a single system formed from at least one circuit, and the term "circuit" may be a device connected in some manner by at least one transistor and/or at least one active or passive component to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like may be used herein to describe and distinguish various elements. Thus, a first element could be termed a second element herein without departing from the spirit of the present disclosure. For ease of understanding, like elements in the various drawings will be designated with the same reference numerals.
Fig. 1 is a schematic diagram of a Successive Approximation Register (SAR) adc device 100 (hereinafter referred to as SAR adc device 100) according to some embodiments of the disclosure. The SAR adc device 100 may generate a digital output DOUT according to the input signal VIP and the input signal VIN.
The SAR adc device 100 includes a switch SW1, a switch SW2, a digital-to-analog converter circuit 110, a digital-to-analog converter circuit 115, a digital-to-analog converter circuit 120, a digital-to-analog converter circuit 125, a comparator circuit 130, a controller circuit 140, and a dynamic element matching circuit 150.
The switches SW1 and SW2 are turned on during the sampling period. Thus, the input signal VIP and the input signal VIN can be transmitted to the node N1 and the node N2, respectively. Under this condition, the digital-to-analog converter circuit 110 may cooperate with the digital-to-analog converter circuit 115 to sample the input signal VIP, and the digital-to-analog converter circuit 120 may cooperate with the digital-to-analog converter circuit 125 to sample the input signal VIN.
The digital-to-analog converter circuit 110 and the digital-to-analog converter circuit 120 correspond to high-weight bits (e.g., most significant bits) in the digital output DOUT, and the digital-to-analog converter circuit 115 and the digital-to-analog converter circuit 125 correspond to low-weight bits (e.g., least significant bits) in the digital output DOUT. In other words, the weight corresponding to the digital-to-analog converter circuit 110 is higher than the weight corresponding to the digital-to-analog converter circuit 115, and the weight corresponding to the digital-to-analog converter circuit 120 is higher than the weight corresponding to the digital-to-analog converter circuit 125. The arrangement of the digital-to-analog converter circuits 110,115,120 and 125 will be described later with reference to fig. 2.
During the analog-to-digital conversion stage, the switches SW1 and SW2 are not conductive. At this stage, the DAC circuit 110 generates the corresponding output at the node N1 according to the high-weight bits, and the DAC circuit 115 generates the corresponding output at the node N1 according to the low-weight bits. In other words, the outputs of the digital-to- analog converter circuits 110 and 115 can be used to adjust the level of the node N1. Similarly, the digital-to-analog converter circuit 120 may generate a corresponding output at the node N2, and the digital-to-analog converter circuit 125 may generate a corresponding output at the node N2. In other words, the outputs of the digital-to- analog converter circuits 120 and 125 can be used to adjust the level of the node N2.
The comparator circuit 130 is used for generating a decision signal VOP and a decision signal VON according to an output of each of the plurality of digital-to-analog converter circuits 110,115,120 and 125. For example, if the level of the node N1 is higher than the level of the node N2, the decision signal VOP has a logic value 1, and the decision signal VON has a logic value 0, but not limited thereto. Alternatively, if the level of the node N1 is lower than the level of the node N2, the decision signal VOP has a logic value 0, and the decision signal VON has a logic value 1, but not limited thereto. In the adc stage, the comparator circuit 130 sequentially generates a plurality of comparison results (i.e., a plurality of sets of decision signals VOP and VON). The controller circuit 140 may sequentially generate a plurality of bits D1 to D14 according to the comparison results, and store the plurality of bits D1 to D14. In this example, the plurality of bits D1D 3 are the most significant bits, and the plurality of bits D4D 14 are the least significant bits, which can be used to switch the DAC circuit 115. In some embodiments, the controller circuit 140 further outputs a plurality of bits Db4 Db14 to switch the DAC circuit 125, wherein a corresponding one of the plurality of bits D4D 14 and a corresponding one of the plurality of bits Db4 Db14 have opposite logic values. For example, when the bit D4 has a logic value of 1, the bit Db4 has a logic value of 0. And so on, when bit D14 has a logic value of 0, bit Db14 has a logic value of 1.
In some embodiments, the controller circuit 140 may perform a successive approximation algorithm with redundancy (redundancy) operation to generate the plurality of bits D1D 14, but the disclosure is not limited thereto. In some embodiments, the successive approximation algorithm may be a binary search algorithm or a non-binary search algorithm depending on the configuration of the plurality of digital-to-analog converters 110,115,120, and 125.
The dynamic device matching circuit 150 is used for encoding a plurality of bits D1-D3 to generate a plurality of bits EB to refresh the DAC circuit 110. In some embodiments, the dynamic device matching circuit 150 is further configured to encode the plurality of bits D1D 3 to generate a plurality of bits EB' to refresh the DAC circuit 120. In some embodiments, each of the controller circuit 140 and the dynamic element matching circuit 150 may be implemented by a digital signal processing circuit. In some embodiments, the controller circuit 140 and the dynamic element matching circuit 150 may be integrated into a digital control logic circuit system.
After the digital-to- analog converter circuits 110 and 120 are refreshed, the controller circuit 140 resets a part of the bits D4 to D14 and a part of the bits D4b to D14b, the comparator circuit 130 generates comparison results according to the outputs of the digital-to-analog converter circuits 110,115,120 and 125 after the part of the bits are reset, and the controller circuit 140 generates bits according to the comparison results and generates a digital output DOUT according to the bits D1 to D14 and the bits (for example, the bits D10_ F to D14_ F). The detailed description about this will be described later with reference to fig. 3.
Fig. 2 is a schematic diagram of the digital-to-analog converter circuits 110,115,120, and 125 in fig. 1 according to some embodiments of the disclosure. In this example, each of the plurality of digital-to-analog converter circuits 110,115,120, and 125 may be a capacitive digital-to-analog converter circuit.
The digital-to-analog converter circuit 110 includes a control logic circuit 211, a switching circuit 212, and a plurality of capacitors C mu1 ～C mu3 . A plurality of capacitors C mu1 ～C mu3 Is based on a thermometer code setting. For example, a capacitance C mu1 Comprising 4 unit capacitors C m (i.e., capacitance C) mu1 Corresponding weight of 4), capacitance C mu2 Comprising 2 unit capacitors C m (i.e., capacitance C) mu2 Corresponding weight of 2), capacitance C mu3 Comprising 1 unit capacitor C m (i.e., capacitance C) mu3 The corresponding weight is 1). In the digital-analog converter circuit 110, a plurality of unit capacitors C m One terminal of the unit capacitors is coupled to the node N1, and a plurality of unit capacitors C m And the other end is coupled to the switching circuit 212. The control logic circuit 211 controls the switching circuit 212 according to the plurality of bits EB. The switching circuit 212 transmits the reference voltage Vp or Vn to the corresponding unit capacitor C based on the control of the control logic circuit 211 m 。
Similarly, the digital-to-analog converter circuit 120 includes a control logic circuit 221, a switching circuit 222, and a plurality of capacitors C du1 ～C du3 . A plurality of capacitors C du1 ～C du3 Is based on a thermometer code setting. For example, a capacitance C du1 Comprising 4 unit capacitors C m (i.e., capacitance C) du1 Corresponding weight of 4), capacitance C du2 Comprising 2 unit capacitors C m (i.e., capacitance C) du2 Corresponding weight of 2), capacitance C du3 Comprising 1 unit capacitor C m (i.e., capacitance C) du3 The corresponding weight is 1). In the digital-analog converter circuit 120, a plurality of unit capacitors C m One terminal of the unit capacitors is coupled to the node N2 and a plurality of unit capacitors C m And the other end is coupled to the switching circuit 222. The control logic circuit 221 controls the switching circuit 222 according to the plurality of bits EB'. The switching circuit 222 transmits the reference voltage Vp or Vn to the corresponding unit capacitor C based on the control of the control logic circuit 221 m 。
The digital-to-analog converter circuit 115 includes a control logic circuit 213, a switching circuit 214, and a plurality of capacitors C M1 ～C MY (several are omitted in the figure). Multiple purposeA capacitor C M1 ～C MY Are different from each other to correspond to different weights. For example, in a plurality of capacitors C M1 ～C MY Middle and high capacitance C MY Corresponding to the maximum weight and having the maximum capacitance value, and a capacitor C M1 Corresponding to the smallest weight and thus having the smallest capacitance. The control logic circuit 213 controls the switching circuit 214 based on the plurality of bits D4 to D14. The switching circuit 214 transfers the reference voltage Vp or Vn to the plurality of capacitors C based on the control of the control logic circuit 213 M1 ～C MY 。
Similarly, the digital-to-analog converter circuit 125 includes a control logic circuit 223, a switching circuit 224, and a plurality of capacitors C L1 ～C LY (several are omitted from the figure). A plurality of capacitors C L1 ～C LY Are different from each other to correspond to different weights. For example, in a plurality of capacitors C L1 ～C LY Middle and high capacitance C LY Corresponding to the maximum weight and having the maximum capacitance value, and a capacitor C L1 To the smallest weight and therefore has the smallest capacitance. The control logic circuit 223 controls the switching circuit 224 based on the plurality of bits Db4 to Db14. The switching circuit 224 transmits the reference voltage Vp or Vn to the plurality of capacitors C based on the control of the control logic circuit 223 L1 ～C LY 。
In some embodiments, the SAR adc 100 of fig. 1 further comprises a capacitor C 1 And a capacitor C 2 . Capacitor C 1 The node N1 is coupled to receive a reference voltage Vn. Capacitor C 2 Coupled to the node N2 and configured to receive a reference voltage Vn. In some embodiments, the capacitor C 1 And a capacitor C 2 For attenuating the effect of the reference voltages Vp and Vn on the nodes N1 and N2 during capacitance switching, i.e. for attenuating the gain of the input signal equivalent to the comparator circuit 130, the arrangement can use higher reference voltages Vp and Vn. In some embodiments, the capacitor C 1 And a capacitor C 2 Which can be considered as the parasitic capacitance to ground of the sum of node N1 and node N2. In some embodiments, the capacitor C 1 Can be the same asCapacitor C M1 And a capacitance value of, and a capacitance C 2 Has the same capacitance value as the capacitor C L1 The capacity value of (c).
Fig. 2 is only an example of a binary digital-to-analog converter, but the present disclosure is not limited thereto. In some embodiments, the capacitors of FIG. 2 can be implemented by non-binary coding or segmented coding. In some embodiments, the control logic (e.g., the control logic 211,213,221, or 223) and the switching circuit (e.g., the switching circuit 212,214,222, or 224) may be implemented by digital circuits and/or switch circuits.
Fig. 3 is a flow chart of a signal conversion method 300 according to some embodiments of the disclosure. In some embodiments, the signal conversion method 300 may be performed by the SAR analog-to-digital conversion device 100 of fig. 1. For ease of understanding, the related operation of the SAR analog-to-digital conversion device 100 will be described below in terms of the signal conversion method 300.
In operation S310, a first SAR adc is performed to generate a plurality of first bits (e.g., a plurality of bits D1 to D3) and a plurality of second bits (e.g., a plurality of bits D4 to D14). Operation S310 includes steps S31 and S32.
In step S31, the input signal is sampled. For example, the switches SW1 and SW2 are turned on, and all the capacitors in the digital-to-analog converter circuits 110,115,120 and 125 receive the reference voltage Vp. Under this condition, the digital-to-analog converter circuit 110 may cooperate with the digital-to-analog converter circuit 115 to sample the input signal VIP, and the digital-to-analog converter circuit 120 may cooperate with the digital-to-analog converter circuit 125 to sample the input signal VIN. After the sampling is completed, the switches SW1 and SW2 are not turned on, and all the capacitors in the digital-to-analog converter circuits 110,115,120 and 125 continue to receive the reference voltage Vp. In step S32, a plurality of first comparison results (i.e., a plurality of sets of decision signals VOP and VON corresponding to the first SAR adc) are generated according to outputs of the plurality of digital-to-analog converter circuits, and a plurality of first bits (e.g., a plurality of bits D1 to D3) and a plurality of second bits (e.g., a plurality of bits D4 to D14) are generated according to the first comparison results.
In operation S320, a plurality of first bits are encoded to generate a plurality of third bits (e.g., a plurality of bits EB) to refresh the digital-to-analog converter circuit corresponding to the high-weight bits.
In some embodiments, the dynamic element matching circuit 150 may encode the bits D1-D3 into bits corresponding to the thermometer code, and perform a randomization (or pseudo-randomization) algorithm according to the bits to generate bits EB, and generate corresponding bits EB 'according to the bits EB, wherein the bits EB can be used to refresh the dac circuit 110, and the bits EB' can be used to refresh the dac circuit 120. In general, the bit EB' is defined in a manner that depends on the bit EB for controlling the capacitance C m The logic is coupled to the voltage Vn or the voltage Vp, but not limited thereto. In some embodiments, the plurality of bits EB can be, but is not limited to, logical complements of the plurality of bits EB'.
For example, if the plurality of bits D1 to D3 is 100, the digital code of the plurality of bits D1 to D3 is +1 (i.e., +4-2-1= + 1), which corresponds to one unit capacitor C m . Assuming that in the first SAR ADC, the DAC circuit 110 utilizes a capacitor C mu1 The 1 st unit capacitor C m To generate an output corresponding to the digital code. For example, the 1 st unit capacitor C m Receives the voltage Vn and the residual unit capacitor C in the DAC circuit 110 m And all unit capacitances C in the digital-to-analog converter circuit 120 m Receives the voltage Vp to generate the output corresponding to the digital code. After being processed by the dynamic element matching circuit 150, the digital-to-analog converter circuit 110 can utilize another unit capacitor C according to the bits EB m (e.g. a capacitance C) mu1 The 2 nd unit capacitor C in m ) To generate an output corresponding to the digital code. For example, the 2 nd unit capacitor C m Receiving the voltage Vn, and the remaining unit capacitor C in the DAC circuit 110 m And all unit capacitances C in the digital-to-analog converter circuit 120 m Receives the voltage Vp to generate the output corresponding to the digital code.
In other words, in the first SAR analog conversion, the digital-analog converter circuit 110 can utilize a plurality of unit capacitors C m At least one first capacitor (e.g. the 1 st unit capacitor C) m ) To produce outputs corresponding to a plurality of first comparison results. Through the dynamic element matching circuit 150, the digital-to-analog converter circuit 110 can utilize a plurality of unit capacitors C according to a plurality of bits EB m At least one second capacitor (for example, the aforementioned 2 nd unit capacitor C) m ) To generate outputs corresponding to a plurality of first comparison results, wherein at least one first capacitor is not identical to at least one second capacitor. Equivalently, the DAC circuit 110 can be refreshed in response to multiple bits EB to select different unit capacitors C m To produce the same output. Thus, the unit capacitors C can be reduced m The mismatch therebetween to improve the linearity of the digital-to-analog converter circuit 110.
In operation S330, a portion of the second bits are reset after the digital-to-analog converter circuit corresponding to the high-weight bits is refreshed. In operation S340, after the partial bit is reset, a plurality of second comparison results are generated according to the outputs of the plurality of digital-to-analog converter circuits. In operation S350, a plurality of fourth bits are generated according to the second comparison results, and a digital output is generated according to the first bits, the second bits, and the fourth bits.
For example, after the digital-to-analog converter circuit 110 is refreshed, the controller circuit 140 may reset a portion of the bits D4 to D14 and maintain the remaining bits of the bits D4 to D14 unchanged from the bits D1 to D3. In some embodiments, the remaining bits correspond to higher weights than the partial bits. For example, a part of the bits may be a plurality of bits D10 to D14 corresponding to lower weights among the plurality of bits D4 to D14, and the remaining bits may be a plurality of bits D4 to D9 corresponding to higher weights among the plurality of bits D4 to D14. It should be appreciated that since the remaining bits D4D 9 remain unchanged, the corresponding bits Db4 Db9 of the plurality of bits Db4 Db14 also remain unchanged. The plurality of digital-to-analog converter circuits 110,115,120, and 125 may be switched in response to the plurality of bits to generate corresponding outputs. Accordingly, after the bits D10-D14 (and the bits Db 10-Db 14) are reset, the comparator circuit 130 can generate a plurality of second comparison results (i.e. a plurality of sets of decision signals VOP and VON) according to the outputs of the digital-to-analog converter circuits 110,115,120 and 125. The controller circuit 140 can generate a plurality of fourth bits (e.g., a plurality of bits D10_ F-D14 _ F as described later) according to the second comparison results, and generate a digital output DOUT according to the plurality of bits D1-D3, the plurality of bits D4-D14 and the fourth bits.
In one example, the SAR adc 100 is a 12-bit SAR adc, and generates 2 redundant bits after generating a plurality of most significant bits (e.g., a plurality of bits D1-D3). As such, in the analog-to-digital conversion, the SAR analog-to-digital conversion apparatus 100 can generate 14 bits (e.g., a plurality of bits D1 to D14). Under this condition, through the aforementioned operations, the bits generated by the controller circuit 140 can be summarized as the following table:
| corresponding comparison result | Stored bits |
| First comparison result | D1、D2、D3、…、D9、D10、D11、…、D14 |
| Second comparison result | D1、D2、D3、…、D9、D10_F、D11_F、…、D14_F |
The first comparison result corresponds to the first SAR adc, and the second comparison result is generated after the digital-to-analog converter circuit 110 is reset. Through the above operations, the controller circuit 140 can obtain a plurality of sets of bits (e.g., the first set of bits D1D 14 and the second set of bits D1D 9 and D10_ F D14_ F). In this way, the controller circuit 140 can perform a statistical operation according to the groups of bits to generate the digital output DOUT.
For example, the controller circuit 140 may average a portion of the bits (e.g., the bits D10-D14) and a plurality of fourth bits (e.g., the bits D10_ F-D14 _ F) to generate a plurality of fifth bits (e.g., an average result of the bits D10-D14 and the bits D10_ F-D14 _ F), and combine the bits D1-D3, the remaining bits D4-D9, and the fifth bits into the digital output DOUT. Alternatively, the controller circuit 140 may directly average the sets of bits in the table above to generate the digital output DOUT. The dynamic element matching circuit 150 and the statistical operations described above can reduce the effect of element (e.g., capacitor) mismatch. As a result, the linearity of the SAR adc 100 can be improved without increasing the device area. In some embodiments, the statistical operation may be an averaging operation or a weighted averaging operation, but the present disclosure is not limited thereto. In addition, since the above operations do not use over sampling (oversampling), the frequency of the input signal VIN is not limited by the sampling frequency, and thus the usable frequency of the input signal VIN is not reduced.
The operations of the signal conversion method 300 are merely examples, and need not be performed in the order of the examples. The various operations of the signal conversion method 300 may be added, substituted, omitted, or performed in a different order (e.g., concurrently or with partial concurrence) as appropriate, without departing from the scope and manner of operation of the various embodiments herein.
The above description is merely exemplary, and the present disclosure is not limited thereto. For example, in other embodiments, the operations S320, S330, and S340 may be repeated multiple times to obtain more sets of bits (e.g., more sets of bits D10_ F-D14 _ F) to generate more accurate digital output DOUT. For example, after obtaining the second set of bits from the above table, the dynamic element matching circuit 150 may encode the plurality of bits D1-D3 to generate a plurality of bits EB and EB' to refresh the plurality of digital-to- analog converter circuits 110 and 120. Then, the controller circuit 140 resets the bits D10_ F-D14 _ F and Db 10-Db 14. After the bits D10-D14 (and Db 10-Db 14) are reset, the comparator circuit 130 may repeatedly compare the output of the DAC circuit 110 (and DAC circuit 115) and the output of the DAC circuit 120 (and DAC circuit 125) to generate more second comparison results. The controller circuit 140 generates a plurality of bits (e.g., the bits D10_ F1-D14 _ F1) according to the second comparison results, and stores the bits as a third set of bits (e.g., the bits D1-D9 and D10_ F1-D14 _ F1). In this way, the controller circuit 140 can generate the digital output DOUT according to the first set of bits, the second set of bits and the third set of bits. For example, the controller circuit 140 may average the plurality of sets of bits to generate the digital output DOUT. In some embodiments, the greater the number of repeated comparisons and/or the number of groups of bits, the more accurate the digital output DOUT may be.
In addition, the above embodiments are only described by way of differential type arrangement, but the present disclosure is not limited thereto. In some embodiments, the above embodiments can be implemented in a single-ended configuration. In some embodiments, in a single-ended configuration, the SAR analog conversion device 100 may operate with a portion of the plurality of digital-to-analog converter circuits 110,115,120, and 125 coupled to an input (e.g., node N1 or node N2) of the comparator circuit 130. For example, the SAR analog conversion device 100 may be a common-mode voltage (VCM-based) switching based single-ended device, which may only include the plurality of digital-to- analog converter circuits 110 and 115.
In summary, the SAR adc and the signal conversion method in some embodiments of the present disclosure may utilize dynamic element matching to refresh the dac circuits corresponding to the high-weight bits, and utilize statistical operations to generate the final digital output. Therefore, the influence of the unmatched elements in the device can be reduced, and the linearity can be improved without increasing the area of the elements. In addition, the correlation operation does not use the oversampling technique, so that the usable frequency of the input signal is not reduced.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
[ description of symbols ]
100: successive approximation register type analog-digital conversion device
110,115,120,125: digital-to-analog converter circuit
130: comparator circuit
140: controller circuit
150: dynamic element matching circuit
211,213,221,223: control logic circuit
212,214,222,224: switching circuit
300: signal conversion method
C 1 ,C 2 ,C L1 ～C LY ,C M1 ～C MY : capacitor with a capacitor element
C du1 ～C du3 ,C mu1 ～C mu3 : capacitor with a capacitor element
C m : unit capacitor
D1-D14, db 4-Db 14, EB, EB': bits
DOUT: digital output
N1, N2: node point
S310, S320, S330, S340, S350: operation of
S31, S32: step (ii) of
SW1, SW2: switch with a switch body
VIN, VIP: input signal
VON, VOP: decision signal
Vn, vp: a reference voltage.
Claims (10)
1. A successive approximation register analog-to-digital conversion device, comprising:
a first digital-to-analog converter circuit;
a second digital-to-analog converter circuit for cooperating with the first digital-to-analog converter circuit to sample an input signal;
a comparator circuit for generating a plurality of first comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit;
a controller circuit for generating a plurality of first bits and a plurality of second bits according to the first comparison result, and storing the first bits and the second bits, wherein the second bits are used for switching the second digital-to-analog converter circuit; and
a dynamic element matching circuit for encoding the first bit to generate a plurality of third bits for refreshing the first DAC circuit,
the controller circuit is further configured to reset a portion of the second bits after the first digital-to-analog converter circuit is refreshed, generate a plurality of second comparison results according to an output of the first digital-to-analog converter circuit and an output of the second digital-to-analog converter circuit after the portion of the bits are reset, generate a plurality of fourth bits according to the second comparison results, and generate a digital output according to the first bits, the second bits, and the fourth bits.
2. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first bit is a plurality of most significant bits and the second bit is a plurality of least significant bits.
3. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first digital-to-analog converter circuit is further configured to be repeatedly refreshed to reset the partial bits, and the comparator circuit is further configured to repeatedly compare the output of the first digital-to-analog converter circuit with the output of the second digital-to-analog converter circuit after the partial bits are reset to generate the second comparison result.
4. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first digital-to-analog converter circuit has a higher weight than the second digital-to-analog converter circuit.
5. The successive approximation register analog-to-digital conversion device of claim 1, wherein the controller circuit is configured to perform a statistical operation on the portion of bits and the fourth bits to generate a plurality of fifth bits, and combine the remaining bits of the first bits, the second bits, and the fifth bits into the digital output.
6. The successive approximation register analog-to-digital conversion device of claim 5, wherein the remaining bits have higher weights than the partial bits.
7. The successive approximation register analog-to-digital conversion device of claim 5, wherein the controller circuit is configured to average the partial bits and the fourth bit to generate the fifth bit.
8. The successive approximation register analog-to-digital conversion device of claim 1, wherein the dynamic element matching circuit is configured to encode the first bit as a thermometer code and generate the third bit according to the thermometer code.
9. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first digital-to-analog converter circuit comprises a plurality of capacitors, and the first digital-to-analog converter circuit generates an output corresponding to the first comparison result according to the third bit.
10. A method of signal conversion, comprising:
sampling an input signal through the cooperative operation of a first digital-to-analog converter circuit and a second digital-to-analog converter circuit to generate a plurality of first comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit;
generating a plurality of first bits and a plurality of second bits according to the first comparison result, and storing the first bits and the second bits, wherein the second bits are used for switching the second digital-to-analog converter circuit;
encoding the first bit to generate a plurality of third bits to refresh the first digital-to-analog converter circuit;
resetting a portion of the second bits after the first digital to analog converter circuit is refreshed;
after the partial bit is reset, generating a plurality of second comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit;
generating a plurality of fourth bits according to the second comparison result; and
a digital output is generated based on the first bit, the second bit, and the fourth bit.
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| CN202111191315.5A CN115967403A (en) | 2021-10-13 | 2021-10-13 | Successive approximation register type analog-digital conversion device and signal conversion method |
| TW110145308A TWI792741B (en) | 2021-10-13 | 2021-12-03 | Successive approximation register analog to digital converter device and signal conversion method |
| US17/870,958 US12034451B2 (en) | 2021-10-13 | 2022-07-22 | Successive approximation register analog to digital converter device and signal conversion method |
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| US8344921B2 (en) * | 2010-11-04 | 2013-01-01 | Mediatek Inc. | Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method |
| JP5589780B2 (en) * | 2010-11-08 | 2014-09-17 | セイコーエプソン株式会社 | A / D conversion circuit, electronic device, and A / D conversion method |
| TWI484761B (en) * | 2011-11-01 | 2015-05-11 | Himax Tech Inc | Successive approximation register analog-to-digital converter and conversion method |
| KR20140011135A (en) * | 2012-07-17 | 2014-01-28 | 한국전자통신연구원 | Apparatus and method for calibrating offset voltage and continuous time delta sigma modulator including the same |
| TWI497918B (en) * | 2012-12-28 | 2015-08-21 | Ind Tech Res Inst | Analog to digital converter and capacitors weighting evaluating method of digital to analog converter thereof |
| TWI524679B (en) * | 2013-05-03 | 2016-03-01 | 瑞昱半導體股份有限公司 | Successive-approximation-register analog-to-digital converter (sar adc) and method therefor |
| TWI521888B (en) * | 2013-12-31 | 2016-02-11 | 瑞昱半導體股份有限公司 | Successive approximation register analog-to-digital converter and associate control method |
| US9203426B2 (en) * | 2014-04-07 | 2015-12-01 | Analog Devices Global | Estimation of digital-to-analog converter static mismatch errors |
| US10001406B2 (en) * | 2016-06-07 | 2018-06-19 | Semiconductor Components Industries, Llc | Charge packet signal processing using pinned photodiode devices |
| US10050639B1 (en) * | 2017-11-29 | 2018-08-14 | Nxp Usa, Inc. | Partially asynchronous clock scheme for SAR ADC |
| TWI672006B (en) * | 2018-09-28 | 2019-09-11 | 新唐科技股份有限公司 | Successive approximation register analog-to-digital converter and control method thereof |
| KR20210091757A (en) * | 2018-12-10 | 2021-07-22 | 아나로그 디바이시즈 인코포레이티드 | Compensation for metastability of asynchronous SAR within delta sigma modulator loop |
| US10778242B2 (en) * | 2019-01-11 | 2020-09-15 | Realtek Semiconductor Corporation | Analog-to-digital converter device |
| US11711089B2 (en) * | 2019-04-05 | 2023-07-25 | Telefonaktiebolaget Lm Ericsson (Publ) | SAR ADC with alternating low and high precision comparators and uneven allocation of redundancy |
| TWI685210B (en) * | 2019-06-14 | 2020-02-11 | 瑞昱半導體股份有限公司 | Successive approximation register analog-to-digital converter and operation method thereof |
| TWI717958B (en) * | 2019-12-31 | 2021-02-01 | 財團法人工業技術研究院 | Successive approximation register analog-to-digital converter with calibration function and calibration method thereof |
| TWI792438B (en) * | 2021-07-22 | 2023-02-11 | 瑞昱半導體股份有限公司 | Signal converter device, dynamic element matching circuit, and dynamic element matching method |
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| US12034451B2 (en) | 2024-07-09 |
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| US20230116785A1 (en) | 2023-04-13 |
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