RU2319299C1 - Multi-input logical "and" element on cmos transistors - Google Patents

Abstract

FIELD: computer engineering, possible use in MOS integration circuits during realization of logical devices.

SUBSTANCE: device contains AND-NOT element (1), inverting element (2), clock transistors (3) and (4) of n-type and p-type respectively, additional transistor (5) of n-type. The AND-NOT element (1) contains pre-charge transistor (6) of p-type and key circuit (7), made on serially connected transistors of n-type, gates of which are connected to inputs (8) of device. Pre-charge transistor (6) is coupled between power bus (9) and output (10) of AND-NOT element (1). First contact (11) of key circuit (7) of AND-NOT element (1) is connected to output (10) of AND-NOT element (1), and second contact (12) through clock transistor (3) is connected to zero bus (13), clock transistor (4) is coupled between power bus (9) and second contact (12) of key circuit (7). Gates of clock transistors (3,4) and pre-charge transistor (6) are connected to clock bus (14). Inverting element (2) contains logical transistor (15) of p-type, coupled between power bus (9) and output (16) and pre-charge transistor (17) of n-type, coupled between output of device and zero bus, gates of transistors (15,17) of inverting element (2) are connected respectively to output (10) and to second output (12) of key circuit (7). Additional transistor (5), gate of which is connected to output (16) of device, is coupled between output (10) of device and second output (12) of key circuit (7).

EFFECT: increased speed of device operation.

1 dwg

Description

The invention relates to the field of computer technology and can be used in CMDP integrated circuits for the implementation of logical devices.

Known clocked logic element And type "dominoes" with multiple inputs (US Patent No. 5208489, FIG.1, H03K 19/094, NKI 307/451 from 05/04/1993). It contains an NAND element with a p-type precharge transistor, a key circuit on n-type transistors, and an output static inverter. The disadvantage of this element is the limited speed, which is associated with the presence of several series-connected transistors of the key circuit and the load of the output inverter.

The closest technical solution to the proposed one is a logic element on KMDP transistors with the And function for several inputs (RF Patent No. 2275737, Н03К 19/01, 19/094 of December 6, 2004). This device, taken as a prototype, contains an AND-NOT element, an inverting element and two clock transistors. The NAND element contains a p-type pre-charge transistor and a logic part in the form of a key circuit made on series-connected n-type transistors, and the inverting element contains a p-type logic transistor and an n-type pre-charge transistor. The disadvantage of this device is the limited performance with a large number of inputs on And, which is due to the slow process of switching the element AND-NOT.

The technical problem solved in the invention is to increase the speed of the device. This goal is achieved by the fact that the multi-input logic element AND on the CMSC transistors, containing the AND-NOT element, an inverting element, an n-type clock transistor and a p-type clock transistor, an AND-NOT element contains a p-type precharge transistor connected between the power bus and the output of this element, and the key circuit, consisting of series-connected transistors of n-type, the gates of which are connected to the inputs of the device, the first output of the key circuit is connected to the output of the element AND NOT, and the second output through the clock transistor n- type is connected to the zero bus, a p-type clock transistor is connected between the power bus and the second output of the NAND element key circuit, an inverting element contains a p-type logic transistor connected between the power bus and the device output, and an n-type precharge transistor included between the output of the device and the zero bus, the gates of the clock transistors and the p-type pre-charge transistor are connected to the clock bus, the gates of the p-type logic transistor and the n-type pre-charge transistor of the inverting element are connected respectively To the output of the NAND element and to the second terminal of the key circuit of the NAND element, it contains an additional n-type transistor that is connected between the output of the NAND element and the second terminal of the key circuit of the same element and whose gate is connected to the output of the device, The device contains at least 8 inputs.

Significant distinguishing features in this set of features is the presence of an additional n-type transistor, which, together with new connections, forms an additional feedback circuit in parallel with the key circuit of the AND-NOT element.

The presence in the proposed device of the above essential features provides a solution to the technical problem - improving the performance of the device. In the known device, when the AND function is implemented, the AND-NOT element is switched through the key circuit with the presence of several series-connected transistors of n-type transistors, and with a large number of inputs, the inverting element switches additionally through several series-connected logical p-type transistors, which limits the performance multi-input element I. In the proposed device, the switching of the AND-NOT element through the key chain occurs only at the initial stage - until reaching the output threshold voltage devices of n-type transistors, which is not more than 20% of the supply voltage. Further, the formation of the output signal to the supply voltage level is carried out when the AND-NOT element is switched through an additional n-type transistor, the resistance of which is much less than the resistance of the key circuit, which increases the speed of the multi-input And element and allows the use of n-type transistors with minimal geometric dimensions with the smallest input capacity, which further leads to increased device performance.

The drawing shows a schematic diagram of the inventive multi-input logic element AND on the CMDT transistors.

The multi-input logic element on the CMSC transistors contains an AND-1 element, an inverting element 2, clock transistors 3 and 4, respectively, of n-type and p-type, an additional transistor 5 of n-type. The AND-NOT 1 element contains a p-type pre-charge transistor 6 and a key circuit 7 made on series-connected n-type transistors, the gates of which are connected to the inputs of the device 8. A p-type pre-charge transistor 6 is connected between the power bus 9 and the output 10 of the NAND element. The first terminal 11 of the key circuit 7 of the AND-NOT element is connected to the output 10 of the AND-NOT element, and the second terminal 12 is connected via the n-type clock transistor 3 to the zero bus 13. The p-type clock transistor 4 is connected between the power bus 9 and the second terminal 12 of the key circuit 7 of the AND-NOT element 1. The gates of the clock transistors 3, 4 and the pre-charge transistor 6 are connected to the clock bus 14.

The inverting element 2 contains a p-type logic transistor 15 connected between the power bus 9 and the device output 16, and an n-type pre-charge transistor 17 connected between the device output 16 and the zero bus 13. The gates of the p-type logic transistor 15 and the pre-charge transistor 17 n-type inverting element 2 are connected respectively to the output 10 and to the second terminal 12 of the key circuit 7 of the element AND.

An additional transistor 5 is an n-type transistor, the gate of which is connected to the output 16 of the device, is connected between the output 10 and the second output 12 of the key circuit 7 of the AND-NOT 1 element.

The device operates as follows. In the initial state - on the first half-cycle, with a zero signal on the clock bus 14, the n-type clock transistor 3 is closed, and the p-type clock transistor 4 and the p-type precharge transistor 6 are open. From the supply bus 9 through the pre-charge transistors 6 and 4 p-type, the process of pre-charging occurs to the logical level 1, equal to the voltage on the supply bus 9, node capacitances associated with the output 10 of the AND-NOT element and with the second output 12 of the key circuit 7 of the same element . As a result, the p-type logic transistor 15 of the inverting element 2 is closed, and the n-type precharge transistor 17 is open. At the output 16 of the device, a logic 0 signal is set. On the first half-cycle, the signals corresponding to the input variables are set at the inputs of the device 8.

In the second half-cycle, after applying a positive signal to the clock bus 14, the n-type clock transistor 3 opens, and the p-type clock transistor 4 and the p-type precharge transistor 6 are closed. The n-type clock transistor 3 with a large channel width provides a fast discharge of the capacitive load associated with the second terminal 12 of the key circuit 7, and the n-type precharge transistor 17 is closed, which prepares the output 16 of the device to generate an output signal. If all the signals supplied to the inputs of the device 8, according to the AND function, correspond to logical 1, the key circuit 7 is in a conducting state and the nodal capacitance of the output 10 of the NAND element starts to discharge through the indicated key circuit and the n-type clock transistor 3. In this case, the p-type logical transistor 15 of the inverting element 2, the gate of which is connected to the output of the AND-NOT element, opens, and the signal level at the output 16 of the device increases. With a large number of device inputs and the small size of the n-type transistors of the key circuit 7, the transition process of the discharge of the nodal capacitance associated with the output 10 of the AND-NOT element would proceed rather slowly, as in the prototype device. When the output voltage 16 of the device reaches the threshold voltage for n-type transistors, an additional n-type transistor 5 opens and the discharge rate of the nodal capacitance associated with the output 10 of the NAND element increases significantly, and accordingly, the p-type logical transistor 15 opens and the signal at the output 16 of the device grows faster. An additional n-type transistor 5 plays the role of positive feedback and its presence allows the use of n-type transistors in the key circuit 7 with minimum dimensions, which significantly reduces the capacitive load at the inputs of the element 8 and increases the speed when the logic elements are cascaded. With a large number of inputs (at least 8), an additional n-type transistor 5 with the same dimensions as the n-type transistors of the key circuit 7 significantly speeds up the process of generating a logical 1 signal at the output of the device.

When a zero signal is applied to the clock bus 14, the initial state of the element is restored, the n-type clock transistor 3 closes, and the p-type clock transistor 4 and the p-type precharge transistor 6 open. In the range while the signal level at the output 16 of the device is above the threshold, the additional n-type transistor 5 operates in the inverse mode, which increases the charge rate of the nodal capacitance of the output of the 10 AND-NOT element, which also reduces the time to restore the initial state of the element.

Claims (1)

A multi-input AND gate on the KMDP transistors containing an NAND element, an inverting element, an n-type clock transistor and a p-type clock transistor, an NAND gate contains an p-type precharge transistor connected between the power bus and the output of this element, and a key circuit consisting of n-type transistors connected in series, the gates of which are connected to the inputs of the device, the first output of the key circuit is connected to the output of the NAND element, and the second output is connected to the zero bus via an n-type clock transistor, The r-type transistor is connected between the power bus and the second terminal of the key circuit of the NAND element, the inverting element contains a p-type logic transistor connected between the power bus and the device output, and an n-type pre-charge transistor connected between the device output and the zero bus , the gates of the clock transistors and p-type pre-charge transistor are connected to the clock bus, the gates of the p-type logic transistor and p-type transistor of the n-type inverting element are connected respectively to the output of the AND-NOT element and to the second output of the key circuit of the AND-NOT element, characterized in that it contains an additional n-type transistor that is connected between the output of the element AND-NOT and the second output of the key circuit of the same element and whose gate is connected to the output of the device, the device comprising at least 8 inputs.