CN106160745B - Analog-digital commutator and its initial method - Google Patents
Analog-digital commutator and its initial method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
- H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
Analog-digital commutator and its initial method.Analog-digital commutator includes the first switch-capacitor unit, the second switch-capacitor unit, circuit unit, first and second initialisation switch, third and the 4th capacitor and logic gate buffer.First and second switch-capacitor unit makes first and second each capacitor be coupled to the first logic voltage, the second logic voltage or first or second input voltage respectively according to first control signal, and generates first and second voltage respectively.Circuit unit compares first voltage and second voltage to generate first control signal.First and second initialisation switch is serially connected in respectively between first and second voltage and common mode endpoint.Third and the 4th capacitor receive first and second voltage respectively and couple common mode endpoint jointly.Logic gate buffer exports first or second logic voltage to common mode endpoint.
Description
Technical field
The present invention relates to a kind of analog-digital commutators, and in particular to a kind of continuous gradual Analog-digital Converter
Device.
Background technique
Trend in IC design in recent years has more more low-power consumption, higher performance and less cost
Carry out more harsh requirement, and in the design of analog front circuit, an efficient analog-digital converter (Analog
To Digital Converter, abbreviation ADC) system overall performance can be made to greatly improve.
The framework of existing ADC is many kinds of, such as flash type ADC (Flash ADC), pipeline ADC (Pipeline
ADC), continuous gradual ADC (Successive Approximation Register ADC, abbreviation SAR-ADC) and two steps type
ADC(Two-Step ADC).These ADC frameworks have respectively suitable application range.Wherein, under same specification demands,
SAR-ADC can have the advantage of lower power consumption and smaller chip area compared to assembly line (pipeline) formula ADC, also therefore, right
In the technological development of SAR-ADC framework, also gradually paid attention to by industry.
It generally can include the analog buffer to generate common-mode voltage under the framework of existing SAR-ADC
(Analog Buffer).However, the power of analogue buffer can substantially increase when the conversion accuracy of SAR-ADC and higher frequency
Add, the difficulty of circuit design is caused to increase therewith.
Summary of the invention
The present invention provides a kind of analog-digital commutator and its initial method, using digital buffer
(Digital Buffer) replaces the analog buffer in traditional design to carry out output common mode voltage.Whereby, it reduces continuous progressive
The overall power of formula analog-digital commutator, and reduce the difficulty of circuit design.
Analog-digital commutator of the invention includes the first switch-capacitor unit, the second switch-capacitor unit, circuit list
Member, first and second initialisation switch and third and the 4th capacitor.First switch-capacitor unit have multiple first capacitors with
And multiple first switches of corresponding each first capacitor.First switch-capacitor unit is according to first control signal to pass through corresponding the
One of one switch makes each first capacitor be coupled to the first logic voltage, the second logic voltage or the first input voltage, and
Generate first voltage.Second switch-capacitor unit has multiple the second of multiple second capacitors and corresponding each second capacitor to open
It closes.Second switch-capacitor unit is according to first control signal to make each second capacitor by one of corresponding second switch
It is coupled to the first logic voltage, the second logic voltage or the second input voltage, and generates second voltage.Circuit unit foundation compares
First voltage and second voltage generate first control signal.First and second initialisation switch is serially connected in first voltage respectively
Between common mode endpoint and between common mode endpoint and second voltage, and according to second control signal to be turned on or off.Third and
Four capacitors receive first and second voltage respectively, and couple common mode endpoint jointly.Logic gate buffer is selected according to second control signal
The first logic voltage of output or the second logic voltage are selected to common mode endpoint.Wherein second control signal turns to instruction simulation number
Whether changing device is in Sampling time periods.
The initial method of analog-digital commutator of the invention, suitable for above-mentioned analog-digital commutator.Side
Method includes: so that each first capacitor is coupled to the first input voltage in Sampling time periods, so that each second capacitor is coupled to second defeated
Enter voltage；The conducting of the first, second initialisation switch is controlled, and control logic buffer exports the first logic voltage to common mode terminal
Point；It in switching period, controls the first, second initialisation switch and disconnects, and control logic buffer exports the second logic electricity
It is depressed into common mode endpoint；And the is adjusted with continuous progressive mode according to the result being compared with second voltage to first voltage
One control signal, makes each first, second capacitor be coupled to the first logic voltage or the second logic voltage accordingly, generates association whereby
In the digital output signal of the first, second input voltage.
It, can be by digital logic in Sampling time periods based on above-mentioned, of the invention analog-digital commutator
Buffer provides the logic voltage of the first logic level to common mode endpoint, to sample to first and second input voltage.And
And in switching period, it is transformed into and the logic voltage of the second logic level is provided to common mode endpoint and can be carried out continuous
Gradual conversion is to generate the digital output signal for being associated with the first, second input voltage.Whereby, traditional design can smoothly be replaced
In analog buffer carry out Analog-digital Converter, to reduce the overall power and design difficulty of circuit.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is painted the schematic diagram of the analog-digital commutator of one embodiment of the invention.
Fig. 2 is painted the signal waveforms of the analog-digital commutator of one embodiment of the invention.
Fig. 3 is painted the schematic diagram of the analog-digital commutator of one embodiment of the invention.
Fig. 4 is painted the flow chart of the initial method of the analog-digital commutator of one embodiment of the invention.
[symbol description]
100: analog-digital commutator
110,120: switch-capacitor unit
130: circuit unit
131: comparator
132: logic controller
140: logic gate buffer
C11~C1N, C21~C2N, C3, C4: capacitor
CTR1, CTR2: control signal
DOUT: digital output signal
EVCM: common mode endpoint
HL: high logic level
IN1, IN2: input terminal
LL: low logic level
OUT: output end
SW1_1, SW1_2, SW1_3, SW2_1, SW2_2, SW2_3: switch
SWI1, SWI2: initialisation switch
SCMP: comparison signal
T1: time point
Tc: switching period
Ts: Sampling time periods
V1, V2: voltage
VIN1, VIN2: input voltage
VL1, VL2: logic voltage
S410~S440: the step of the initial method of analog-digital commutator
Specific embodiment
The schematic diagram of the analog-digital commutator of Fig. 1 is painted one embodiment of the invention that first, referring to fig. 1,.In this reality
Apply in example, analog-digital commutator 100 include switch-capacitor unit 110, switch-capacitor unit 120, circuit unit 130, just
Beginning Switching SWI1, SWI2, capacitor C3, C4 and logic gate buffer 140.The reception of switch-capacitor unit 110 logic voltage VL1,
Logic voltage VL2 and input voltage VIN 1, and the multiple switch with multiple capacitors and corresponding each capacitor.These switches
Control signal CTR1 can be controlled by allow corresponding each capacitor to be coupled to logic voltage VL1, logic voltage VL2 or input voltage
One of VIN1, so that switch-capacitor unit 110 generates voltage V1.In the present embodiment, logic voltage VL1 is low logic
Level, logic voltage VL2 are high logic level.
Similarly, switch-capacitor unit 120 receives logic voltage VL1, logic voltage VL2 and input voltage VIN 2, and
Multiple switch with multiple capacitors and corresponding each capacitor.It is corresponding each to allow that these switches can be controlled by control signal CTR1
A capacitor is coupled to one of logic voltage VL1, logic voltage VL2 or input voltage VIN 2, so that switch-capacitor unit
120 generate voltage V2.
In Fig. 1, voltage V1 and voltage V2 can be compared and generate control according to comparison result by circuit unit 130
Signal CTR1 processed.Also, when analog-digital commutator 100 carries out Analog-digital Converter, circuit unit 130 can be based on voltage
The comparison result of V1 and voltage V2 are generated and are associated in continuous progressive (successive approximation, SAR) mode
The digital output signal DOUT of input voltage VIN 1 and VIN2.In addition, initialisation switch SWI1, SWI2 is then serially connected in voltage respectively
Between V1 and common mode endpoint EVCM and between common mode endpoint EVCM and voltage V2, and according to control signal CTR2 to be turned on or off.
Capacitor C3 and capacitor C4 then receives voltage V1 and voltage V2 respectively, and couples common mode endpoint EVCM jointly.As shown in Figure 1, electric
Hold C3 and capacitor C4 and is parallel to initialisation switch SWI1, SWI2 respectively.
Logic gate buffer 140 is, for example, digital buffer.In Fig. 1, logic gate buffer 140 receives logic voltage VL1
And logic voltage VL2, and can be according to control signal CTR2 selection output logic voltage VL1 or logic voltage VL2 to common mode endpoint
EVCM.Wherein, whether control signal CTR2 can be used to instruction simulation digital switching device 100 in Sampling time periods.
Specifically, the analog-digital commutator 100 of the embodiment of the present invention can operationally be divided into Sampling time periods
And two period/stages of switching period.Specifically, Fig. 2 is painted the Analog-digital Converter dress of one embodiment of the invention
The signal waveforms set.Referring to figure 2., citing depicts control signal CTR2, voltage V1 (solid line) and voltage V2 in Fig. 2
The waveform of (dotted line) in Sampling time periods Ts and switching period Tc.From the point of view of waveform by control signal CTR2, when
When to control signal CTR2 be high logic level HL (logic 1), it can indicate that analog-digital commutator 100 is in initialize
Sampling time periods Ts.When controlling signal CTR2 is low logic level LL (logical zero), analog-digital commutator can be indicated
100 have entered switching period Tc.It should be noted that in other embodiments, control signal CTR2 can also according to it is aforementioned
The state of the logic level instruction simulation digital switching device 100 of opposite way, the embodiment of the present invention are not limited according to this.
Referring to Fig. 1 and Fig. 2, in the operation of circuit, in Sampling time periods Ts, circuit unit 130 can lead to
Crossing control signal CTR1 makes each capacitor in switch-capacitor unit 110 be coupled to input voltage VIN 1, and makes switch-capacitor unit
Each capacitor in 120 is coupled to input voltage VIN 2.Also, initialisation switch SWI1 and SWI2 can be controlled by for example high logic electricity
The control signal CTR2 of flat HL and be connected, by the connection path short circuit of common mode endpoint EVCM and voltage V1 and V2.Then, logic
Buffer 140 can export logic voltage VL1 to common mode endpoint EVCM according to control signal CTR2.Accordingly, logic gate buffer 140
It can directly be connected with switch-capacitor unit 110 and switch-capacitor unit 120 via common mode endpoint EVCM, and by logic voltage
VL1 is provided to two input terminals of circuit unit 130 in a manner of common mode, to utilize switch-capacitor unit 110 and switch-capacitor
The sampling of unit 120 progress input voltage VIN 1 and input voltage VIN 2.As shown in Fig. 2, in Sampling time periods Ts, circuit
The voltage V1 and V2 of two input terminals of unit 130 are all equal to logic voltage VL1.
Accept above-mentioned, after Sampling time periods Ts, analog-digital commutator 100 can enter switching period
Tc.In switching period Tc, analog-digital commutator 100 can according to digital output signal DOUT digit and including number
A conversion stage.Also, in each conversion stage, analog-digital commutator 100 can continuously progressive mode determine respectively
The place value (i.e. 1 or 0) of position is corresponded in fixed number word output signal DOUT, and in the place value for determining all digital output signal DOUT
Afterwards, Analog-digital Converter is completed.
In the operation of switching period Tc, initialisation switch SWI1 and SWI2 can first be controlled by such as low logic level
The control signal CTR2 of LL and disconnect, also, logic gate buffer 140 can according to transition be low logic level LL control signal
CTR2 and export logic voltage VL2 to common mode endpoint EVCM.With this condition, circuit unit 130 and capacitor C3 and switching electricity
The voltage value for holding the voltage V1 on the endpoint that unit 110 couples will generate offset, wherein deviant Vofs1 can be such as following formula (2)
To indicate:
Wherein, in formula (1), CA1 indicates equivalent capacitance value provided by switch-capacitor unit 110.
In addition, the voltage of the voltage V2 on the endpoint that circuit unit 130 and capacitor C4 and switch-capacitor unit 120 are coupled
Value can similarly generate offset, wherein deviant Vofs2 can be indicated such as following formula (2):
Wherein, in formula (2), CA2 indicates equivalent capacitance value provided by switch-capacitor unit 120.
As shown in Fig. 2, two of circuit unit 130 are defeated when entering switching period Tc by Sampling time periods Ts
The voltage V1 and V2 for entering end can revert to differential form because of breaking with the connection path of common mode endpoint EVCM, and by circuit
Unit 130 comparison voltage V1 and V2.After comparison, circuit unit 130 can determine according to voltage V1 and the comparison result of voltage V2
The place value of the most significant bit (most significant bit, MSB) of fixed number word output signal DOUT.
Next, after the highest order for obtaining digital output signal DOUT, then it can continuous progressive manner adjustment control
Signal CTR1.By the control signal CTR1 gradually changed, each capacitor in switch-capacitor unit 110 and 120 can be changed
The received voltage value of institute, and then change the voltage value of voltage V1 and voltage V2.As shown in Fig. 2, changing voltage V1 in time point T1
And V2, circuit unit 130 can continue to compare the voltage V1 and V2 after changing to determine the next bit of digital output signal DOUT
Place value.Then it repeats the above steps, until circuit unit 130 is with the institute of continuous progressive mode decision digital output signal DOUT
Until the place value for having position, input voltage VIN 1 and the Analog-digital Converter of VIN2 can be completed.
In the present embodiment, logic gate buffer 140 that can be digital in analog-digital commutator 100 replaces analog
Buffer carries out Analog-digital Converter, to reduce the overall power and design difficulty of the circuit when conversion frequency is higher, and
Improve the speed of Analog-digital Converter.Subsidiary one mentions, and logic gate buffer 140 can be in Design of Digital Circuit common reversed
Device is completed.
Referring to FIG. 3, Fig. 3 is painted the signal of an embodiment of the analog-digital commutator of Fig. 1 embodiment of the present invention
Figure.Analog-digital commutator 100 includes switch-capacitor unit 110, switch-capacitor unit 120, circuit unit 130, initialization
Switch SWI1, SWI2, capacitor C3, C4 and logic gate buffer 140.Switch-capacitor unit 110 has multiple capacitor C11~C1N.
Switch-capacitor unit 110 also has the multiple groups switch of corresponding each capacitor C11~C1N.Switch-capacitor unit 110 can be believed according to control
Number CTR1 has switch-capacitor unit 110 come the conducting of one of the switch that controls corresponding each capacitor C11~C1N
Each capacitor C11~C1N is coupled to one of logic voltage VL1, logic voltage VL2 or input voltage VIN 1, and generates electricity
Press V1.
Using capacitor C11 as example, switch SW1_1, SW1_2 and SW1_3 of corresponding capacitor C11 is controlled by control signal
CTR1.Also, when switch SW1_1 is switched on (switch SW1_2 and SW1_3 are disconnected), capacitor C11 receives logic voltage
VL1；When switch SW1_2 is switched on (switch SW1_1 and SW1_3 are disconnected), capacitor C11 receives logic voltage VL2；And work as
When switch SW1_3 is switched on (switch SW1_1 and SW1_2 are disconnected), capacitor C11 then receives input voltage VIN 1.
It should be noted that above-mentioned switch SW1_1, SW1_2 and SW1_3 are in switching period and Sampling time periods
In only one switch can be switched on.That is, can't occur on the endpoint of switch SW1_1~SW1_3 coupled jointly
The phenomenon that transmitting more than two different voltages simultaneously.
In Fig. 3, switch-capacitor unit 120 has multiple capacitor C21~C2N.Switch-capacitor unit 120, which also has, to be corresponded to
The multiple groups of each capacitor C21~C2N switch.Switch-capacitor unit 120 can control corresponding each capacitor C21 according to control signal CTR1
The conducting of one of switch of~C2N, each capacitor C21~C2N for having switch-capacitor unit 120 are coupled to logic electricity
One of VL1, logic voltage VL2 or input voltage VIN 2 are pressed, and generates voltage V2.
Using capacitor C21 as example, switch SW2_1, SW2_2 and SW2_3 of corresponding capacitor C21 is controlled by control signal
CTR1.Also, when switch SW2_1 is switched on (switch SW2_2 and SW2_3 are disconnected), capacitor C21 receives logic voltage
VL1；When switch SW2_2 is switched on (switch SW2_1 and SW2_3 are disconnected), capacitor C21 receives logic voltage VL2；And work as
When switch SW2_3 is switched on (switch SW2_1 and SW2_2 are disconnected), capacitor C21 then receives input voltage VIN 2.Similarly,
Being controlled by the endpoint of switch SW2_1~SW2_3 of control signal CTR1 coupled jointly will not also occur to transmit two simultaneously
The phenomenon that above different voltages.
In addition, can have certain proportionate relationship between the capacitance of capacitor C11~C1N in switch-capacitor unit 110.
For example, the capacitance of capacitor C11~C1N can be arranged according to 2 power side, that is to say, that the capacitance of capacitor C12
Twice for can be the capacitance of capacitor C11 is big, and the capacitance of capacitor C1N then can be the 2 of the capacitance of capacitor C11(N-1)。
It is similar with switch-capacitor unit 110, between the capacitance of capacitor C21~C2N in switch-capacitor unit 120
There can be certain proportionate relationship.For example, the capacitance of capacitor C21~C2N can be arranged according to 2 power side,
That is the capacitance of capacitor C22 can be twice of the capacitance of capacitor C21 greatly, and the capacitance of capacitor C2N then can be
The 2 of the capacitance of capacitor C21(N-1)。
Circuit unit 130 includes comparator 131 and logic controller 132.Comparator 131 has input terminal IN1, input
Hold IN2 and output end OUT.The input terminal IN1 of comparator 131 receives voltage V1, and the input terminal IN2 of comparator 131 receives electricity
V2 is pressed, logic controller 132 then couples the output end OUT of comparator 131.In the present embodiment, logic controller 132 is to mention
For controlling signal CTR1 and CTR2, and can comparison signal SCMP caused by the output end OUT according to comparator 131 with continuous
Progressive mode adjustment control signal CTR1.Accordingly, after the Analog-digital Converter of continuous progressive mode, logic controller
132 exportable converted digital output signal DOUT.It should be noted that in other embodiments, control signal CTR2 can also
It is provided by other signal generation units, the embodiment of the present invention is not limited according to this.
In the present embodiment, comparator 131 can be any type of comparator well-known to those skilled in the art, or
It is also possible to delayed comparator.In addition, logic controller 132 then can be continuous progressive (successive
Approximation, SAR) logic controller.
Fig. 4 is painted the flow chart of the initial method of the analog-digital commutator of one embodiment of the invention.The present invention is real
The initial method for applying example is suitable for the analog-digital commutator 100 of Fig. 1.Fig. 1 and Fig. 4 is please referred to, in step S410,
Sampling time periods make each capacitor of switch-capacitor unit 110 be coupled to input voltage VIN 1, make switch-capacitor unit 120
Each capacitor is coupled to input voltage VIN 2.Also, in the step s 420, control initialisation switch SWI1 and SWI2 conducting, and control
Logic gate buffer 140 processed exports logic voltage VL1 to common mode endpoint EVCM.Then, in step S430, in conversion time week
Phase, control initialisation switch SWI1 and SWI2 are disconnected, and control logic buffer 140 exports logic voltage VL2 to common mode endpoint
EVCM.Also, in step S440, is adjusted and controlled with continuous progressive mode according to the result being compared to voltage V1 with voltage V2
Signal CTR1 processed makes each capacitor C11~C1N and each capacitor C21~C2N be coupled to logic voltage VL1 or logic voltage accordingly
VL2 is generated be associated with input voltage VIN 1 and the digital output signal DOUT of VIN2 whereby.
In addition, about in above-mentioned Fig. 4, the implementation detail of the execution step of the initial method of analog-digital commutator,
It is all discussed in detail in multiple embodiments above-mentioned and multiple embodiments, below without repeating more.
In conclusion the present invention can realize continuous gradual Analog-digital Converter by digital logic gate buffer.
Whereby, it can smoothly replace the analog buffer in traditional design to carry out Analog-digital Converter, reduce the overall power of circuit
And design difficulty, to improve the overall performance of Analog-digital Converter.
Claims (7)
1. a kind of analog-digital commutator, comprising:
First switch-capacitor unit, multiple first switches with multiple first capacitors and the corresponding respectively first capacitor, foundation
First control signal with by one of these corresponding first switches make respectively the first capacitor be coupled to the first logic electricity
Pressure, the second logic voltage or the first input voltage, and generate first voltage；
Second switch-capacitor unit, multiple second switches with multiple second capacitors and corresponding respectively second capacitor, foundation
The first control signal with by one of these corresponding second switches make respectively second capacitor be coupled to this and first patrol
Voltage, second logic voltage or the second input voltage are collected, and generates second voltage；
Circuit unit, foundation compare the first voltage and the second voltage to generate the first control signal；
First and second initialisation switch, be serially connected between the first voltage and common mode endpoint respectively and the common mode endpoint and this
Between two voltages, and according to second control signal to be turned on or off；
Third and the 4th capacitor, receive respectively this first and the second voltage, and couple the common mode endpoint jointly；And
Logic gate buffer selects output first logic voltage or second logic voltage total to this according to the second control signal
Mould endpoint,
Wherein, the second control signal is to indicate whether the analog-digital commutator is in Sampling time periods.
2. analog-digital commutator as described in claim 1, wherein the circuit unit includes:
Comparator, have first input end, the second input terminal and output end, the first input end of the comparator couple this first
Second input terminal of voltage, the comparator couples the second voltage；And
Logic controller couples the output end of the comparator, to provide this first and the second control signal, in the sampling
Between the period, the logic controller by the first control signal make these each first capacitors be coupled to first input voltage and
These each second capacitors are made to be coupled to second input voltage.
3. analog-digital commutator as claimed in claim 2, wherein the logic controller passes through in the Sampling time periods
First, second initialisation switch is connected in the second control signal, and the logic gate buffer is made to export first logic electricity
It is depressed into the common mode endpoint.
4. analog-digital commutator as claimed in claim 2, wherein in a switching period, the logic controller foundation
Comparison signal caused by the output end of the comparator adjusts the first control signal with continuous progressive mode, make accordingly it is each these
The first, these second capacitors are coupled to first logic voltage or second logic voltage, whereby generate be associated with this first, should
One digital output signal of the second input voltage, wherein the switching period is after the Sampling time periods.
5. analog-digital commutator as claimed in claim 4, wherein the logic controller passes through in the switching period
The second control signal disconnects first, second initialisation switch, and the logic gate buffer is made to export second logic electricity
It is depressed into the common mode endpoint, and each first, second input terminal of the comparator is made to generate the first, second offset voltage respectively.
6. analog-digital commutator as claimed in claim 5, wherein respectively first, second offset voltage is equal to:
Wherein, CB is the capacitance of the third or the 4th capacitor, and VL1, VL2 are the voltage value of first, second logic voltage,
CA is then equivalent capacitance value provided by the first switch-capacitor unit or the second switch-capacitor unit.
7. a kind of initial method of analog-digital commutator is suitable for Analog-digital Converter as described in claim 1 and fills
It sets, comprising:
In Sampling time periods, these each first capacitors is made to be coupled to first input voltage, makes each these second capacitors coupling
To second input voltage；
Control first, second initialisation switch conducting, and control the logic gate buffer export first logic voltage to should
Common mode endpoint；
In switching period, control first, second initialisation switch disconnection, and control the logic gate buffer export this
Two logic voltages are to the common mode endpoint；And
First control is adjusted with a continuous progressive mode according to the result being compared to the first voltage with the second voltage
Signal makes these each first, these second capacitors be coupled to first logic voltage or second logic voltage accordingly, produces whereby
The raw digital output signal for being associated with first, second input voltage.
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| CN201510149665.3A CN106160745B (en) | 2015-03-31 | 2015-03-31 | Analog-digital commutator and its initial method |
| TW104112057A TWI583139B (en) | 2015-03-31 | 2015-04-15 | Analog to digital converting apparatus and initial method thereof |
| US14/726,625 US9276596B1 (en) | 2015-03-31 | 2015-06-01 | Analog to digital converting apparatus and initial method thereof |
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| US10715037B2 (en) * | 2016-08-05 | 2020-07-14 | The University Of Hong Kong | High-efficiency switched-capacitor power supplies and methods |
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| TWI583139B (en) | 2017-05-11 |
| TW201635719A (en) | 2016-10-01 |
| CN106160745A (en) | 2016-11-23 |
| US9276596B1 (en) | 2016-03-01 |
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