CN114595658A - Design method of row decoding circuit and related equipment - Google Patents

Design method of row decoding circuit and related equipment Download PDF

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Publication number
CN114595658A
CN114595658A CN202210222590.7A CN202210222590A CN114595658A CN 114595658 A CN114595658 A CN 114595658A CN 202210222590 A CN202210222590 A CN 202210222590A CN 114595658 A CN114595658 A CN 114595658A
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decoder
splicing
line
level
module
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许婷
韩郑生
闫珍珍
郭燕萍
高立博
王成成
卜建辉
刘海南
赵发展
罗家俊
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a design method and related equipment of a row decoding circuit, relates to the technical field of integrated circuits, and can solve the problem that an existing customized development decoding circuit cannot be multiplexed. The design method of the row decoding circuit comprises the following steps: in a circuit layout design environment, calling a primary decoder structure packet required by a primary row decoding module, a secondary decoder structure packet required by a secondary row decoding module and a splicing module respectively according to decoding capacity; electrically connecting a first-level output end of the binary decoder in the first-level decoder structure package with a first splicing connecting line of the splicing module, and electrically connecting a second-level input end of the logic gate cascade device in the second-level decoder structure package with a second splicing connecting line of the splicing module; and forming electric connection between the first splicing connecting line and the second splicing connecting line through punching.

Description

Design method of row decoding circuit and related equipment
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method for designing a row decoding circuit and a related device.
Background
The memory is an important part of a large-scale integrated circuit, and can improve the efficiency of a system, reduce power consumption and reduce packaging cost. In the design phase, the required Memory can be generated from a Memory Compiler generator, which is very important to the user in terms of area, power consumption, and speed. In order to realize a memory compiler with small generation area, low power consumption and high speed, a layout generation method of an SRAM (static random access memory) global decoding circuit is important. The SRAM structure mainly comprises a decoding circuit, a storage array and the like. On the whole SRAM chip, the most occupied area is the storage array, and the decoding circuit is arranged in the second place. Decoding circuitry is an important structure for selecting a particular row and column of memory cells.
However, the existing decoding circuit adopts a customized development mode, and the decoding circuit layout cannot be multiplexed, so that the decoding circuit is not suitable for realizing Memory Compiler.
Disclosure of Invention
The embodiment of the application provides a design method of a row decoding circuit and related equipment, which can solve the problem that the conventional decoding circuit cannot be reused in customized development.
In a first aspect of the embodiments of the present application, a method for designing a row decoding circuit is provided, including:
in a circuit layout design environment, calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
electrically connecting a first-level output end of the binary decoder in the called first-level decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting a second-level input end of the logic gate cascading device in the called second-level decoder structure packet with a second splicing connecting line of the splicing module;
and forming electric connection between the first splicing connecting line and the second splicing connecting line through punching.
In some embodiments, the logic gate cascade device includes at least three of the secondary inputs, each of the secondary inputs is used for connecting to the corresponding primary output of a different binary decoder, and the electrically connecting the first and second splicing connecting lines by punching includes:
and electrically connecting the first splicing connecting line and the second splicing connecting line through punching so as to enable at least any two primary output ends to be connected to the same logic gate cascade device.
In some embodiments, the first-level row decoding module includes a low-level decoder, a middle-level decoder and a high-level decoder, the logic gate cascade device includes three second-level input terminals, and the three second-level input terminals are respectively connected to any one of the first-level output terminals corresponding to the low-level decoder, the middle-level decoder and the high-level decoder.
In some embodiments, two adjacent logic gate cascade devices are a decoder unit, each of the decoder units includes a first unit input terminal, a second unit input terminal, a third unit input terminal, and a fourth unit input terminal;
will first concatenation connecting wire with second concatenation connecting wire forms the electricity through punching and connects, include:
and electrically connecting the first splicing connecting wire and the second splicing connecting wire through punching, so that the input end of the first unit is electrically connected with any one of the first-level output ends corresponding to the low-level decoder, the input end of the second unit is electrically connected with any one of the first-level output ends corresponding to the medium-level decoder, the input end of the third unit is electrically connected with any one of the first-level output ends corresponding to the high-level decoder, the input end of the fourth unit is electrically connected with any one of the first-level output ends corresponding to the low-level decoder, and the input end of the fourth unit is electrically connected with the first unit input end at different first-level output ends.
In some embodiments, in the circuit layout design environment, the calling a primary decoder structure packet required by a primary row decoding module, a secondary decoder structure packet required by a secondary row decoding module, and a splicing module according to decoding capacity includes:
in the circuit layout design environment, under the condition that the value of the decoding capacity is 32, the first-level decoder structure packet corresponding to one 3-line-8-line decoder and one 2-line-4-line decoder, the second-level decoder structure packet corresponding to 32 logic gate cascade devices and the splicing module corresponding to the number of lines are respectively called.
In some embodiments, in the circuit layout design environment, the calling a primary decoder structure packet required by a primary row decoding module, a secondary decoder structure packet required by a secondary row decoding module, and a splicing module according to decoding capacity includes:
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 33 and 64, the first-level decoder structure packages corresponding to two 3-line-8-line decoders, the second-level decoder structure packages corresponding to the logic gate cascade devices with the same number as the value of the decoding capacity and the splicing modules with the corresponding line number are respectively called; or the like, or, alternatively,
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 65 and 128, the first-level decoder structure packages corresponding to two 3-line-8-line decoders and one 1-line-2-line decoder, the second-level decoder structure packages corresponding to the logic gate level connection devices with the same number as the value of the decoding capacity and the splicing modules with the corresponding line number are respectively called; or the like, or, alternatively,
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 129-256, the first-level decoder structure packages corresponding to two 3-line-8-line decoders and one 2-line-4-line decoder, the second-level decoder structure packages corresponding to the logic gate cascade devices with the same number of values of the decoding capacity and the splicing modules with the corresponding line number are respectively called; or the like, or, alternatively,
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 257 and 512, the first-level decoder structure packet corresponding to three 3-line-8-line decoders, the second-level decoder structure packets corresponding to the logic gate cascade devices with the same number as the value of the decoding capacity, and the splicing modules with the corresponding line number are respectively called.
In a second aspect of the embodiments of the present application, there is provided a device for generating a decoding circuit, including:
the calling module is used for calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity in a circuit layout design environment, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
the connection module is used for electrically connecting the primary output end of the binary decoder in the called primary decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting the secondary input end of the logic gate cascade device in the called secondary decoder structure packet with a second splicing connecting line of the splicing module;
and the punching module is used for electrically connecting the first splicing connecting line with the second splicing connecting line through punching.
In a third aspect of embodiments of the present application, there is provided an electronic device, including:
a memory having a computer program stored therein;
a processor for implementing the method of designing a row decoding circuit as described in the first aspect when executing the computer program.
In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and the computer program, when executed by a processor, implements the method for designing a line decoding circuit according to the first aspect.
In a fifth aspect of the embodiments of the present application, a row decoding circuit is provided, which is generated by applying the design method of the decoding circuit according to the first aspect, and the row decoding circuit includes:
a primary row decoding module comprising at least one binary decoder;
and the secondary row decoding module comprises at least one logic gate cascade device, and the primary output end of the binary decoder is electrically connected with the secondary input end of the logic gate cascade device.
The design method and the related device of the row decoding circuit provided by the embodiment of the application adopt customized development aiming at the existing decoding circuit, are not suitable for multiplexing, and can not be used in Memory Compiler. In a circuit layout design environment, a primary decoder structure packet required by a primary row decoding module, a secondary decoder structure packet required by a secondary row decoding module and a splicing module are respectively called according to decoding capacity. And electrically connecting the primary output end of the binary decoder in the called primary decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting the secondary input end of the logic gate cascading device in the called secondary decoder structure packet with a second splicing connecting line of the splicing module. And electrically connecting the first splicing connecting line with the second splicing connecting line through punching. After the number of binary decoders and the types of the corresponding binary decoders required by the primary row decoding module and the number of logic gate cascade devices required by the secondary row decoding module are determined, the decoder structure packages with the corresponding number and types can be directly called, and the generation efficiency of the decoding circuit can be improved. And the line decoding circuits with different decoding capacities can be generated according to the requirement of the target storage capacity, and the expansion of the line decoding circuit of the corresponding memory can be adapted. The position of punching can be determined according to the connection mode of the primary output end and the secondary input end, so that the splicing module can be applied to various connection schemes, and the splicing module can be used as a template to be called and applied to generate row decoding circuits with different circuit structures. The automatic generation of the row decoding circuit can be realized, the row decoding circuit can be automatically obtained by inputting the decoding capacity, and the design technology of the decoding circuit is simplified.
Drawings
Fig. 1 is a schematic flow chart of a method for designing a row decoding circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic block diagram of a row decoding circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural block diagram of a logic gate cascade device provided in an embodiment of the present application;
fig. 4 is a schematic block diagram of a decoder unit according to an embodiment of the present application;
fig. 5 is a schematic diagram of a splicing of a row decoding circuit according to an embodiment of the present disclosure;
FIG. 6 is a block diagram illustrating a schematic structure of a design apparatus of a row decoding circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic structural block diagram of an electronic device according to an embodiment of the present application;
FIG. 8 is a block diagram illustrating an exemplary structure of a computer-readable storage medium according to an embodiment of the present application;
fig. 9 is a schematic structural block diagram of a memory circuit provided in an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations on the technical solutions of the embodiments of the present specification, and the technical features in the embodiments and examples of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes the case of two or more.
The memory is an important part of a large-scale integrated circuit, and can improve the efficiency of a system, reduce power consumption and reduce packaging cost. In the design phase, the required Memory can be generated, typically from the Memory Compiler's generator, the area, power consumption, and speed of the generated Memory being very important to the user. The layout generation method of SRAM global decoding is important for realizing a memory compiler with small generation area, low power consumption and high speed. The SRAM structure mainly comprises a decoding circuit, a storage array and the like. On the whole SRAM chip, the most occupied area is the storage array, and the decoding circuit is arranged in the second place. Decoding circuitry is an important structure for selecting a particular row and column of memory cells. However, the conventional decoding circuit adopts a customized development mode, and the circuit structure cannot be multiplexed, so that the decoding circuit is not suitable for Memory Compiler.
In view of this, embodiments of the present disclosure provide a method and related apparatus for designing a column decoding circuit, which can solve the problem that the existing decoding circuit module cannot be reused.
In a first aspect of the embodiments of the present application, a method for designing a row decoding circuit is provided, and fig. 1 is a schematic flow chart of the method for designing a row decoding circuit provided in the embodiments of the present application. As shown in fig. 1, a method for designing a row decoding circuit provided in an embodiment of the present application includes:
s100: in a circuit layout design environment, a first-level decoder structure package required by a first-level row decoding module, a second-level decoder structure package required by a second-level row decoding module and a splicing module are respectively called according to decoding capacity, wherein the first-level decoder structure package comprises circuit structures of various binary decoders, the second-level decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line. In a circuit layout design environment, the number of binary decoders and the corresponding types of binary decoders required by the primary row decoding module and the number of logic gate cascade devices required by the secondary row decoding module can be determined according to the target storage capacity of a target memory. Because the decoding circuit for direct decoding causes the problems of large layout area requirement and slow decoding speed of the decoding circuit, it is difficult to satisfy the SRAM with large storage capacity. The decoding circuit designed in the design method of the row decoding circuit provided by the embodiment of the application is provided with the first-level row decoding module and the second-level row decoding module, so that two-level decoding can be realized, the decoding digits can be increased by the cascaded first-level row decoding module and the cascaded second-level row decoding module, the decoding capacity is increased, the decoding speed is improved, the time delay and the power consumption are reduced, and the occupied area of the row decoding circuit is smaller under the condition of the same decoding capacity. In the design stage of the row decoding circuit or the design stage of the memory, the row decoding circuit can be designed in a circuit layout design environment, and then the number of binary decoders required by a first-stage row decoding module in the row decoding circuit and the corresponding type of the binary decoders required by the first-stage row decoding module can be determined according to the target storage capacity of the target memory, the types of the binary decoders required by the first-stage row decoding usually comprise a 1-line-2-line decoder, a 2-line-4-line decoder and a 3-line-8-line decoder, the 1-line-2-line decoder represents the binary decoder of 1 input line and 2 output lines, the 2-line-4-line decoder represents the binary decoder of 2 input lines and 4 output lines, and the 3-line-8-line decoder represents the binary decoder of 3 input lines and 8 output lines, the corresponding binary decoders may be 1-line-2-line decoders, 2-line-4-line decoders, and 3-line-8-line decoders. The output line of the binary decoder in the first-level row decoding module is connected with the input line of the logic gate cascade device in the second-level row decoding module. After the number and the type are determined, the decoder structure package needs to be further called according to the number of the binary decoders required by the primary row decoding module, the corresponding binary decoder type and the number of the logic decoders required by the secondary row decoding module. The first-level row decoding module correspondingly calls the first-level decoder structure package, the second-level row decoding module correspondingly calls the second-level decoder structure package, the first-level decoder structure package comprises circuit structures of various binary decoders, the second-level decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises splicing connecting lines. The decoder structure package can be a circuit structure of an existing decoder in a circuit layout design environment, after the number of binary decoders and the types of the corresponding binary decoders needed by the first-level row decoding module and the number of logic decoders needed by the second-level row decoding module are determined, the decoder structure packages with the corresponding numbers and types can be directly called, and the generation efficiency of the decoding circuit can be improved. The line decoding circuits with different capacities can be generated according to the requirement of the target storage capacity, and the expansion of the line decoding circuit of the corresponding memory can be adapted. Each decoder structure includes, for example, a circuit structure of a binary decoder or a circuit structure of a logic gate cascade device, and the embodiments of the present application are not limited in particular. The number of the splicing connecting lines in the called splicing module corresponds to the output and the input of the first-level decoder structure packet and the second-level decoder structure packet.
S200: and electrically connecting the primary output end of the binary decoder in the called primary decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting the secondary input end of the logic gate cascading device in the called secondary decoder structure packet with a second splicing connecting line of the splicing module. The splicing module comprises a first splicing connecting line and a second splicing connecting line, the output end of the binary decoder is a first-level output end, the input end of the logic gate cascade device is a second-level input end, the first-level output end is electrically connected with the first splicing connecting line, and the second-level input end is electrically connected with the second splicing connecting line. Illustratively, if the first splicing connecting line and the second splicing connecting line in the splicing module are designed to be the same connecting line, the connection mode of the first-level decoder structure packet and the second-level decoder structure packet spliced by the splicing module is fixed.
S300: and electrically connecting the first splicing connecting line with the second splicing connecting line through punching. The first splicing connecting line and the second splicing connecting line in the splicing module are electrically connected through punching, and then the first-level output end in the first-level decoder structure packet can be electrically connected with the second-level input end in the second-level decoder structure packet. The first splicing connecting line and the second splicing connecting line are electrically connected in a punching mode, and the punching position can be determined according to the connection mode of the primary output end and the secondary input end, so that the splicing module can be applied to various connection schemes, and can be used as a template to be called and applied to generate row decoding circuits with different circuit structures.
The design method of the row decoding circuit provided by the embodiment of the application adopts customized development aiming at the existing decoding circuit, is not suitable for multiplexing, and can not be used in Memory Compiler. In a circuit layout design environment, a primary decoder structure packet required by a primary row decoding module, a secondary decoder structure packet required by a secondary row decoding module and a splicing module are respectively called according to decoding capacity. And electrically connecting the primary output end of the binary decoder in the called primary decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting the secondary input end of the logic gate cascading device in the called secondary decoder structure packet with a second splicing connecting line of the splicing module. And electrically connecting the first splicing connecting line with the second splicing connecting line through punching. After the number of binary decoders and the types of the corresponding binary decoders required by the primary row decoding module and the number of logic gate cascade devices required by the secondary row decoding module are determined, the decoder structure packages with the corresponding number and types can be directly called, and the generation efficiency of the decoding circuit can be improved. And the line decoding circuits with different decoding capacities can be generated according to the requirement of the target storage capacity, and the expansion of the line decoding circuit of the corresponding memory can be adapted. The position of punching can be determined according to the connection mode of the primary output end and the secondary input end, so that the splicing module can be applied to various connection schemes, and the splicing module can be used as a template to be called and applied to generate row decoding circuits with different circuit structures. The automatic generation of the row decoding circuit can be realized, the row decoding circuit can be automatically obtained by inputting the decoding capacity, and the design technology of the decoding circuit is simplified.
In some embodiments, fig. 2 is a schematic block diagram of a row decoding circuit provided in an embodiment of the present application. As shown in fig. 2, a row decoder obtained by the method for designing a row decoding circuit according to the embodiment of the present application includes a primary row decoding module 100, a secondary row decoding module 200, and a concatenation module 300, where the primary row decoding module 100 includes at least one binary decoder. The binary decoder can translate various states of the input binary code into corresponding output types according to the original meaning, and the n lines are commonly used as 2nLine decoders, i.e. input lines having n, output lines having 2nRoot, input and output line specification is n line-2nThe conventional binary decoder includes 1-2-line decoder, 2-4-line decoder and 3-8-line decoderAnd a coder. The secondary row decoding module 200, the secondary row decoding module 200 includes at least one logic gate cascade device, and the primary output end of the binary decoder is electrically connected to the secondary input end of the logic gate cascade device. The number of the logic gate cascade devices may be determined by the number of output lines of all the binary decoders, or the number of the logic gate cascade devices may be determined by the storage capacity of the memory accessed by the row decoding circuit, and the embodiment of the present application is not particularly limited.
In some embodiments, the row decoder obtained by the method for designing a row decoding circuit provided in this embodiment may further include other modules 400, the other modules 400 may include a column decoding module and/or a column gating module, and the other modules 400 may also be other kinds of modules, which is not specifically limited in this embodiment. The data flow of the decoded data may be: the decoded row address data is input to the primary row decoding module 100, the data decoded by the primary row decoding module 100 is input to the secondary row decoding module 200, and the data processed by the secondary row decoding module 200 is transmitted to the memory cell array, thereby completing the row address decoding. The decoded row address data is input to a row decoding module, and the result is transmitted to a row gating module after row decoding. For example, when the number of ways of the multiplexers in the memory is equal to 4, the number of the multiplexers may represent the number of data multiplexes, and a 1-line-2-line decoder may be used as the upper decoder and a 1-line-2-line decoder may be used as the lower decoder in the column decoding block; when the data multiplexing number in the memory is equal to 8, the column decoding module can use a 2-line-4-line decoder as a high-order decoder and a 1-line-2-line decoder as a low-order decoder; when the number of data multiplexes in the memory is equal to 16, the column decoding block may use a 3-line-8-line decoder as the upper decoder and a 1-line-2-line decoder as the lower decoder.
In some embodiments, the logic gate cascade device may include at least three of the secondary inputs, each of the secondary inputs being used for connecting to a corresponding primary output of a different binary decoder, and step S300 may include:
and electrically connecting the first splicing connecting line and the second splicing connecting line through punching so as to connect at least any two primary output ends to the same logic gate cascade device. One logic gate cascade device can operate the pre-decoding results output by two or more different first-stage output ends, so that more decoding results can be obtained through the logic gate cascade device operation of the second-stage row decoding module 200, and the address decoding can be more detailed to find a target address and perform data read-write operation corresponding to the target address (a row where a target storage unit in the memory is located). Illustratively, the first-level row decoding module 100 includes a 3-line-8-line decoder and a 2-line-4-line decoder, the logic gate cascade device is connected to any two different first-level output terminals, for example, a logic gate cascade device is connected to one first-level output terminal of the 3-line-8-line decoder and one first-level output terminal of the 2-line-4-line decoder, the decoding results of the two first-level output terminals are operated to obtain one result, the number of the logic gate cascade devices may be 8 × 4, and the second-level row decoding module 200 may output 32 results.
According to the design method of the row decoding circuit provided by the embodiment of the application, the designed row decoding circuit is connected to the same logic gate cascade device through setting at least any two primary output ends, and more decoding results can be obtained through further operation on the output result of the primary row decoding module 100, so that the decoding digit is increased, and the decoding capacity is increased.
In some embodiments, the first-level row decoding module includes a low-level decoder, a middle-level decoder and a high-level decoder, and the logic gate level connection device includes three second-level input terminals respectively connected to any one of the first-level output terminals corresponding to the low-level decoder, the middle-level decoder and the high-level decoder. The logic gate cascade device can operate the data output by the three primary output ends and can perform more combined operations, so that more results are obtained, fewer decoders can be utilized, more decoding results can be obtained, the decoding capacity is improved, and excessive circuit area is not increased.
In some embodiments, two adjacent logic gate cascade devices are a decoder unit, and each decoder unit includes a first unit input terminal, a second unit input terminal, a third unit input terminal, and a fourth unit input terminal.
Step S300 may include:
and electrically connecting the first splicing connecting line and the second splicing connecting line through punching, so that the input end of the first unit is electrically connected with any one stage of output end corresponding to the low-order decoder, the input end of the second unit is electrically connected with any one stage of output end corresponding to the middle-order decoder, the input end of the third unit is electrically connected with any one stage of output end corresponding to the high-order decoder, the input end of the fourth unit is electrically connected with any one stage of output end corresponding to the low-order decoder, and the input end of the fourth unit and the input end of the first unit are electrically connected with different stage of output ends.
It is easy to understand that three secondary input ends of each logic gate cascade device are respectively connected with one primary output end of the low-order decoder, one primary output end of the middle-order decoder and one primary output end of the high-order decoder, and therefore decoding capacities corresponding to various storage capacities of the existing memory can be met.
For example, fig. 3 is a schematic structural block diagram of a logic gate cascade device provided in an embodiment of the present application. As shown in fig. 3, the logic gate cascade device includes three secondary inputs, which are a low-level secondary input G0, a middle-level secondary input G1 and a high-level secondary input G2, the low-level secondary input G0 may be correspondingly connected to any one of the primary outputs of the low-level decoders in the primary row decoding module 100, the middle-level secondary input G1 may be correspondingly connected to any one of the primary outputs of the middle-level decoders in the primary row decoding module 100, and the high-level secondary input G2 may be correspondingly connected to any one of the primary outputs of the high-level decoders in the primary row decoding module 100.
For example, the operation principle of the logic gate cascade device shown in fig. 3 may be: if at least one of the low level secondary input terminal G0, the middle level secondary input terminal G1 and the high level secondary input terminal G2 is low (specifically, 0), the output result of the logic gate cascade device is 0; the pre-decoding results of the first-level row decoding input by the low-order secondary input end G0, the middle-order secondary input end G1, and the high-order secondary input end G2 are all high level (specifically may be 1), and then the output result of the logic gate cascade device is input to the corresponding storage array for gating the storage unit of the corresponding row, and completing the row decoding, so that the target data can be read and written in the gated storage unit.
For example, fig. 4 is a schematic structural block diagram of a decoder unit provided in an embodiment of the present application. As shown in fig. 4, two adjacent logic gate cascade devices 210 can be used as one decoder unit 220, each decoder unit 220 includes a first unit input terminal, a second unit input terminal, a third unit input terminal and a fourth unit input terminal, the lower-order secondary input terminal G0 of one logic gate cascade device 210 in each decoder unit 220 is used as the first unit input terminal G01, the lower-order secondary input terminal G0 of another logic gate cascade device 210 is used as the fourth unit input terminal G02, the middle-order secondary input terminals G1 of two logic gate cascade devices 210 are connected in common potential and then used as the second unit input terminal, the upper-order secondary input terminals G2 of two logic gate cascade devices 210 are connected in common potential and then used as the third unit input terminal, that is, the middle secondary input ends G1 of the two logic gate cascade devices 210 are connected to the same primary output end, and the high secondary input ends G2 of the two logic gate cascade devices 210 are connected to the same primary output end. The first unit input end G01 is used for connecting any one stage of output end corresponding to the low-order decoder, the second unit input end is used for connecting any one stage of output end corresponding to the middle-order decoder, the third unit input end is used for connecting any one stage of output end corresponding to the high-order decoder, the fourth unit input end G02 is used for connecting any one stage of output end corresponding to the low-order decoder, and the fourth unit input end and the first unit input end are connected to different one stage of output ends. Each of the cascade devices 210 corresponds to a secondary output, and each of the decoder units includes two secondary outputs, namely a first secondary output GT1 and a second secondary output GT 2.
In some embodiments, step S100 may include:
in a circuit layout design environment, under the condition that the value of the decoding capacity is 32, a first-level decoder structure packet corresponding to a 3-line-8-line decoder and a 2-line-4-line decoder, a second-level decoder structure packet corresponding to 32 logic gate cascade devices and a splicing module corresponding to the number of lines are respectively called.
In some embodiments, the row decoding circuit with the decoding capacity of 32 corresponds to two first-level decoder structure packages, the two first-level decoder structure packages correspond to a circuit structure of a 3-line-8-line decoder and a circuit structure of a 2-line-4-line decoder respectively, the number of the second-level decoder structure packages is 32, and corresponding logic gates in the second-level decoder are connected with circuit structures of devices in a cascade mode.
Illustratively, the decoding capacity may be understood as the number of decoded output results, and the decoding capacity may be according to the number of word lines of the memory. For example, the ratio of the word (number of memory cells) to the data multiplexing ratio of the memory can be regarded as the number of word lines, and the number of word lines is the same as the decoding capacity. That is, WL is the number of word lines (i.e., decoding capacity), W is the number of memory cells in the memory, and M is the number of multiplexer paths in the memory, i.e., the number of data multiplexes.
Illustratively, when the decoding capacity is equal to 32, the number of binary decoders required by the first-level row decoding module is two, namely, a 3-line-8-line decoder and a 2-line-4-line decoder, and the number of decoders required by the second-level row decoding module is 32. Fig. 5 is a schematic diagram illustrating a splicing process of a row decoding circuit according to an embodiment of the present disclosure. As shown in fig. 5, the first-level row decoding module may include a low-level decoder and a middle-level decoder, the middle-level decoder may adopt a 2-line to 4-line decoder, the low-level decoder may adopt a 3-line to 8-line decoder, and a high-level decoder is not required. The 3-line-8-line decoder as a lower decoder has 3 first primary input terminals IN1, and has 8 primary output terminals, L1, L2, L3, L4, L5, L6, L7, and L8, respectively. The 2-line-4-line decoder, which is a median decoder, has 2 second-stage output terminals IN2, and has 4 first-stage output terminals, which are M1, M2, M3, and M4, respectively. Then M1, M2, M3 and M4 may have 4 × 8 combinations with L1, L2, L3, L4, L5, L6, L7 and L8, that is, 32 combined results, the secondary row decoding module may be provided with 32 logic gate cascade devices, that is, 16 decoder units, the first unit input terminal G01 and the fourth unit input terminal G02 of each decoder unit are respectively connected to any two of L1, L2, L3, L4, L5, L6, L7 and L8, and the middle secondary input terminal G1 is connected to any one of M1, M2, M3 and M4. The connection between the primary output end of the primary row decoding module and the secondary input end of the secondary row decoding module is realized by punching two (the punching connection positions shown in fig. 5 are indicated by black dots) of the first splicing connection line 310 and the second splicing connection line 320 in the splicing module 300. Since the row decoding circuit with the decoding capacity of 32 is not provided with a high-level decoder, the high-level secondary input terminal G2 of each decoder unit is connected to a high-level VDD, which may be a power supply voltage, and the embodiment of the present application is not particularly limited. Each logic gate cascade device in the secondary row decoding module corresponds to the address of one storage unit or the address of one row of storage units, one output result in the 32 output results is a global pulse control signal, and the corresponding logic gate cascade device in the secondary row decoding module which outputs the global pulse control signal can correspond to the position of one storage unit in the memory, can complete row address decoding, and stores data to be stored in one storage unit of the gated row. The output result of the secondary row decoding module is input to the corresponding storage array and used for gating the storage units of the corresponding row to complete row decoding, and then the target data can be stored in the storage units of the gated row. Illustratively, the global pulse control signal may be 0 or 1, and the embodiment of the present application is not particularly limited.
In some embodiments, step S100 may include:
in a circuit layout design environment, under the condition that the value of decoding capacity is between 33 and 64, a first-level decoder structure packet corresponding to two 3-line to 8-line decoders, a second-level decoder structure packet corresponding to logic gate cascade devices with the same number as the value of the decoding capacity and a splicing module with the corresponding line number are respectively called.
Illustratively, when WL is equal to or less than 33 and equal to or less than 64, both the lower decoder and the middle decoder are 3-line-8-line decoders, and when WL is equal to or less than 48, the first-level row decoding module consisting of two 3-line-8-line decoders can have 64 output results corresponding to the second-level row decoding module, but because the target word line number is only 48, and 16 output results do not have corresponding memory cell arrays and are useless, the number of decoders of the second-level row decoding module can be only 48, the middle decoder is continuously arranged after the lower decoders are arranged fully, and the useless 16 positions can be corresponding to the middle decoder.
In some embodiments, in a circuit layout design environment, under the condition that the value of the decoding capacity is between 65 and 128, a first-level decoder structure packet corresponding to two 3-line-8-line decoders and a 1-line-2-line decoder, a second-level decoder structure packet corresponding to logic gate level connection devices with the same number as the value of the decoding capacity, and a splicing module corresponding to the number of lines are respectively called.
The row decoding circuit with the decoding capacity of 65-128 comprises three binary decoders which are respectively two 3-line-8-line decoders and a 1-line-2-line decoder, and the number of logic gate cascade devices is equal to the value of the decoding capacity.
In some embodiments, in a circuit layout design environment, under the condition that the value of the decoding capacity is between 129-256, the first-level decoder structure packets corresponding to two 3-line-8-line decoders and one 2-line-4-line decoder, the second-level decoder structure packets corresponding to logic gate cascade devices with the same number of values of the decoding capacity, and the splicing modules with the corresponding line number are respectively invoked.
The row decoding circuit with the decoding capacity value between 129 and 256 comprises three binary decoders which are respectively a 3-line-8-line decoder and a 2-line-4-line decoder, and the number of the logic gate cascade devices is equal to the value of the decoding capacity.
In some embodiments, in a circuit layout design environment, under the condition that the value of the decoding capacity is between 257 and 512, a first-level decoder structure packet corresponding to three 3-8-line decoders, a second-level decoder structure packet corresponding to logic gate cascade devices with the same number as the value of the decoding capacity, and a splicing module corresponding to the number of lines are respectively invoked.
When 257 is equal to or less than WL equal to or less than 512, the low-order decoder, the middle-order decoder and the high-order decoder are all 3-8 line decoders.
According to the design method of the row decoding circuit, the number of word lines of a memory is calculated according to the number of storage units of the memory and the number of paths of a multiplexer; based on the fact that the number of word lines is the same as the decoding capacity, the number and the corresponding types of binary decoders needed in the primary row decoding module and the number of decoders needed in the secondary row decoding module are set respectively, when the decoding capacity is smaller than the maximum output combination number of the binary decoders in the primary row decoding module, the decoding capacity can be used as the number of decoders needed by the secondary row decoding module, the area of the secondary row decoding module and the number of decoders in the secondary row decoding module can be saved, and unnecessary waste of logic gate cascade devices is avoided. The number of the decoders is determined based on the number of the word lines, and automatic splicing and expansion of decoding circuit layouts corresponding to SRAMs with different capacities can be achieved according to the number of different storage units and the number of paths of the multi-path selector.
In a second aspect of the embodiments of the present application, a generating device of a decoding circuit is provided, and fig. 6 is a schematic structural block diagram of a design device of a row decoding circuit provided in the embodiments of the present application. As shown in figure 6 of the drawings,
the design device of the row decoding circuit comprises:
the calling module 500 is used for calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity in a circuit layout design environment, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
a connection module 600, configured to electrically connect a first-level output end of the binary decoder in the called first-level decoder structure package to a first splicing connection line of the splicing module, and electrically connect a second-level input end of the logic gate cascade device in the called second-level decoder structure package to a second splicing connection line of the splicing module;
and the punching module 700 is used for electrically connecting the first splicing connecting line with the second splicing connecting line through punching.
The design device of the row decoding circuit provided by the embodiment of the application adopts customized development aiming at the existing decoding circuit, is not suitable for multiplexing, and cannot be used in Memory Compiler. In a circuit layout design environment, a primary decoder structure packet required by a primary row decoding module, a secondary decoder structure packet required by a secondary row decoding module and a splicing module are respectively called according to decoding capacity. And electrically connecting the primary output end of the binary decoder in the called primary decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting the secondary input end of the logic gate cascading device in the called secondary decoder structure packet with a second splicing connecting line of the splicing module. And electrically connecting the first splicing connecting line with the second splicing connecting line through punching. After the number of binary decoders and the types of the corresponding binary decoders required by the primary row decoding module and the number of logic gate cascade devices required by the secondary row decoding module are determined, the decoder structure packages with the corresponding number and types can be directly called, and the generation efficiency of the decoding circuit can be improved. And the line decoding circuits with different decoding capacities can be generated according to the requirement of the target storage capacity, and the expansion of the line decoding circuit of the corresponding memory can be adapted. The position of punching can be determined according to the connection mode of the primary output end and the secondary input end, so that the splicing module can be applied to various connection schemes, and the splicing module can be used as a template to be called and applied to generate row decoding circuits with different circuit structures. The automatic generation of the row decoding circuit can be realized, the row decoding circuit can be automatically obtained by inputting the decoding capacity, and the design technology of the decoding circuit is simplified.
In a third aspect of the embodiments of the present application, an electronic device is provided, and fig. 7 is a schematic structural block diagram of the electronic device provided in the embodiments of the present application. As shown in fig. 7, the electronic apparatus includes:
a memory 800, the memory 800 having stored therein a computer program;
a processor 900, said processor 900 being adapted to implement the method of designing a row decoding circuit as described in the first aspect when said computer program is executed.
The design method of the row decoding circuit comprises the following steps:
in a circuit layout design environment, calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
electrically connecting a first-level output end of the binary decoder in the called first-level decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting a second-level input end of the logic gate cascading device in the called second-level decoder structure packet with a second splicing connecting line of the splicing module;
and forming electric connection between the first splicing connecting line and the second splicing connecting line through punching.
In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, and fig. 8 is a schematic structural block diagram of a computer-readable storage medium provided in the embodiments of the present application. As shown in fig. 8, the computer-readable storage medium 1000 has a computer program 1100 stored thereon, and the computer program 1100, when executed by a processor, implements the method for designing a line decoding circuit according to the first aspect.
The design method of the row decoding circuit comprises the following steps:
in a circuit layout design environment, calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
electrically connecting a first-level output end of the binary decoder in the called first-level decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting a second-level input end of the logic gate cascading device in the called second-level decoder structure packet with a second splicing connecting line of the splicing module;
and forming electric connection between the first splicing connecting line and the second splicing connecting line through punching.
In a fifth aspect of the embodiments of the present application, there is provided a row decoding circuit, which is generated by applying the design method of the decoding circuit according to the first aspect, and referring to fig. 2, the row decoding circuit includes: a first-level row decoding module 100, the first-level row decoding module 100 comprising at least one binary decoder; the secondary row decoding module 200, the secondary row decoding module 200 includes at least one logic gate cascade device, and the primary output end of the binary decoder is electrically connected to the secondary input end of the logic gate cascade device.
The existing decoding circuit is developed in a customized mode, and is not suitable for multiplexing, so that the existing decoding circuit cannot be used in Memory Compiler. In the row decoding circuit provided in the embodiment of the present application, by providing the primary row decoding module 100 and the secondary row decoding module 200, at least one binary decoder is provided in the primary row decoding module 100, and the binary decoder 110 can provide address pre-decoding. At least one logic gate cascade device is arranged in the secondary row decoding module 200, a primary output end of the binary decoder is electrically connected with a secondary input end of the logic gate cascade device, the logic gate cascade device can carry out combination operation on results output by the binary decoder to obtain more output results, the logic gate cascade device can carry out further address decoding, two-stage decoding can be realized, the cascade primary row decoding module 100 and the cascade secondary row decoding module 200 can increase decoding digits, increase decoding capacity and improve decoding speed, and under the condition of the same decoding capacity, the occupied area of a decoding circuit is smaller.
In the row decoding circuit provided by the embodiment of the application, the primary row decoding module 100 and the secondary row decoding module 200 are arranged, at least one binary decoder is arranged in the primary row decoding module 100, and the binary decoder can provide address pre-decoding. At least one logic gate cascade device is arranged in the secondary row decoding module 200, the logic gate cascade device can perform combined operation on the results output by the binary decoder to obtain more output results, the logic gate cascade device can perform further address decoding, two-stage decoding can be realized, the cascade primary row decoding module and the cascade secondary row decoding module can increase decoding digits, increase decoding capacity and improve decoding speed, and the occupied area of a decoding circuit is smaller under the condition of the same decoding capacity.
Fig. 9 is a schematic structural block diagram of a memory circuit provided in an embodiment of the present application. As shown in fig. 9, a memory circuit provided in an embodiment of the present application includes: the row decoding circuit of the fifth aspect; the memory cell array 2000 is electrically connected to the row decoding circuit, and specifically, the memory cell array 2000 is electrically connected to the secondary row decoding module 200.
According to the memory circuit provided by the embodiment of the application, the first-level row decoding module and the second-level row decoding module are arranged in the row decoding circuit, at least one binary decoder is arranged in the first-level row decoding module, and the binary decoder can perform address pre-decoding. At least one logic gate cascade device is arranged in the second-level row decoding module, the logic gate cascade device can carry out combined operation on the results output by the binary decoder to obtain more output results, the logic gate cascade device can carry out further address decoding, two-level decoding can be realized, the cascade first-level row decoding module and the cascade second-level row decoding module can increase decoding digits, increase decoding capacity and improve decoding speed, and the occupied area of a decoding circuit is smaller under the condition of the same decoding capacity.
It should be noted that, in the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to relevant descriptions of other embodiments for parts that are not described in detail in a certain embodiment.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-readable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Embodiments of the present application also provide a computer program product comprising computer software instructions that, when executed on a processing device, cause the processing device to execute a method flow of a line decoding circuit.
The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). A computer-readable storage medium may be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus, device and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
While preferred embodiments of the present specification have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all changes and modifications that fall within the scope of the specification.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present specification without departing from the spirit and scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalents, the specification is intended to include such modifications and variations.

Claims (10)

1. A method for designing a row decoding circuit, comprising:
in a circuit layout design environment, calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
electrically connecting a first-level output end of the binary decoder in the called first-level decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting a second-level input end of the logic gate cascading device in the called second-level decoder structure packet with a second splicing connecting line of the splicing module;
and forming electric connection between the first splicing connecting line and the second splicing connecting line through punching.
2. The method of claim 1, wherein said logic gate cascade device comprises at least three of said secondary inputs, each of said secondary inputs is for connecting to a corresponding one of said primary outputs of a different one of said binary decoders, and said electrically connecting said first and second splice connections is performed by punching, comprising:
and electrically connecting the first splicing connecting line and the second splicing connecting line through punching so as to enable at least any two primary output ends to be connected to the same logic gate cascade device.
3. The method of claim 2, wherein said first-level row decoding module comprises a low-level decoder, a middle-level decoder and a high-level decoder, said logic gate cascade device comprises three said second-level inputs, and said three second-level inputs are respectively connected to any one of said first-level outputs corresponding to said low-level decoder, said middle-level decoder and said high-level decoder.
4. The method of claim 3, wherein two adjacent said logic gate cascade devices are a decoder unit, each of said decoder units comprising a first unit input terminal, a second unit input terminal, a third unit input terminal and a fourth unit input terminal;
will first concatenation connecting wire with second concatenation connecting wire forms the electricity through punching and connects, include:
and electrically connecting the first splicing connecting line and the second splicing connecting line through punching, so that the input end of the first unit is electrically connected with any one stage output end corresponding to the low-order decoder, the input end of the second unit is electrically connected with any one stage output end corresponding to the medium-order decoder, the input end of the third unit is electrically connected with any one stage output end corresponding to the high-order decoder, the input end of the fourth unit is electrically connected with any one stage output end corresponding to the low-order decoder, and the input end of the fourth unit and the input end of the first unit are electrically connected with different stage output ends.
5. The method according to claim 1, wherein in the circuit layout design environment, the calling of the primary decoder structure packet required by the primary row decoding module, the secondary decoder structure packet required by the secondary row decoding module, and the splicing module according to the decoding capacity respectively comprises:
in the circuit layout design environment, under the condition that the value of the decoding capacity is 32, the first-level decoder structure packet corresponding to one 3-line-8-line decoder and one 2-line-4-line decoder, the second-level decoder structure packet corresponding to 32 logic gate cascade devices and the splicing module corresponding to the number of lines are respectively called.
6. The method according to claim 1, wherein in the circuit layout design environment, the calling of the primary decoder structure packet required by the primary row decoding module, the secondary decoder structure packet required by the secondary row decoding module, and the splicing module according to the decoding capacity respectively comprises:
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 33 and 64, the first-level decoder structure packages corresponding to two 3-line-8-line decoders, the second-level decoder structure packages corresponding to the logic gate cascade devices with the same number as the value of the decoding capacity and the splicing modules with the corresponding line number are respectively called; or the like, or, alternatively,
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 65 and 128, the first-level decoder structure packages corresponding to two 3-line-8-line decoders and one 1-line-2-line decoder, the second-level decoder structure packages corresponding to the logic gate level connection devices with the same number as the value of the decoding capacity and the splicing modules with the corresponding line number are respectively called; or the like, or, alternatively,
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 129-256, the first-level decoder structure packages corresponding to two 3-line-8-line decoders and one 2-line-4-line decoder, the second-level decoder structure packages corresponding to the logic gate cascade devices with the same number of values of the decoding capacity and the splicing modules with the corresponding line number are respectively called; or the like, or, alternatively,
in the circuit layout design environment, under the condition that the value of the decoding capacity is between 257 and 512, the first-level decoder structure packet corresponding to three 3-line-8-line decoders, the second-level decoder structure packets corresponding to the logic gate cascade devices with the same number as the value of the decoding capacity, and the splicing modules with the corresponding line number are respectively called.
7. An apparatus for generating a decoding circuit, comprising:
the calling module is used for calling a primary decoder structure package required by a primary row decoding module, a secondary decoder structure package required by a secondary row decoding module and a splicing module respectively according to decoding capacity in a circuit layout design environment, wherein the primary decoder structure package comprises circuit structures of various binary decoders, the secondary decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises a splicing connecting line;
the connection module is used for electrically connecting the primary output end of the binary decoder in the called primary decoder structure packet with a first splicing connecting line of the splicing module, and electrically connecting the secondary input end of the logic gate cascade device in the called secondary decoder structure packet with a second splicing connecting line of the splicing module;
and the punching module is used for electrically connecting the first splicing connecting line with the second splicing connecting line through punching.
8. An electronic device, comprising:
a memory having a computer program stored therein;
a processor for implementing a method of designing a row decoding circuit as claimed in any one of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements a method of designing a row decoding circuit according to any one of claims 1-6.
10. A row decoding circuit, characterized in that, applying the design method of the decoding circuit as claimed in any one of claims 1-6, the row decoding circuit comprises:
a primary row decoding module comprising at least one binary decoder;
and the secondary row decoding module comprises at least one logic gate cascade device, and the primary output end of the binary decoder is electrically connected with the secondary input end of the logic gate cascade device.
CN202210222590.7A 2022-03-07 2022-03-07 Design method of row decoding circuit and related equipment Pending CN114595658A (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN115102553A (en) * 2022-08-26 2022-09-23 深圳市汇顶科技股份有限公司 Device for converting binary code into thermometer code and electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115102553A (en) * 2022-08-26 2022-09-23 深圳市汇顶科技股份有限公司 Device for converting binary code into thermometer code and electronic equipment

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