CN219304823U - Full-dynamic Delta-Sigma modulator circuit - Google Patents
Full-dynamic Delta-Sigma modulator circuit Download PDFInfo
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- CN219304823U CN219304823U CN202320171194.6U CN202320171194U CN219304823U CN 219304823 U CN219304823 U CN 219304823U CN 202320171194 U CN202320171194 U CN 202320171194U CN 219304823 U CN219304823 U CN 219304823U
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Abstract
The utility model relates to the technical field of integrated circuit design, and particularly discloses a full-dynamic Delta-Sigma modulator circuit which comprises a dynamic integrator, a noise shaping analog-to-digital converter and a dynamic element matching calibration circuit, wherein the input end of the dynamic integrator is respectively connected with an analog input signal and a feedback signal, the input end of the noise shaping analog-to-digital converter is respectively connected with the analog input signal and the output end of the dynamic integrator, and the output end of the noise shaping analog-to-digital converter is connected with the input end of the dynamic element matching calibration circuit; the dynamic integrator is used for integrating the signal obtained by subtracting the analog input signal and the feedback signal and outputting the integrated signal; the noise shaping analog-to-digital converter is used for quantizing the signal obtained by adding the integrated signal and the analog input signal and outputting a quantized digital signal; the dynamic element matching calibration circuit is used for calibrating the quantized digital signal and outputting a feedback signal. The utility model can eliminate the static current of the modulator and realize high energy efficiency ratio.
Description
Technical Field
The utility model relates to the technical field of integrated circuit design, in particular to a full-dynamic Delta-Sigma modulator circuit.
Background
With the rapid development of the information age, various electronic devices are developed towards the direction of digitalization, and direct analog signal processing modes are gradually eliminated, instead of large-scale digital signal processing, but the real world is full of various sounds, light rays, temperature, pressure and the like which are analog signals, so that a high-performance analog-to-digital converter becomes a bridge connecting the digital world and the analog world. For example, in the audio field, high-precision Delta-Sigma analog-to-digital converters are widely used in various high-fidelity audio consumer electronic devices such as headphones, speakers, microphones, and the like. The power consumption requirements of wearable portable audio electronic equipment are also high, so that a low-power-consumption and high-precision Delta-Sigma analog-digital converter is generally adopted in the audio field.
In a Delta Sigma analog to digital converter, the analog part is a Delta Sigma modulator and the digital part is a downsampled digital filter, wherein the Delta Sigma modulator determines the performance of the whole converter. As process technology continues to evolve toward advanced processes, the intrinsic gain of the transistor continues to decrease, and the supply voltage continues to decrease, presenting a significant challenge to the design of high precision Delta Sigma modulators.
The current mainstream method for reducing power consumption is realized by adopting a continuous time architecture with feedforward, so that the problem that the resistor and the capacitor cannot provide an accurate time constant to cause instability of the modulator and are more susceptible to problems of clock jitter, excessive loop delay and the like is avoided. The reason why the discrete Delta Sigma modulator consumes much power is that it requires a large capacitance in the driver chip, thus requiring a large quiescent current of the op amp.
Another common low power consumption approach is to use an inverter-based integrator, whose supply voltage can be as low as 1V or less, achieving very low power consumption. The significant number of bits implemented by this architecture is typically limited to under 14 bits and the circuit is very sensitive to process, temperature and voltage variations.
Furthermore, if a multi-bit quantizer is used, which is typically implemented by a flash analog-to-digital converter, the number of comparators required for the flash analog-to-digital converter increases exponentially with the number of bits, e.g., a 5-bit flash analog-to-digital converter requires 31 comparators, which also consumes a significant amount of power consumption. And the scale of the dynamic element matching circuit increases exponentially when the quantizer accuracy is too high, so the number of quantizer bits is typically less than 6 bits.
Disclosure of Invention
In order to solve the defects in the prior art, the utility model provides a full-dynamic Delta-Sigma modulator circuit, the noise shaping capability of a first-order modulator is improved to a second order by using an active noise shaping quantizer, the quiescent current of the modulator is eliminated, and a very high energy efficiency ratio is realized.
As a first aspect of the present utility model, a fully dynamic Delta Sigma modulator circuit is provided, the fully dynamic Delta Sigma modulator circuit includes a dynamic integrator, a noise shaping analog-to-digital converter, and a dynamic element matching calibration circuit, an input end of the dynamic integrator is respectively connected to an analog input signal and an output end of the dynamic element matching calibration circuit, an input end of the noise shaping analog-to-digital converter is respectively connected to the analog input signal and an output end of the dynamic integrator, and an output end of the noise shaping analog-to-digital converter is connected to an input end of the dynamic element matching calibration circuit;
the dynamic integrator is used for integrating the signal obtained by subtracting the analog input signal from the feedback signal and outputting the integrated signal to the noise shaping analog-to-digital converter;
the noise shaping analog-to-digital converter is used for quantizing the signal obtained by adding the integrated signal and the analog input signal, and outputting a quantized digital signal to the dynamic element matching calibration circuit;
the dynamic element matching calibration circuit is used for calibrating the quantized digital signal and outputting the feedback signal.
Further, the dynamic integrator comprises a floating inverting dynamic amplifier and a sampling capacitor C S Integrating capacitor C I The floating inverting dynamic amplifier comprises two symmetrical inverters and an energy storage capacitor C r ；
In the sampling phase phi 1, one end of a sampling capacitor Cs is connected with an analog input voltage signal Vin/Vip, the analog input voltage signal Vin/Vip is sampled on the sampling capacitor Cs, the other end of the sampling capacitor Cs is connected with a common mode level Vcm, one end of an energy storage capacitor Cr is connected with a power supply voltage VDD, the other end of the energy storage capacitor Cr is connected with the ground, and the power supply is connected with the energy storage capacitor C r Charging is carried out, and the output ends of the two inverters are connected to a common mode level Vcm for resetting;
in the integration phase phi 2, one end of the sampling capacitor Cs is connected with the reference level Vref, and the other end of the sampling capacitor Cs is respectively connected with the input end of the first chopper switch and the integration capacitor C I Is forced to transfer to the integrating capacitor C I The power ends and the ground ends of the two inverters are respectively connected to the two ends of the energy storage capacitor Cr, the output ends of the two inverters are connected to the second chopper switch, the output ends of the two inverters are not clamped to the common mode level Vcm any more, and during the period, the floating inversion dynamic amplifier has amplifying capability, so that the integration behavior is realized;
at sampling phase phi 1 or integration phase phi 2, the integration capacitance C I Are connected across the input of the first chopping switch and the output of the second chopping switch.
Further, the noise shaping analog-to-digital converter comprises a switched capacitor array, a dynamic amplifier, a dynamic comparator and an asynchronous successive approximation logic circuit, wherein one end of the switched capacitor array is connected to a positive input end of the dynamic comparator, the other end of the switched capacitor array is connected to an analog input voltage signal Vin, a positive reference level Vrefp, a negative reference level Vrefn and a common mode level Vcm, a negative input end of the dynamic comparator is connected to an output end of the dynamic amplifier, an output end of the dynamic comparator is connected to a first end of the asynchronous successive approximation logic circuit, a second end of the asynchronous successive approximation logic circuit is connected to a switch of the positive reference level Vrefp, the negative reference level Vrefn and the common mode level Vcm, and a third end of the asynchronous successive approximation logic circuit is connected to a clock input end of the dynamic comparator;
at phase Φs, a capacitor C1 is connected between two grounds; at a phase Φn1, a capacitor C1 is connected between one end of the switched capacitor array and ground; at phase Φn2, a capacitor C1 is connected between the negative input of the dynamic amplifier and ground; the capacitor C2 is always connected between the negative input end and the output end of the dynamic amplifier in a bridging way to form closed-loop negative feedback.
Further, the asynchronous successive approximation logic circuit comprises a D flip-flop and a logic gate circuit.
Further, the dynamic element matching calibration circuit comprises two full adders, a group of registers, a thermometer code decoder and a logarithmic shifter, wherein a first input end of a first full adder is connected with a 5-bit digital input signal, a second input end of the first full adder is connected with an output end of the registers, an output end of the first full adder is connected with an input end of the registers through the second full adder, an output end of the registers is connected with a first input end of the logarithmic shifter, a second input end of the logarithmic shifter is connected with an output end of the thermometer code decoder, and an input end of the thermometer code decoder is connected with the 5-bit digital input signal.
Further, the shift number input end of the logarithmic shifter is connected with the output end of the register, the data input end of the logarithmic shifter is connected with the output end of the thermometer code decoder, and the logarithmic shifter outputs the shifted 31-bit data finally.
The full-dynamic Delta-Sigma modulator circuit provided by the utility model has the following advantages: in order to reduce the power consumption of a modulator circuit, the utility model adopts a closed-loop dynamic integrator based on a floating inverting dynamic amplifier to replace a traditional integrator based on an operational amplifier, and a quantizer part utilizes an active noise shaping successive approximation analog-to-digital converter to replace a traditional flash analog-to-digital converter, so that the energy efficiency ratio of the whole circuit is improved, and the whole noise shaping effect is improved to be second order. In addition, a dynamic element matching calibration circuit is utilized to eliminate nonlinear distortion introduced by capacitance mismatch of a feedback branch of the digital-to-analog converter; the first-stage integrator improves the linearity of sampling by using a bootstrap switch and suppresses DC offset and low-frequency flicker noise by using a chopper switch.
Drawings
The accompanying drawings are included to provide a further understanding of the utility model, and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the description serve to explain, without limitation, the utility model.
FIG. 1 is a block diagram of a full dynamic Delta-Sigma modulator circuit according to the present utility model.
Fig. 2 is a schematic circuit diagram of a conventional dynamic amplifier.
Fig. 3 is a schematic circuit diagram of a dynamic integrator based on a floating-phase inverting dynamic amplifier according to the present utility model.
Fig. 4 is a single-ended equivalent circuit diagram of the noise shaping analog-to-digital converter provided by the present utility model.
Fig. 5 is a schematic block diagram of a dynamic element matching calibration circuit provided by the present utility model.
Fig. 6 is a schematic diagram of an asynchronous successive approximation logic circuit provided by the present utility model.
Detailed Description
In order to further describe the technical means and effects adopted to achieve the preset purpose of the present utility model, the following detailed description refers to the specific implementation, structure, characteristics and effects of the fully dynamic Delta Sigma modulator circuit according to the present utility model with reference to the accompanying drawings and preferred embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the utility model herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the explanation of the present utility model, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise indicated. For example, the connection may be a fixed connection, or may be a connection through a special interface, or may be an indirect connection via an intermediary. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
In this embodiment, as shown in fig. 1, a fully-dynamic Delta-Sigma modulator circuit is provided, where the fully-dynamic Delta-Sigma modulator circuit includes a dynamic integrator, a noise shaping analog-to-digital converter, and a dynamic element matching calibration circuit, an input end of the dynamic integrator is connected to an analog input signal and an output end of the dynamic element matching calibration circuit, an input end of the noise shaping analog-to-digital converter is connected to the analog input signal and an output end of the dynamic integrator, and an output end of the noise shaping analog-to-digital converter is connected to an input end of the dynamic element matching calibration circuit;
the dynamic integrator is used for integrating the signal obtained by subtracting the analog input signal from the feedback signal and outputting the integrated signal to the noise shaping analog-to-digital converter;
the noise shaping analog-to-digital converter is used for quantizing the signal obtained by adding the integrated signal and the analog input signal, and outputting a quantized digital signal to the dynamic element matching calibration circuit;
the dynamic element matching calibration circuit is used for calibrating the quantized digital signal and outputting the feedback signal.
Specifically, the analog input signal is subtracted from the feedback signal, the subtracted signal is sent to a dynamic integrator for integration, the integrated signal and the analog input signal are added and then quantized through an active noise shaping successive approximation analog-digital converter, a 5-bit digital signal is output after quantization, and the 5-bit digital signal is calibrated by a dynamic element matching calibration circuit and then fed back to the input end.
In the embodiment of the utility model, the full-dynamic Delta-Sigma modulator circuit adopts a single-loop first-order modulator architecture with feedforward, wherein a closed-loop dynamic integrator is composed of a floating inverting amplifier, the integrator adopts a bootstrap switching technology and a chopping technology, and the quantizer adopts an active noise shaping successive approximation analog-to-digital converter, and is fed back to the input end of the integrator after passing through a dynamic element matching and calibrating circuit.
It should be noted that the dynamic integrator normally operates with zero input and the low frequency integrator provides a very high loop gain, so the analog input signal and the feedback signal are approximately equal at low frequencies. The noise transfer function exhibits a high-pass characteristic, so that the quantization noise is shaped to a higher frequency band after passing through the modulator. Since a dynamic amplifier is used, no additional quiescent current is required, and is therefore referred to as a dynamic integrator.
It should be noted that the active noise shaping successive approximation analog-to-digital converter not only can quantize the input signal like a nyquist analog-to-digital converter, but also has a first order noise shaping characteristic. The overall Delta Sigma modulator exhibits a second order noise shaping effect because the dynamic integrator provides a first order noise shaping capability.
It should be noted that there is a mismatch between the unit capacitances of the feedback branches of the digital-to-analog converter, which introduces nonlinear distortion that cannot be shaped to high frequencies like quantization noise, so that the mismatch needs to be calibrated. The dynamic element matching circuit is used for calibrating nonlinear distortion introduced by capacitance mismatch of the feedback branch of the digital-to-analog converter.
The full-dynamic Delta-Sigma modulator circuit provided by the utility model has the advantages that the integrator is composed of the floating inverting dynamic amplifier, the sampling switch adopts the bootstrap switch to improve the linearity of sampling, the chopper switch is introduced to eliminate the mismatch and the low-frequency flicker noise, the whole integrator works in a dynamic mode, and the power consumption is greatly reduced while the enough loop gain is provided; the quantizer is realized by a five-bit active noise shaping successive approximation analog-to-digital converter, improves the overall noise shaping effect to second order and further reduces the power consumption of the overall circuit.
Since operational amplifiers in conventional pipelined analog-to-digital converters and Delta-Sigma analog-to-digital converters consume a significant amount of power, dynamic amplifiers have been the focus of research during the last decade, one conventional dynamic amplifier being shown in fig. 2, in the reset phase phi rst The output node is precharged to the supply voltage; once the amplified phase phi is reached en The output discharges at different rates depending on the magnitude of the input voltage. The amplifier operates in a dynamic manner, achieving a high energy efficiency. However, it has many limitations in practical applications. First, its gain is very limited and once the output common mode voltage drops to ground, the amplification stops and the limited gain results in inaccurate closed loop behavior. Second, the tail current source contributes noise when in the amplified phase, mainly because the dynamic amplifier cannot provide a very high common mode rejection ratio. Again, the output voltage drops from the supply to ground, and this unstable output common mode voltage makes it difficult for the closed loop system to stabilize. Finally, the output common-mode voltage of the structure is sensitive to process, voltage and temperature, requiring additional calibration circuitry to stabilize the common-mode voltage.
The utility model adopts a closed-loop integrator based on a floating inverting dynamic amplifier, the schematic diagram of which is shown in figure 3, and the dynamic integrator comprises the floating inverting dynamic amplifier and a sampling capacitor C S Integrating capacitor C I A first chopper switch and a second chopper switchThe chopper switch comprises two symmetrical inverters and an energy storage capacitor C r Wherein phi is 1 And phi 2 Is a two-phase non-overlapping clock, phi 1e And phi 2e Respectively phi 1 And phi 2 Is used for realizing sampling capacitance sampling, phi c1 And phi c2 Is the clock of the chopper switch, which is set in advance to eliminate the influence of charge injection and clock feedthrough by means of backplane sampling, and is employed to eliminate offset and low frequency flicker noise of the amplifier.
In the sampling phase phi 1, one end of a sampling capacitor Cs is connected with an analog input voltage signal Vin/Vip, the analog input voltage signal Vin/Vip is sampled on the sampling capacitor Cs, the other end of the sampling capacitor Cs is connected with a common mode level Vcm, one end of an energy storage capacitor Cr is connected with a power supply voltage VDD, the other end of the energy storage capacitor Cr is connected with the ground, and the power supply is connected with the energy storage capacitor C r Charging is carried out, and the output ends of the two inverters are connected to a common mode level Vcm for resetting;
specifically, reset phase, φ 1 Switch is closed, sampling capacitor C S Sampling and storing capacitor C r The output of both inverters is reset to the common mode level Vcm for precharging.
In the integration phase phi 2, one end of the sampling capacitor Cs is connected with the reference level Vref, and the other end of the sampling capacitor Cs is respectively connected with the input end of the first chopper switch and the integration capacitor C I Due to conservation of charge, the charge on the sampling capacitor Cs is forced to transfer to the integrating capacitor C I The power ends and the ground ends of the two inverters are respectively connected to the two ends of the energy storage capacitor Cr, the output ends of the two inverters are connected to the second chopper switch, the output ends of the two inverters are not clamped to the common mode level Vcm any more, and during the period, the floating inversion dynamic amplifier has amplifying capability, so that the integration behavior is realized;
at sampling phase phi 1 or integration phase phi 2, the integration capacitance C I Are all connected across the input end of the first chopping switch and the output end of the second chopping switch。
Note that Φc1 and Φc2 are chopper phases. In the phi c1 phase, the two chopper switches act as wires; in the phase phi c2, the two chopper switches respectively invert their input signals.
Specifically, the integration phase, φ 2 Switch is closed, integrating capacitor C I The virtual place connected to the amplifier performs integration operation, and two power rails of the inverter are respectively connected to the energy storage capacitor C r At both ends of (i.e. by energy-storage capacitor C) r The two inverters are powered, so that the currents flowing into and out of the storage capacitors must be exactly equal, forcing the current flowing from the output point to the load capacitor to be zero, so that the common mode level Vcm of the output point is stable when the inverters are in an amplified state. This closed loop integration mode is similar to a conventional operational amplifier integrator with common mode feedback, and the integrated coefficient is represented by a capacitance ratio C S /C I It is decided that a high degree of accuracy can be achieved in CMOS processes. While the accuracy of the establishment of a closed-loop integrator depends on the bandwidth of the amplifier in addition to the open-loop gain of the amplifier. In the integration phase, the energy storage capacitor supplies power to the two inverters, the power supply voltage of the energy storage capacitor is reduced along with time, so that the bandwidth of the amplifier is reduced along with time, but as long as the speed requirement of the system is met in a half period, the closed loop integration behavior is stably established.
It should be noted that, the chopper switch is applied to a closed-loop integrator, modulates the detuning and flicker noise of the low frequency band to the high frequency band, and filters out the detuning and flicker noise by using a digital filter and quantization noise at the back end. The bootstrap switch is applied to the closed loop integrator, and suppresses nonlinear distortion introduced by the sampling switch.
The closed-loop integrator based on the floating inverting dynamic amplifier provided by the utility model adopts a closed-loop integrator structure insensitive to parasitics, and has various advantages compared with the structure of fig. 2. First, the PMOS and NMOS inputs of the floating anti-phase dynamic amplifier are used for multiplexing current, so that the current utilization rate is improved. Second, the structure also provides a constant output common mode voltage, which can be achieved without an additional common mode feedback circuit. Furthermore, the performance of the amplifier is insensitive to clock frequency, process, voltage and temperature variations due to the stable output common mode voltage.
The quantizer adopted by the utility model is an active noise shaping successive approximation analog-digital converter, a unilateral equivalent circuit diagram of which is shown as figure 4, and the noise shaping analog-digital converter comprises a switched capacitor array, a dynamic amplifier, a dynamic comparator and an asynchronous successive approximation logic circuit, wherein the middle phi is s Is the sampling phase, phi c Is to switch phase phi sum In time slots of sampling and conversion phases for feed-forward summation, phi n1 Is the residual sampling phase, phi n2 Is the residual integral phase.
One end of the switch capacitor array is connected to the positive input end of the dynamic comparator, the other end of the switch capacitor array is connected to an analog input voltage signal Vin, a positive reference level Vrefp, a negative reference level Vrefn and a common mode level Vcm, the negative input end of the dynamic comparator is connected to the output end of the dynamic amplifier, the output end of the dynamic comparator is connected to the first end of the asynchronous successive approximation logic circuit, the second end of the asynchronous successive approximation logic circuit is connected to the switches of the positive reference level Vrefp, the negative reference level Vrefn and the common mode level Vcm, and the third end of the asynchronous successive approximation logic circuit is connected to the clock input end of the dynamic comparator; wherein the control switches of Vin and Vout are phi s, and the switches of the rest levels are controlled by a successive approximation logic circuit.
In the sampling phase Φs, a capacitor C1 is connected between two grounds; at a phase Φn1, a capacitor C1 is connected between one end of the switched capacitor array and ground; at phase Φn2, a capacitor C1 is connected between the negative input of the dynamic amplifier and ground; the capacitor C2 is always connected between the negative input end and the output end of the dynamic amplifier in a bridging way to form closed-loop negative feedback.
During sampling phase phis, an integrator output signal Vout is connected to a top plate of the capacitor array for sampling, a modulator input Vin is connected to a bottom plate for sampling, a feedforward operation is embedded into two non-overlapping time slots, and during sampling phase phisum, the bottom plate of the capacitor array is fully connected to Vcm voltage, so that feedforward summation operation is automatically completed before conversion. And then performing successive approximation conversion, wherein after the conversion phase phi C is finished, the residual voltage of the top plate of the capacitor array is quantized residual voltage, the residual voltage is sampled to a capacitor C1 in the phi n1 phase, then the upper polar plate of the phi n2 phase C1 is connected to the input end of the dynamic amplifier, and the residual voltage is integrated to a capacitor C2. And finally, sending the signals into a dynamic comparator to finish summation and comparison.
In an embodiment of the utility model, a floating inverting dynamic amplifier is used as the dynamic amplifier. The introduction of feedforward reduces the swing of the integrator output and similarly reduces the swing of the quantizer input, i.e., reduces the nonlinear effect of the quantizer, making it more similar to a linear system, thus improving the stability of the overall modulator system. However, the introduction of feedforward is also more complicated, it is common practice to use an op-amp to perform feedforward summation, and the structure of fig. 4 samples the output voltage V of the integrator by using switched capacitor array top plate sampling before the start of conversion out Input V to feedforward branch by means of sampling on bottom plate in Sampling followed by phi before the arrival of the conversion phase sum Phase connects the bottom plates of all capacitors to common mode voltage V cm This automatically completes the summation prior to conversion. At this time, the residual voltage converted at this time is stored on the top plate of the capacitor array, and then the phase phi is sampled at the residual n1 Sampling the residual voltage, and integrating the phase phi in the residual n2 The residual voltage is integrated. In the transition phase phi c And (3) starting successive approximation conversion, automatically generating a comparison clock by a digital logic after each comparison of the dynamic comparator, and obtaining a final conversion result after 5 times of comparison. Because of the full dynamic operation of the quantizer, a high energy efficiency is maintained.
The active noise shaping successive approximation analog-to-digital converter provided by the utility model is used as a multi-bit quantizer, greatly improves the noise shaping capability of a first-order modulator, reduces the design difficulty of an amplifier in an integrator, performs input feedforward summation operation before conversion, omits an amplifier, and keeps lower power consumption.
As shown in fig. 6, the asynchronous successive approximation logic circuit mainly comprises standard unit circuits such as a D trigger, a delay unit, a basic logic gate and the like, and the clock of the comparator is automatically generated by the asynchronous successive approximation logic circuit, so that an external high-frequency synchronous clock is not required. The conversion process is represented by phi C The rising edge of the comparator is triggered by the rising edge of the exclusive or gate, the D flip-flop 3 latches the output result OP of the comparator, and a switching clock S is generated from the comparison result Vrefp,i 、S Vrefn,i For connecting the high-order capacitive backplane to Vrefp and Vrefn, respectively. D flip-flop 2 generates a switching clock S Vcm,i For connecting the remaining capacitor bottom plate to Vcm. The time of charge redistribution is controlled by a delay unit, and the delay time is T R . After all comparisons are completed, the result D is converted i Is output in parallel by the D flip-flop 4. Clock phi of comparator COMP Is automatically generated by the logic circuit after the last comparison, and does not need to be externally connected with a high-frequency synchronous clock.
Specifically, when sampling clock Φ S To a high level, convert clock phi C At low level, D flip-flop 1, D flip-flop 2, and D flip-flop 3 are reset, and control signal R 0 ～R 4 Becomes high level, clock Φ of dynamic comparator COMP At low level, i.e. the comparator is also in reset. When switching clock phi C At a high level, the clock Φ of the comparator COMP To a high level, i.e. the comparator is activated to compare the input signal, and then the exclusive-or gate output goes to a high level to cause the D flip-flop 1 to operate, the output Q of the D flip-flop 1 4 Changing from low level to high level, QB 4 Changing from high level to low level, QB 4 The falling edge of (1) causes the D flip-flop 3 to operate, the D flip-flop 3 latches the output result OP of the comparator, and the switching clocks S of the reference levels Vrefp and Vrefn will be generated from the comparison result Vrefp,4 、S Vrefn,4 For connecting the most significant capacitor, the bottom plate of the corresponding other capacitor being kept connected to Vcm voltage, D flip-flop 2 generating Vcm' S switching clock S Vcm,4 For connecting the remaining capacitors; at the same time as the time of this,control signal R 4 First of all, change from high to low and then delay T R After this time the comparator is reset and the first charge redistribution is completed and after the delay the comparator is activated again for a second comparison. And so on until the last comparison is completed, converting the result D i Is output in parallel by the D flip-flop 4.
Multi-bit quantization provides a series of benefits including reduced quantization noise, reduced quantizer nonlinearity, reduced amplifier design requirements, improved modulator loop stability, etc., but there are also issues to be addressed in that the mismatch of the capacitive elements of the digital-to-analog converter introduces nonlinearity that can severely degrade the signal-to-noise ratio of the output. The utility model adopts a dynamic element matching calibration circuit for data weighted average. The digital circuit is characterized in that the dynamic element matching calibration circuit comprises two full adders, a group of registers, a thermometer code decoder and a logarithmic shifter, wherein a first input end of the first full adder is connected with a 5-bit digital input signal, a second input end of the first full adder is connected with an output end of the registers, an output end of the first full adder is connected with the input end of the registers through the second full adder, an output end of the registers is connected with the first input end of the logarithmic shifter, a second input end of the logarithmic shifter is connected with the output end of the thermometer code decoder, and an input end of the thermometer code decoder is connected with the 5-bit digital input signal.
Specifically, the shift number input end of the logarithmic shifter is connected with the output end of the register, the data input end of the logarithmic shifter is connected with the output end of the thermometer code decoder, and the logarithmic shifter outputs the shifted 31-bit data finally.
In the embodiment of the utility model, the output data of the noise shaping analog-to-digital converter is converted into thermometer codes through a decoder to drive the switch of the digital-to-analog converter, and the sequence of the control switches is periodically circulated according to a polling algorithm, wherein an adder, a register and a logarithmic shifter are used for realizing the algorithm. The register latches the result of the previous summation and sends it as the number of shifts into the logarithmic shifter in the next cycle, cyclically shifting the thermometer code by a specified amount. After passing through the dynamic element matching calibration circuit, nonlinear distortion introduced by capacitance mismatch is effectively suppressed.
In the embodiment of the utility model, the closed-loop integrator formed by the floating inverting dynamic amplifier works in a dynamic mode, can provide noise shaping effect with excellent performance like the traditional closed-loop integrator based on the operational amplifier, has extremely low power consumption, and is insensitive to clock frequency, process, temperature and voltage because the output common mode of the floating inverting dynamic amplifier is stable.
A chopper switch is introduced into the first integrator, so that low-frequency flicker noise and direct current offset are moved to a higher frequency band outside the signal band, and can be eliminated by a digital filter at the rear end of the modulator together with quantization noise.
There is one input signal feedforward path before the quantizer and the feedforward summation operation is performed embedded in a successive approximation analog-to-digital converter. The introduction of the feed-forward path makes the input signal of the quantizer almost related to quantization noise, reduces the correlation between the input of the quantizer and the input signal of the modulator, and further improves the loop stability and reduces the design requirements of the dynamic amplifier in the second-stage integrator. The quantizer adopts an active noise shaping successive approximation analog-to-digital converter, the integral noise shaping effect is improved to a second order, the output swing of the output end of the integrator is reduced, the design requirement of an internal amplifier is reduced, and the performance requirement of a simple single-stage dynamic amplifier can be met by combining a feedforward path.
The dynamic element matching calibration circuit effectively suppresses nonlinear distortion introduced by the capacitance mismatch of the feedback branch of the digital-to-analog converter.
In summary, the full-dynamic Delta-Sigma modulator circuit provided by the utility model eliminates static current, meets high performance and simultaneously maintains low power consumption.
The present utility model is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the utility model.
Claims (6)
1. The full-dynamic Delta-Sigma modulator circuit is characterized by comprising a dynamic integrator, a noise shaping analog-to-digital converter and a dynamic element matching calibration circuit, wherein the input end of the dynamic integrator is respectively connected with an analog input signal and the output end of the dynamic element matching calibration circuit, the input end of the noise shaping analog-to-digital converter is respectively connected with the analog input signal and the output end of the dynamic integrator, and the output end of the noise shaping analog-to-digital converter is connected with the input end of the dynamic element matching calibration circuit;
the dynamic integrator is used for integrating the signal obtained by subtracting the analog input signal from the feedback signal and outputting the integrated signal to the noise shaping analog-to-digital converter;
the noise shaping analog-to-digital converter is used for quantizing the signal obtained by adding the integrated signal and the analog input signal, and outputting a quantized digital signal to the dynamic element matching calibration circuit;
the dynamic element matching calibration circuit is used for calibrating the quantized digital signal and outputting the feedback signal.
2. The full-dynamic Delta-Sigma modulator circuit of claim 1, wherein said dynamic integrator comprises a floating inverting dynamic amplifier, a sampling capacitor C S Integrating capacitor C I A first chopping switch and a second chopping switch, the followingThe floating inverting dynamic amplifier comprises two symmetrical inverters and an energy storage capacitor C r ；
In the sampling phase phi 1, one end of a sampling capacitor Cs is connected with an analog input voltage signal Vin/Vip, the analog input voltage signal Vin/Vip is sampled on the sampling capacitor Cs, the other end of the sampling capacitor Cs is connected with a common mode level Vcm, one end of an energy storage capacitor Cr is connected with a power supply voltage VDD, the other end of the energy storage capacitor Cr is connected with the ground, and the power supply is connected with the energy storage capacitor C r Charging is carried out, and the output ends of the two inverters are connected to a common mode level Vcm for resetting;
in the integration phase phi 2, one end of the sampling capacitor Cs is connected with the reference level Vref, and the other end of the sampling capacitor Cs is respectively connected with the input end of the first chopper switch and the integration capacitor C I Is forced to transfer to the integrating capacitor C I The power ends and the ground ends of the two inverters are respectively connected to the two ends of the energy storage capacitor Cr, the output ends of the two inverters are connected to the second chopper switch, the output ends of the two inverters are not clamped to the common mode level Vcm any more, and during the period, the floating inversion dynamic amplifier has amplifying capability, so that the integration behavior is realized;
at sampling phase phi 1 or integration phase phi 2, the integration capacitance C I Are connected across the input of the first chopping switch and the output of the second chopping switch.
3. The full-dynamic Delta-Sigma modulator circuit of claim 2, wherein said noise-shaping analog-to-digital converter comprises a switched capacitor array, a dynamic amplifier, a dynamic comparator and an asynchronous successive approximation logic circuit, one end of said switched capacitor array is connected to a positive input of said dynamic comparator, the other end of said switched capacitor array is connected to an analog input voltage signal Vin, a positive reference level Vrefp, a negative reference level Vrefn and a common mode level Vcm, a negative input of said dynamic comparator is connected to an output of said dynamic amplifier, an output of said dynamic comparator is connected to a first end of said asynchronous successive approximation logic circuit, a second end of said asynchronous successive approximation logic circuit is connected to a switch of said positive reference level Vrefp, negative reference level Vrefn and common mode level Vcm, and a third end of said successive approximation logic circuit is connected to a clock input of said dynamic comparator;
at phase Φs, a capacitor C1 is connected between two grounds; at a phase Φn1, a capacitor C1 is connected between one end of the switched capacitor array and ground; at phase Φn2, a capacitor C1 is connected between the negative input of the dynamic amplifier and ground; the capacitor C2 is always connected between the negative input end and the output end of the dynamic amplifier in a bridging way to form closed-loop negative feedback.
4. A fully dynamic Delta Sigma modulator circuit according to claim 3 wherein said asynchronous successive approximation logic circuit includes D flip-flops and logic gates.
5. A fully dynamic Delta Sigma modulator circuit according to claim 3 wherein said dynamic element matching calibration circuit includes two full adders, a set of registers, a thermometer code decoder and a logarithmic shifter, a first input of a first full adder terminating a 5 bit digital input signal, a second input of a first full adder terminating an output of said registers, an output of a first full adder being connected to an input of said registers through a second full adder, an output of said registers being connected to a first input of said logarithmic shifter, a second input of said logarithmic shifter being connected to an output of said thermometer code decoder, an input of said thermometer code decoder being connected to said 5 bit digital input signal.
6. The fully dynamic Delta Sigma modulator circuit of claim 5 wherein the number of shifts input of the logarithmic shifter is connected to the output of the register, the data input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the logarithmic shifter outputs the shifted 31-bit data.
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