CN114172494B - Clock signal delay circuit - Google Patents
Clock signal delay circuit Download PDFInfo
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- CN114172494B CN114172494B CN202210127556.1A CN202210127556A CN114172494B CN 114172494 B CN114172494 B CN 114172494B CN 202210127556 A CN202210127556 A CN 202210127556A CN 114172494 B CN114172494 B CN 114172494B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/00084—Fixed delay by trimming or adjusting the delay
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
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Abstract
The invention discloses a clock signal delay circuit, when the actual delay degree of the phase of a preset clock signal compared with the phase of an initial clock signal is less than the preset delay degree, the driving voltage output by a delay regulation and control module is gradually reduced, so that the delay action of a buffer is gradually enhanced, the actual delay degree is gradually close to the preset delay degree, and when the actual delay degree is the preset delay degree, the driving voltage output by the delay regulation and control module stops changing. At this time, the number relationship between the delay degree of the clock signal output by the output end of each buffer compared with the initial clock signal and the preset delay degree is determined. The invention can delay the initial clock signal to generate the delay clock signal without using other signals with the frequency higher than that of the delay clock signal, and is easy to realize.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a clock signal delay circuit.
Background
In the field of integrated circuits, it is sometimes necessary to delay the phase of an initial clock signal by a clock signal delay circuit to meet specific requirements, for example, it is often necessary to delay the phase of the initial clock signal by 90 degrees to generate a quadrature clock signal corresponding to the initial clock signal, and mixing the initial clock signal and the quadrature clock signal can suppress an image frequency generated during signal mixing to ensure the quality of the mixed signal. In the prior art, a group of differential signals with the frequency twice that of the quadrature clock signals are needed for generating the quadrature clock signals meeting the requirement, the frequency of the quadrature clock signals is usually higher, and if the differential signals with the frequency twice that of the quadrature clock signals are to be regenerated, the regeneration is difficult.
Disclosure of Invention
The invention aims to provide a clock signal delay circuit which can delay an initial clock signal to generate a delay clock signal without using other signals with the frequency higher than that of the delay clock signal and is easy to realize.
In order to solve the technical problem, the invention provides a clock signal delay circuit, which comprises a delay module and a delay regulation module, wherein the delay module comprises N buffers, and N is a positive integer;
the driving ends of the N buffers are connected with the output end of the delay regulation and control module, the input ends and the output ends of the N buffers are sequentially connected, one end of the connected circuit is used for inputting an initial clock signal, the other end of the connected circuit is used for outputting a preset clock signal, and the delay degree of the buffers to the input signal is in negative correlation with the driving voltage of the driving ends of the buffers;
the delay regulation and control module is used for outputting the driving voltage and gradually reducing the driving voltage when the phase of the preset clock signal is smaller than the actual delay degree of the phase of the initial clock signal than the actual delay degree, and controlling the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, wherein a first input end of the delay regulation and control module is used for inputting the initial clock signal, and a second input end of the delay regulation and control module is used for inputting the preset clock signal;
one or more output ends of the N buffers are used as the output end of the clock signal delay circuit to output delay clock signals.
Preferably, the delay regulation and control module is further configured to control the driving voltage to be the driving voltage corresponding to the minimum actual delay degree when the reset signal is at the first level, output the driving voltage and gradually decrease the driving voltage when the reset signal is changed from the first level to the second level opposite to the potential of the first level, and control the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, where a third input end of the delay regulation and control module is configured to input the reset signal.
Preferably, the delay regulation and control module comprises a first PMOS, a first controllable switch, a second controllable switch, an energy storage element, a charging current providing module and a regulation and control module;
the source electrode of the first PMOS and the first end of the energy storage element are both connected with a power supply, the grid electrode of the first PMOS is respectively connected with the first end of the first controllable switch, the first end of the second controllable switch and the second end of the energy storage element, and the drain electrode of the first PMOS is used as the output end of the delay regulation module;
the second end of the first controllable switch is connected with the output end of the charging current providing module, and the second end of the second controllable switch is grounded;
the regulation and control module is used for controlling the second controllable switch to be closed when the reset signal is at the first level and controlling the second controllable switch to be opened when the reset signal is at the second level;
the control module is also used for the reset signal does the second level just actual delay number of degrees is less than control when predetermineeing the delay number of degrees first controllable switch is closed actual delay number of degrees equals when predetermineeing the delay number of degrees control first controllable switch breaks off, the output current's of charging current provision module size with first controllable switch's on-time is positive correlation.
Preferably, the charging current providing module includes a second PMOS, a third PMOS, and a resistor;
the source electrode of the second PMOS and the source electrode of the third PMOS are both connected with the power supply, the grid electrode of the second PMOS is respectively connected with the drain electrode of the second PMOS and the grid electrode of the third PMOS, the drain electrode of the second PMOS is connected with the first end of the resistor, the second end of the resistor is grounded, and the drain electrode of the third PMOS is used as the output end of the charging current providing module.
Preferably, the preset delay degree is 180 degrees, the first level is a high level, the regulation and control module includes a first D flip-flop, a second D flip-flop, a third D flip-flop, an and gate, a first nor gate, a second nor gate, and a phase inverter, and the first D flip-flop, the second D flip-flop, and the third D flip-flop are triggered by rising edges;
the input end of the inverter is used for inputting the reset signal, the output end of the inverter is connected with the first end of the first NOR gate, and the first end of the second NOR gate is used for inputting the reset signal;
the input end of the first D flip-flop is used for inputting the initial clock signal, the in-phase output end of the first D flip-flop is connected with the input end of the second D flip-flop, the anti-phase output end of the first D flip-flop is connected with the first end of the and gate, both the trigger end of the first D flip-flop and the trigger end of the second D flip-flop are used for inputting the preset clock signal, and the in-phase output end of the second D flip-flop is connected with the second end of the and gate;
the trigger end of the third D trigger is connected with the output end of the AND gate, the input end of the third D trigger is connected with the power supply, the reset end of the third D trigger is used for inputting the reset signal, and the in-phase output end of the third D trigger is respectively connected with the second end of the first NOR gate and the second end of the second NOR gate;
the output end of the first NOR gate is connected with the control end of the second controllable switch, and the output end of the second NOR gate is connected with the control end of the first controllable switch;
the first controllable switch is switched on when the control end of the first controllable switch is at a high level and is switched off when the control end of the first controllable switch is at a low level;
the second controllable switch is turned on when the control terminal of the second controllable switch is at a high level, and is turned off when the control terminal of the second controllable switch is at a low level.
Preferably, the first controllable switch and the second controllable switch are both NMOS.
Preferably, the N buffers are of the same type.
Preferably, the energy storage element is a capacitor.
Preferably, the resistor is an adjustable resistor.
The invention provides a clock signal delay circuit, when the actual delay degree of the phase of a preset clock signal compared with the phase of an initial clock signal is smaller than the preset delay degree, the driving voltage output by a delay regulation and control module is gradually reduced, so that the delay action of a buffer is gradually enhanced, the actual delay degree is gradually close to the preset delay degree, and when the actual delay degree is the preset delay degree, the driving voltage output by the delay regulation and control module stops changing. At this time, the number relationship between the delay degree of the clock signal output by the output end of each buffer compared with the initial clock signal and the preset delay degree is determined. The invention can delay the initial clock signal to generate the delay clock signal without using other signals with the frequency higher than that of the delay clock signal, and is easy to realize.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a clock signal delay circuit according to the present invention;
FIG. 2 is a circuit diagram of a portion of a prior art quadrature clock signal circuit;
FIG. 3 is a circuit diagram of another portion of a prior art quadrature clock signal circuit;
FIG. 4 is a waveform diagram of related signals of a prior art quadrature clock signal circuit;
FIG. 5 is a waveform diagram of signals related to a regulation module of the clock signal delay circuit according to the present invention;
FIG. 6 is a detailed circuit diagram of a clock signal delay circuit according to the present invention.
Detailed Description
The core of the invention is to provide a clock signal delay circuit, which can delay an initial clock signal to generate a delay clock signal, does not need to use other signals with the frequency higher than that of the delay clock signal, and is easy to realize.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a clock signal delay circuit provided in the present invention, the circuit includes:
the delay module 1 comprises N buffers 11, and N is a positive integer;
the driving ends of the N buffers 11 are connected with the output end of the delay regulation and control module 2, the input ends and the output ends of the N buffers 11 are sequentially connected, one end of a connected circuit is used for inputting an initial clock signal, the other end of the connected circuit is used for outputting a preset clock signal, and the delay degree of the buffers 11 to the input signal is in negative correlation with the driving voltage of the driving ends of the buffers 11;
the delay control module 2 is configured to output a driving voltage and gradually reduce the driving voltage when an actual delay degree of a phase of a preset clock signal compared with a phase of an initial clock signal is less than the preset delay degree, control the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, input the initial clock signal at a first input end of the delay control module 2, and input the preset clock signal at a second input end of the delay control module 2;
one or more of the outputs of the N buffers 11 serve as the output of the clock signal delay circuit for outputting a delayed clock signal.
Clock signal delay circuits in the prior art typically require other signals having a higher frequency than the delayed clock signal when generating the delayed clock signal. For example, referring to fig. 2 and 3, fig. 2 is a circuit diagram of a part of a quadrature clock signal circuit of the prior art, fig. 3 is a circuit diagram of another part of a quadrature clock signal circuit of the prior art, and nodes with the same node names in fig. 2 and 3 are connected together, so that the purpose of generating a quadrature clock signal of an initial clock signal is realized by the circuit shown in fig. 2 and the circuit shown in fig. 3 in the prior art, but the circuit also needs to input a set of differential clock signals, fig. 4 is a waveform diagram of related signals of the quadrature clock signal circuit of the prior art, a curve (a) in fig. 4 is the initial clock signal, a curve (b) is the quadrature clock signal corresponding to the initial clock signal, and a curve (c) is the differential signal needed for generating the quadrature clock signal, and thus it can be seen. The frequency of the differential signal is twice the frequency of the initial clock signal and the frequency of the quadrature clock signal. In a radio frequency circuit, the frequency of an initial clock signal and the frequency of a quadrature clock signal are already high-frequency signals, and it is difficult to generate a frequency-doubled differential signal, which requires a larger circuit area and power consumption overhead.
In order to solve the technical problem, the invention provides a clock signal delay circuit, which comprises a delay module 1 and a delay regulation and control module 2, wherein the delay module 1 comprises N buffers 11, the buffers 11 have a delay function on an input signal, the delay time is in negative correlation with the driving voltage of the buffers 11, one end of the circuit, after the input end and the output end of the N buffers 11 are sequentially connected, inputs an initial clock signal, and the other end of the circuit outputs a preset clock signal. The delay regulation and control module 2 continuously adjusts the driving voltage based on the actual delay degree to adjust the delay action of the buffer 11, and when the actual delay degree is less than the preset delay degree, the delay regulation and control module 2 outputs the gradually decreased driving voltage, so that the delay action of the buffer 11 is gradually enhanced, the actual delay degree between the phase of the preset clock signal and the initial clock signal is gradually increased, until the actual delay degree is equal to the preset delay degree, the driving voltage output by the delay regulation and control module 2 stops changing, the delay degree of the buffer 11 also stops changing, and the phase of the preset clock signal is also stabilized.
Since the delay degree of each buffer 11 is determined, the ratio between the delay degrees of the respective buffers 11 is determined, and when the actual delay degree between the phase of the predetermined clock signal and the phase of the initial clock signal is determined as the predetermined delay degree, the phase difference between the phase of the output clock signal at the output terminal of the respective buffer 11 and the phase of the initial clock signal can be obtained. For example, the delay module 1 includes a first buffer 11 and a second buffer 11, and the two buffers 11 have the same model, and the preset delay degree is 180 degrees, so when the actual delay degree is 180 degrees, the clock signal output by the common terminal, where the output terminal of the first buffer 11 is connected to the input terminal of the second buffer 11, is the quadrature clock signal of the initial clock signal. Therefore, compared with the prior art, the invention does not need other signals with the frequency higher than the frequency of the initial clock signal or the frequency of the delayed clock signal, and is easy to realize.
In addition, the phase difference between the phase of the output clock signal at the output terminal of each buffer 11 and the phase of the initial clock signal is different, so that the present invention can simultaneously generate a plurality of delayed clock signals with different delay degrees.
The invention provides a clock signal delay circuit, when the actual delay degree of the phase of a preset clock signal compared with the phase of an initial clock signal is smaller than the preset delay degree, the driving voltage output by a delay regulation and control module 2 is gradually reduced, so that the delay action of a buffer 11 is gradually enhanced, the actual delay degree is gradually close to the preset delay degree, and when the actual delay degree is the preset delay degree, the driving voltage output by the delay regulation and control module 2 stops changing. At this time, the number relationship between the delay degree of the clock signal output from the output terminal of each buffer 11 compared to the initial clock signal and the preset delay degree is determined. The invention can delay the initial clock signal to generate the delay clock signal without using other signals with the frequency higher than that of the delay clock signal, and is easy to realize.
On the basis of the above-described embodiment:
as a preferred embodiment, the delay control module 2 is further configured to control the driving voltage to be a driving voltage corresponding to a minimum actual delay degree when the reset signal is at a first level, output the driving voltage and gradually decrease the driving voltage when the reset signal is changed from the first level to a second level opposite to a potential of the first level and the actual delay degree is less than the preset delay degree, control the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, and use a third input terminal of the delay control module 2 to input the reset signal.
In this embodiment, the delay adjusting and controlling module 2 may be further configured to restore the delay module 1 to an initial state, specifically, when the reset signal is the first level delay, the driving voltage output by the adjusting and controlling module 2 is the driving voltage corresponding to the minimum actual delay degree, so that the delay effect of the N buffers 11 is the weakest, and the phase difference between the phase of the preset clock signal and the phase of the initial clock signal is the minimum; when the reset signal changes to the second level and the actual delay degree is smaller than the preset delay degree, the driving voltage is controlled to gradually decrease so that the delay function of the N buffers 11 is gradually enhanced, and the phase difference between the phases of the preset clock signal and the initial clock signal is gradually increased; when the actual delay degree is equal to the preset delay degree, the driving voltage is controlled to stop changing so that the delay function of the N buffers 11 remains unchanged, and the phase difference between the phase of the preset clock signal and the phase of the initial clock signal is maintained at the preset delay degree.
In summary, the clock signal delay circuit can further ensure the working stability of the clock signal delay circuit, and can better generate the delay clock signal meeting the actual requirement.
As a preferred embodiment, the delay adjusting and controlling module 2 includes a first PMOS21, a first controllable switch 22, a second controllable switch 23, an energy storage element 24, a charging current providing module 25, and an adjusting and controlling module 26;
the source of the first PMOS21 and the first end of the energy storage element 24 are both connected to the power supply, the gate of the first PMOS21 is connected to the first end of the first controllable switch 22, the first end of the second controllable switch 23, and the second end of the energy storage element 24, respectively, and the drain of the first PMOS21 is used as the output end of the delay regulation module 26;
a second terminal of the first controllable switch 22 is connected to the output terminal of the charging current providing module 25, and a second terminal of the second controllable switch 23 is grounded;
the regulation and control module 26 is configured to control the second controllable switch 23 to be turned on when the reset signal is at a first level, and control the second controllable switch 23 to be turned off when the reset signal is at a second level;
the regulation and control module 26 is further configured to control the first controllable switch 22 to be turned on when the reset signal is the second level and the actual delay degree is less than the preset delay degree, and control the first controllable switch 22 to be turned off when the actual delay degree is equal to the preset delay degree, and the magnitude of the output current of the charging current providing module 25 is positively correlated with the on-time of the first controllable switch 22.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a clock signal delay circuit according to the present invention.
In this embodiment, the equivalent resistance between the drain and the source of the first PMOS21 can be represented as Rp, Rp =1/a (VDD-Vg1-Vt), where a is a constant of the first PMOS21 determined by the process dimension, VDD is the source voltage of the first PMOS21, Vg1 is the gate voltage of the first PMOS21, and Vt is the threshold voltage of the first PMOS 21.
When the reset signal is at the first level, the control module 26 controls the second controllable switch 23 to be turned on, the gate voltage of the first PMOS21 is pulled low, Rp is minimum, the voltage output by the drain of the first PMOS21 is the maximum driving voltage, at this time, the delay effect of the N buffers 11 is weakest, and the actual delay degree is minimum.
When the reset signal is at the second level and the actual delay degree is smaller than the preset delay degree, the control module 26 controls the first controllable switch 22 to be turned on, and the output current of the charging current providing module 25 may be represented as I, Vg = (I × t)/C, where Vg is the gate voltage of the first PMOS21, t is the on-time of the first controllable switch 22, and C is the energy storage amount of the energy storage element 24. Due to the effect of the charging current providing module 25, the gate voltage of the first PMOS21 gradually increases with the increase of the on-time of the first controllable switch 22, Rp gradually increases, the voltage output by the drain of the first PMOS21, that is, the driving voltage, gradually decreases, the delay effect of the N buffers 11 gradually increases, the actual delay degree gradually increases, until the actual delay reaches the preset delay degree, the control module 26 controls the first controllable switch 22 to be turned off, Vg does not change any more, and the delay effect of the N buffers 11 does not change any more.
In summary, in the present application, the first PMOS21, the first controllable switch 22, the second controllable switch 23, the energy storage element 24, the charging current providing module 25 and the regulation module 26 realize the function of the delay regulation module 2, and the structure is simple and easy to implement.
As a preferred embodiment, the charging current providing module 25 includes a second PMOS, a third PMOS, and a resistor;
the source of the second PMOS and the source of the third PMOS are both connected to the power supply, the gate of the second PMOS is connected to the drain of the second PMOS and the gate of the third PMOS, respectively, the drain of the second PMOS is connected to the first end of the resistor, the second end of the resistor is grounded, and the drain of the third PMOS serves as the output terminal of the charging current providing module 25.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a clock signal delay circuit according to the present invention.
In this embodiment, the second PMOS and the third PMOS form a common-gate-common-source current mirror, and the drain current of the second PMOS and the drain current of the third PMOS are both (VDD-Vsg2)/R1, where VDD is the source voltage of the second PMOS, Vsg2 is the voltage between the source and the gate of the second PMOS, and R1 is the resistance of the resistor.
As a preferred embodiment, the preset delay degree is 180 degrees, the first level is a high level, the regulation and control module 26 includes a first D flip-flop, a second D flip-flop, a third D flip-flop, an and gate, a first nor gate, a second nor gate, and an inverter, and the first D flip-flop, the second D flip-flop, and the third D flip-flop are triggered by rising edges;
the input end of the phase inverter is used for inputting a reset signal, the output end of the phase inverter is connected with the first end of the first NOR gate, and the first end of the second NOR gate is used for inputting the reset signal;
the input end of the first D trigger is used for inputting an initial clock signal, the in-phase output end of the first D trigger is connected with the input end of the second D trigger, the anti-phase output end of the first D trigger is connected with the first end of the AND gate, the trigger end of the first D trigger and the trigger end of the second D trigger are both used for inputting a preset clock signal, and the in-phase output end of the second D trigger is connected with the second end of the AND gate;
the trigger end of the third D trigger is connected with the output end of the AND gate, the input end of the third D trigger is connected with a power supply, the reset end of the third D trigger is used for inputting a reset signal, and the in-phase output end of the third D trigger is respectively connected with the second end of the first NOR gate and the second end of the second NOR gate;
the output end of the first nor gate is connected with the control end of the second controllable switch 23, and the output end of the second nor gate is connected with the control end of the first controllable switch 22;
the first controllable switch 22 is turned on when the control terminal of the first controllable switch 22 is at a high level, and is turned off when the control terminal of the first controllable switch 22 is at a low level;
the second controllable switch 23 is turned on when the control terminal of the second controllable switch 23 is at a high level, and turned off when the control terminal of the second controllable switch 23 is at a low level.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a clock signal delay circuit according to the present invention.
In this embodiment, the regulation module 26 includes a first D flip-flop, a second D flip-flop, a third D flip-flop, an and gate, a first nor gate, a second nor gate, and an inverter.
When the reset signal is at the first level, that is, the high level, the delay degree of the N buffers 11 is the weakest, the phase difference between the phases of the preset clock signal and the initial clock signal is much smaller than the half cycle of the initial clock signal, at this time, the in-phase output end of the first D flip-flop is set to the high level, the anti-phase output end of the first D flip-flop is set to the low level, the in-phase output end of the second D flip-flop is set to the high level, and the output of the and gate is the low level.
When the reset signal changes to the second level, that is, the low level, the delay degrees of the N buffers 11 gradually increase, at a certain time, the in-phase output terminal of the first D flip-flop outputs the low level, the inverted output terminal of the first D flip-flop outputs the high level, and the in-phase output terminal of the second D flip-flop is the high level, where the in-phase output terminal of the second D flip-flop represents a sampling result of the preset clock signal on the initial clock signal in a previous period of the preset clock signal, which means that a phase difference between phases of the preset clock signal and the initial clock signal is 180 degrees. Referring to fig. 5, fig. 5 is a waveform diagram of related signals of a regulation and control module of a clock signal delay circuit provided by the present invention, in which a square wave is a waveform diagram of an initial clock signal, and it can be seen that when an actual delay degree of a phase of a preset clock signal compared with a phase of the initial clock signal is changed to 180 degrees, an in-phase output end of a first D flip-flop outputs a low level, and an in-phase output end of a second D flip-flop outputs a high level.
At this time, the two input ends of the and gate are both at a high level, the and gate outputs the high level, the in-phase output end of the third D flip-flop outputs the high level, so that the first controllable switch 22 and the second controllable switch 23 are both turned off, the driving voltage is kept unchanged, and the delay degrees of the N buffers 11 are kept unchanged. The phase difference between the phase of the default clock signal and the phase of the initial clock signal is maintained at 180 degrees, and the degree of delay of each buffer 11 is determined, so that the ratio between the degrees of delay of each buffer 11 is determined, and when the actual degree of delay between the phase of the default clock signal and the phase of the initial clock signal is determined to be 180 degrees, the phase difference between the phase of the output clock signal at the output terminal of each buffer 11 and the phase of the initial clock signal can be obtained.
In this embodiment, the preset delay degree is 180 degrees, for example, the delay module 1 includes two buffers 11 with the same model, when the actual delay degree is equal to the preset delay degree, that is, equal to 180 degrees, the delay clock signal output by the output end of the first buffer 11 is the quadrature clock signal of the initial clock signal, and the initial clock signal is used for mixing with the corresponding delay clock signal, so that the image sideband generated during mixing can be suppressed, and the quality of the mixed signal is improved.
As a preferred embodiment, the first controllable switch 22 and the second controllable switch 23 are both NMOS.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a clock signal delay circuit according to the present invention.
In the embodiment, the NMOS is used as the first controllable switch 22 and the second controllable switch 23, which has the advantages of small input impedance and fast switching speed.
As a preferred embodiment, the N buffers 11 are of the same type.
In the present embodiment, the N buffers 11 have the same model, so that the delay functions of the N buffers 11 are the same when the driving voltages are the same, and when the actual delay degree reaches the preset delay degree, the phase difference between the phase of the output clock signal at the output terminal of the nth buffer 11 and the phase of the initial clock signal is N × (preset delay degree/N). The use of the same type of buffer 11 makes it easier to calculate the phase difference between the phase of the delayed clock signal and the phase of the initial clock signal.
As a preferred embodiment, the energy storage element 24 is a capacitor.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a clock signal delay circuit according to the present invention.
In this embodiment, the energy storage element 24 is a capacitor, and the output current of the charging current providing module 25 can be represented as I, Vg = (I × t)/C, where Vg is the gate voltage of the first PMOS21, t is the on-time of the first controllable switch 22, and C is the capacity of the capacitor. The circuit cost is lower, and the circuit structure is simple.
In a preferred embodiment, the resistor is an adjustable resistor.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a clock signal delay circuit according to the present invention.
In this embodiment, the resistor is an adjustable resistor, and since the delay adjusting module 2 may have a certain error in the process of controlling the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, some error may exist between the final delay clock signal and the ideal delay clock signal. During the charging process of the gate voltage of the first PMOS21, for each period T of the predetermined clock signal, the gate voltage Vg of the first PMOS21 increases by (I × T)/C, where I is the output current of the charging current providing module 25 and C is the stored energy of the energy storage element 24. Delay of input signal phase by buffer 11
It is shown that,
k is a constant, that is, in each period of the preset clock signal, the delay of the buffer 11 to the phase of the input signal is increased by (k × I × T)/C, so that the purpose of reducing the error can be achieved by increasing the energy storage of the energy storage element 24 or by increasing the resistance of the adjustable resistor to reduce I, and therefore the error of the clock signal delay circuit of the present application is easier to control and more accurate.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A clock signal delay circuit is characterized by comprising a delay module and a delay regulation module, wherein the delay module comprises N buffers, and N is a positive integer;
the driving ends of the N buffers are connected with the output end of the delay regulation and control module, the input ends and the output ends of the N buffers are sequentially connected, one end of the connected circuit is used for inputting an initial clock signal, the other end of the connected circuit is used for outputting a preset clock signal, and the delay degree of the buffers to the input signal is in negative correlation with the driving voltage of the driving ends of the buffers;
the delay regulation and control module is used for outputting the driving voltage and gradually reducing the driving voltage when the phase of the preset clock signal is smaller than the actual delay degree of the phase of the initial clock signal than the actual delay degree, and controlling the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, wherein a first input end of the delay regulation and control module is used for inputting the initial clock signal, and a second input end of the delay regulation and control module is used for inputting the preset clock signal;
one or more output ends of the N buffers are used as the output end of the clock signal delay circuit to output delay clock signals;
the delay regulation module is further configured to control the driving voltage to be a driving voltage corresponding to the minimum actual delay degree when a reset signal is a first level, output the driving voltage and gradually decrease the driving voltage when the reset signal is changed from the first level to a second level opposite to a potential of the first level and the actual delay degree is smaller than the preset delay degree, control the driving voltage to stop changing when the actual delay degree is equal to the preset delay degree, and input the reset signal at a third input end of the delay regulation module;
the time delay regulation and control module comprises a first PMOS, a first controllable switch, a second controllable switch, an energy storage element, a charging current providing module and a regulation and control module;
the source electrode of the first PMOS and the first end of the energy storage element are both connected with a power supply, the grid electrode of the first PMOS is respectively connected with the first end of the first controllable switch, the first end of the second controllable switch and the second end of the energy storage element, and the drain electrode of the first PMOS is used as the output end of the delay regulation module;
the second end of the first controllable switch is connected with the output end of the charging current providing module, and the second end of the second controllable switch is grounded;
the regulation and control module is used for controlling the second controllable switch to be closed when the reset signal is at the first level and controlling the second controllable switch to be opened when the reset signal is at the second level;
the control module is also used for the reset signal does the second level just actual delay number of degrees is less than control when predetermineeing the delay number of degrees first controllable switch is closed actual delay number of degrees equals when predetermineeing the delay number of degrees control first controllable switch breaks off, the output current's of charging current provision module size with first controllable switch's on-time is positive correlation.
2. The clock signal delay circuit of claim 1, wherein the charging current providing module comprises a second PMOS, a third PMOS, and a resistor;
the source electrode of the second PMOS and the source electrode of the third PMOS are both connected with the power supply, the grid electrode of the second PMOS is respectively connected with the drain electrode of the second PMOS and the grid electrode of the third PMOS, the drain electrode of the second PMOS is connected with the first end of the resistor, the second end of the resistor is grounded, and the drain electrode of the third PMOS is used as the output end of the charging current providing module.
3. The clock signal delay circuit of claim 2, wherein the predetermined delay degree is 180 degrees, the first level is a high level, the regulation and control module comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, an and gate, a first nor gate, a second nor gate, and an inverter, and the first D flip-flop, the second D flip-flop, and the third D flip-flop are triggered by a rising edge;
the input end of the inverter is used for inputting the reset signal, the output end of the inverter is connected with the first end of the first NOR gate, and the first end of the second NOR gate is used for inputting the reset signal;
the input end of the first D flip-flop is used for inputting the initial clock signal, the in-phase output end of the first D flip-flop is connected with the input end of the second D flip-flop, the anti-phase output end of the first D flip-flop is connected with the first end of the and gate, the trigger end of the first D flip-flop and the trigger end of the second D flip-flop are both used for inputting the preset clock signal, and the in-phase output end of the second D flip-flop is connected with the second end of the and gate;
the trigger end of the third D trigger is connected with the output end of the AND gate, the input end of the third D trigger is connected with the power supply, the reset end of the third D trigger is used for inputting the reset signal, and the in-phase output end of the third D trigger is respectively connected with the second end of the first NOR gate and the second end of the second NOR gate;
the output end of the first NOR gate is connected with the control end of the second controllable switch, and the output end of the second NOR gate is connected with the control end of the first controllable switch;
the first controllable switch is switched on when the control end of the first controllable switch is at a high level and is switched off when the control end of the first controllable switch is at a low level;
the second controllable switch is turned on when the control terminal of the second controllable switch is at a high level, and is turned off when the control terminal of the second controllable switch is at a low level.
4. The clock signal delay circuit of claim 3, wherein the first controllable switch and the second controllable switch are both NMOS.
5. The clock signal delay circuit of claim 1, wherein N of the buffers are the same type.
6. The clock signal delay circuit of claim 1, wherein the energy storage element is a capacitor.
7. The clock signal delay circuit of any one of claims 2 to 4, wherein the resistor is an adjustable resistor.
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| CN113346739A (en) * | 2021-05-28 | 2021-09-03 | 长江存储科技有限责任公司 | Charge pump circuit system, three-dimensional memory and three-dimensional memory system |
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| JP3657486B2 (en) * | 1999-12-13 | 2005-06-08 | 松下電器産業株式会社 | Switch element drive circuit |
| KR100370955B1 (en) * | 2000-07-20 | 2003-02-06 | 주식회사 하이닉스반도체 | Phase locked loop for improving jitter characteristics |
| US7425857B2 (en) * | 2004-02-10 | 2008-09-16 | Stmicroelectronics S.R.L. | Time-delay circuit |
| CN104113342B (en) * | 2013-11-28 | 2017-05-24 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN104124968B (en) * | 2014-08-06 | 2017-12-29 | 西安电子科技大学 | A kind of clock duty cycle calibration circuit for flow-line modulus converter |
| CN106849942B (en) * | 2016-12-29 | 2020-10-16 | 北京时代民芯科技有限公司 | Ultra-high-speed low-jitter multiphase clock circuit |
| CN113325744A (en) * | 2021-04-25 | 2021-08-31 | 北京时代民芯科技有限公司 | DDR3 storage protocol-oriented calibration controller |
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| CN106941345A (en) * | 2017-03-17 | 2017-07-11 | 中国电子科技集团公司第二十四研究所 | D type flip flop and asynchronous gradual approaching A/D converter |
| CN113346739A (en) * | 2021-05-28 | 2021-09-03 | 长江存储科技有限责任公司 | Charge pump circuit system, three-dimensional memory and three-dimensional memory system |
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