CN105049051A - Successive approximation type analog-to-digital conversion circuit and electronic device having same - Google Patents
Successive approximation type analog-to-digital conversion circuit and electronic device having same Download PDFInfo
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- CN105049051A CN105049051A CN201510450101.3A CN201510450101A CN105049051A CN 105049051 A CN105049051 A CN 105049051A CN 201510450101 A CN201510450101 A CN 201510450101A CN 105049051 A CN105049051 A CN 105049051A
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- electric capacity
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- successive approximation
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Abstract
The invention discloses a successive approximation type analog-to-digital conversion circuit and an electronic device having the same. The successive approximation type analog-to-digital conversion circuit comprises a digital-to-analog converter, a comparator, a successive approximation type register and a logic control circuit; the digital-to-analog converter is used for converting acquired digital signals to analog signals and sending the analog signals to the input end of the comparator; the comparator is used for comparing the received analog signals and outputting a binary value to the successive approximation type register; the successive approximation type register is used for storing the binary value output by the comparator, generating an internal control signal of the successive approximation type analog-to-digital conversion circuit and sending the control signal to the logic control circuit; the logic control circuit is used for adjusting drive capability of the control signal and sending the adjusted control signal to the digital-to-analog converter so as to realize a corresponding control function. By adoption of the structurally optimized digital-to-analog converter, the design of the whole circuit is simplified, and the power consumption is reduced.
Description
Technical field
The present invention relates to electric and electronic technical field, particularly the electronic equipment of a kind of successive approximation analog-to-digital conversion circuit and this circuit of tool.
Background technology
Along with the develop rapidly of digital technology, Digital AC turns direct current (AlternatingCurrenttoDirectCurrent is called for short AC/DC) power supply and is used widely.Relatively traditional analog power, the Switching Power Supply adopting digital algorithm to control has and controls flexibly, is convenient to the features such as integrated, efficiency is high, environmental protection.Analog to digital converter (AnalogtoDigitalConverter, be called for short ADC) as the interface circuit of analog signal and digital signal, directly can monitor the change of AC/DC power supply input signal, and analog quantity is converted to digital quantity, internal digital logic is provided to carry out related calculation and control treatment, the height of ADC performance, directly has influence on the performance of AC/DC power source integral performance.Hard constraints is there is in the ADC be applied in digital AC/DC power supply in area, power consumption and precision etc.Gradual approaching A/D converter (SuccessiveapproximationA/DConverter, be called for short SARADC) is the ADC of a kind of low sampling rate, medium above precision, has that size is little, low in energy consumption, advantages of simple structure and simple.Different from structure according to its internal system digital to analog converter (Digital-to-AnalogConverter is called for short DAC) signal processing mode, SARADC can be divided three classes, voltage-type, current mode, charge type.The SARADC of voltage-type structure has monotonicity and substitutional resistance, and area is large, and easily by the impact of parasitic capacitance, power consumption is large; Current mode SARADC speed is fast, does not affect by switch parasitic capacitance, and range of components is large, and power consumption is large, non-monotonic; Charge type SARADC speed is fast, and precision is high, low in energy consumption, and range of components is large, non-monotonic.
Therefore, design in successive approximation analog-to-digital conversion circuitry processes inventor, find that in prior art, at least there are the following problems:
In prior art, successive approximation analog-to-digital conversion circuit design structure is complicated, and power consumption is large.
Summary of the invention
In view of the above problems, proposing the present invention to provide a kind of overcomes the problems referred to above or solves the problem at least in part, and technical scheme of the present invention is achieved in that
On the one hand, the invention provides a kind of successive approximation analog-to-digital conversion circuit, comprising: digital-to-analogue converter, comparator, successive approximation register and logic control circuit;
Described digital-to-analogue converter is used for the digital signal collected to be converted into analog signal, and described analog signal is sent to described comparator input terminal;
Described comparator is used for the described analog signal received to compare, and exports a binary value to described successive approximation register;
The binary value that described successive approximation register exports for storing described comparator, and generate described successive approximation analog-to-digital conversion inside circuit control signal, and described control signal is sent to described logic control circuit;
Control signal after described adjustment for adjusting the driving force of described control signal, and is sent to described digital-to-analogue converter by described logic control circuit, to realize corresponding controlling functions.
Preferably, described digital-to-analogue converter adopts sectional capacitance structure.
Preferably, described digital-to-analogue converter comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn, the 6th electric capacity C
mSBn, the 7th electric capacity C
a1, the 8th electric capacity C
a2, the first switch S
1, second switch S
0, the 3rd switch S, the 4th switch S
1P ~ 5P, the 5th switch S
6P ~ 10P, the 6th switch S
0P, the 7th switch S
1n ~ 5n, the 8th switch S
6n ~ 10n, the 9th switch S
0n;
6th switch S described in described first electric capacity C1 mono-termination
0Pone end, comparator negative input, described 3rd electric capacity C described in described first another termination of electric capacity C1
mSBp, described 7th electric capacity C
a1, second switch S
0with the link of the 3rd switch S;
Described 6th switch S
0Panother termination voltage V
iNPside, described 6th switch S
0P3rd termination voltage V
cMside;
Described 3rd electric capacity C
mSBp5th switch S described in another termination
6P ~ 10Pone end; Described 5th switch S
6P ~ 10Panother termination voltage V
refp, described 5th switch S
6P ~ 10P3rd termination voltage V
cMside;
Described 4th electric capacity C
lSBp4th switch S described in one termination
1P ~ 5Pone end; Described 4th electric capacity C
lSBp7th electric capacity C described in another termination
a1one end;
Described 4th switch S
1P ~ 5Panother termination voltage V
refp, described 4th switch S
1P ~ 5P3rd termination voltage V
cMside;
Described second switch S
04th switch S described in another termination
1P ~ 5Pwith described 4th electric capacity C
lSBplink;
Comparator normal phase input end described in described 3rd another termination of switch S, described second electric capacity C2, described 6th electric capacity C
mSBn, described 8th electric capacity C
a2, described first switch S
1link;
9th switch S described in described second another termination of electric capacity C2
0none end; Described 9th switch S
0nanother termination voltage V
iNN, described 9th switch S
0n3rd termination voltage V
cMside;
Described 6th electric capacity C
mSBn8th switch S described in another termination
6n ~ 10none end; Described 8th switch S
6n ~ 10nother end voltage V
refn, described 8th switch S
6n ~ 10n3rd termination voltage V
cMside;
Described 8th electric capacity C
a25th electric capacity C described in another termination
lSBnone end; Described 5th electric capacity C
lSBn7th switch S described in another termination
1n ~ 5nwith described first switch S
1link;
Described 7th switch S
1n ~ 5nother end voltage V
refn, described 7th switch S
1n ~ 5n3rd termination voltage V
cMside.
Preferably, unit coupling capacitance is adopted to connect height section capacitor array.
Preferably, described comparator adopts and exports imbalance memory technology.
The invention provides a kind of electronic equipment, comprising: successive approximation analog-to-digital conversion circuit; This circuit comprises: digital-to-analogue converter, comparator, successive approximation register and logic control circuit;
Described digital-to-analogue converter is used for the digital signal collected to be converted into analog signal, and described analog signal is sent to described comparator input terminal;
Described comparator is used for the described analog signal received to compare, and exports a binary value to described successive approximation register;
The binary value that described successive approximation register exports for storing described comparator, and generate described successive approximation analog-to-digital conversion inside circuit control signal, and described control signal is sent to described logic control circuit;
Control signal after described adjustment for adjusting the driving force of described control signal, and is sent to described digital-to-analogue converter by described logic control circuit, to realize corresponding controlling functions.
Preferably, described digital-to-analogue converter adopts sectional capacitance structure.
Preferably, described digital-to-analogue converter comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn, the 6th electric capacity C
mSBn, the 7th electric capacity C
a1, the 8th electric capacity C
a2, the first switch S
1, second switch S
0, the 3rd switch S, the 4th switch S
1P ~ 5P, the 5th switch S
6P ~ 10P, the 6th switch S
0P, the 7th switch S
1n ~ 5n, the 8th switch S
6n ~ 10n, the 9th switch S
0n;
6th switch S described in described first electric capacity C1 mono-termination
0Pone end, comparator negative input, described 3rd electric capacity C described in described first another termination of electric capacity C1
mSBp, described 7th electric capacity C
a1, second switch S
0with the link of the 3rd switch S;
Described 6th switch S
0Panother termination voltage V
iNPside, described 6th switch S
0P3rd termination voltage V
cMside;
Described 3rd electric capacity C
mSBp5th switch S described in another termination
6P ~ 10Pone end; Described 5th switch S
6P ~ 10Panother termination voltage V
refp, described 5th switch S
6P ~ 10P3rd termination voltage V
cMside;
Described 4th electric capacity C
lSBp4th switch S described in one termination
1P ~ 5Pone end; Described 4th electric capacity C
lSBp7th electric capacity C described in another termination
a1one end;
Described 4th switch S
1P ~ 5Panother termination voltage V
refp, described 4th switch S
1P ~ 5P3rd termination voltage V
cMside;
Described second switch S
04th switch S described in another termination
1P ~ 5Pwith described 4th electric capacity C
lSBplink;
Comparator normal phase input end described in described 3rd another termination of switch S, described second electric capacity C2, described 6th electric capacity C
mSBn, described 8th electric capacity C
a2, described first switch S
1link;
9th switch S described in described second another termination of electric capacity C2
0none end; Described 9th switch S
0nanother termination voltage V
iNN, described 9th switch S
0n3rd termination voltage V
cMside;
Described 6th electric capacity C
mSBn8th switch S described in another termination
6n ~ 10none end; Described 8th switch S
6n ~ 10nother end voltage V
refn, described 8th switch S
6n ~ 10n3rd termination voltage V
cMside;
Described 8th electric capacity C
a25th electric capacity C described in another termination
lSBnone end; Described 5th electric capacity C
lSBn7th switch S described in another termination
1n ~ 5nwith described first switch S
1link;
Described 7th switch S
1n ~ 5nother end voltage V
refn, described 7th switch S
1n ~ 5n3rd termination voltage V
cMside.
Preferably, unit coupling capacitance is adopted to connect height section capacitor array.
Preferably, described comparator adopts and exports imbalance memory technology.
Technical scheme of the present invention, by adopting sectional capacitance structure digital-to-analogue converter and optimizing successive approximation register and logic control circuit, makes circuit structure design simplify, lower power consumption; Adopt unit coupling capacitance to connect height section capacitor array, improve circuit and transform precision; Employing output imbalance memory technology reduces the random imbalance in the described comparator course of work.
Accompanying drawing explanation
A kind of successive approximation analog-to-digital conversion electrical block diagram that Fig. 1 provides for the embodiment of the present invention;
A kind of successive approximation analog-to-digital conversion circuit diagram that Fig. 2 provides for the embodiment of the present invention;
A kind of electronic devices structure schematic diagram that Fig. 3 provides for the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
As a kind of successive approximation analog-to-digital conversion electrical block diagram that Fig. 1 provides for being depicted as the embodiment of the present invention; This comprises: digital-to-analogue converter, comparator, successive approximation register and logic control circuit;
Described digital-to-analogue converter is used for the digital signal collected to be converted into analog signal, and described analog signal is sent to described comparator input terminal;
Described comparator is used for the described analog signal received to compare, and exports a binary value to described successive approximation register;
The binary value that described successive approximation register exports for storing described comparator, and generate described successive approximation analog-to-digital conversion inside circuit control signal, and described control signal is sent to described logic control circuit;
Control signal after described adjustment for adjusting the driving force of described control signal, and is sent to described digital-to-analogue converter by described logic control circuit, to realize corresponding controlling functions.
It should be noted that, described digital-to-analogue converter adopts sectional capacitance structure.
Also it should be noted that, described comparator adopts and exports imbalance memory technology.
Based on above embodiment, as shown in Figure 2, if the successive approximation analog-to-digital conversion circuit diagram of a kind of 10 that provides of the embodiment of the present invention; This circuit comprises: digital-to-analogue converter, comparator, successive approximation register and logic control circuit; Wherein, described digital-to-analogue converter comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn, the 6th electric capacity C
mSBn, the 7th electric capacity C
a1, the 8th electric capacity C
a2, the first switch S
1, second switch S
0, the 3rd switch S, the 4th switch S
1P ~ 5P, the 5th switch S
6P ~ 10P, the 6th switch S
0P, the 7th switch S
1n ~ 5n, the 8th switch S
6n ~ 10n, the 9th switch S
0n;
6th switch S described in described first electric capacity C1 mono-termination
0Pone end, comparator negative input, described 3rd electric capacity C described in described first another termination of electric capacity C1
mSBp, described 7th electric capacity C
a1, second switch S
0with the link of the 3rd switch S;
Described 6th switch S
0Panother termination voltage V
iNPside, described 6th switch S
0P3rd termination voltage V
cMside;
Described 3rd electric capacity C
mSBp5th switch S described in another termination
6P ~ 10Pone end; Described 5th switch S
6P ~ 10Panother termination voltage V
refp, described 5th switch S
6P ~ 10P3rd termination voltage V
cMside;
Described 4th electric capacity C
lSBp4th switch S described in one termination
1P ~ 5Pone end; Described 4th electric capacity C
lSBp7th electric capacity C described in another termination
a1one end;
Described 4th switch S
1P ~ 5Panother termination voltage V
refp, described 4th switch S
1P ~ 5P3rd termination voltage V
cMside;
Described second switch S
04th switch S described in another termination
1P ~ 5Pwith described 4th electric capacity C
lSBplink;
Comparator normal phase input end described in described 3rd another termination of switch S, described second electric capacity C2, described 6th electric capacity C
mSBn, described 8th electric capacity C
a2, described first switch S
1link;
9th switch S described in described second another termination of electric capacity C2
0none end; Described 9th switch S
0nanother termination voltage V
iNN, described 9th switch S
0n3rd termination voltage V
cMside;
Described 6th electric capacity C
mSBn8th switch S described in another termination
6n ~ 10none end; Described 8th switch S
6n ~ 10nother end voltage V
refn, described 8th switch S
6n ~ 10n3rd termination voltage V
cMside;
Described 8th electric capacity C
a25th electric capacity C described in another termination
lSBnone end; Described 5th electric capacity C
lSBn7th switch S described in another termination
1n ~ 5nwith described first switch S
1link;
Described 7th switch S
1n ~ 5nother end voltage V
refn, described 7th switch S
1n ~ 5n3rd termination voltage V
cMside.
It should be noted that, adopt unit coupling capacitance to connect height section capacitor array.
Based on above circuit, operation principle of the present invention is described in detail;
As shown in Figure 2, a kind of successive approximation analog-to-digital conversion circuit that the present invention proposes is fully differential input charge code reassignment successive approximation analog-to-digital conversion circuit structure.Its structural advantages, except low in energy consumption, eliminate sample/hold circuit independent in existing charge redistribution structure, circuit design is significantly simplified.Realize transfer process by capacitor charge and discharge form in digital-to-analogue converter, because electric capacity phase ratio resistance has better matching degree and temperature stability, be conducive to realizing higher conversion accuracy.For the successive approximation analog-to-digital conversion circuit of 10, be described in detail to its course of work, concrete steps are as follows:
(1) initialization
Described initialization procedure comprises: capacitor discharge process, comparator disappearance tune process and sampling/keep-process.
After system starts, first Closing Switch S
0can realize the short circuit up and down of capacitor array, electric capacity fully discharges; After electric discharge terminates, the state of each switch is constant, and the voltage at comparator two ends is all voltage Vcm, the common mode electrical level of the tune that disappears as comparator; Next, enter the sampling maintenance stage, during sampling, switch S, S
0, S
1closed, the high-order electric capacity of capacitor array and C1, C2 participate in sampling, i.e. C
mSBp, C1 and C
mSBn, C2 bottom crown meet V respectively
inpand V
inn, bit capacitor is not sampled, i.e. C
lSBpand C
lSBnbottom crown connect C respectively
mSBpand C
mSBntop crown.After sampling terminates, enter the maintenance stage, first switch S disconnects, Simultaneous Switching S
0and S
1also disconnect, the bottom crown of all electric capacity of upper and lower capacitor array all meets common mode electrical level V
cm.
2), after sampling/keep-process completes, the work of ADC enters second process, i.e. transfer process.
Approach by inchmeal carries out in this process, and consumes 10 clock cycle.Period, the domination number character code of Approach by inchmeal is kept in successive approximation register, and logic control circuit controls the reallocation of electric charge in capacitor array in digital-to-analogue converter according to these digital codes.A clock cycle determines one digit number character code, by the memory cell Serial output of successive approximation register.
3), last process, i.e. standby.
After ADC completes a data transaction, enter holding state, save power consumption.
Supposing the system clock is 2MHz, and sampling rate is 100Ks/s.A sampling period is 10 μ, and corresponding 20 clock cycle, whole transfer process consumes 15 cycles; Wherein, in 1 cycle of capacitor discharge process need, sampling keep-process needs 2 cycles, and transfer process needs 10 cycles, and standby needs 1 cycle, remains 5 clock cycle.After data transaction is complete, can designs and successive approximation register is controlled to send a control signal to logic control circuit, enter holding state by logic control circuit control ADC, close comparator simultaneously, save power consumption.
It should be noted that, adopt unit coupling capacitance to connect height section capacitor array, namely described unit coupling capacitance comprises: the 7th electric capacity C
a1, the 8th electric capacity C
a2; Described high section capacitor array comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 6th electric capacity C
mSBn; Described low section of capacitor array comprises: the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn; I.e. the 4th electric capacity C of described low section of capacitor array
lSBpby described 7th electric capacity C
a1with the first electric capacity C1, the 3rd electric capacity C of described high section capacitor array
mSBpconnect; 5th electric capacity C of described low section of capacitor array
lSBnby described 8th electric capacity C
a2with the second electric capacity C2 of described high section capacitor array, the 6th electric capacity C
mSBnconnect.
As shown in Figure 3, be a kind of electronic devices structure schematic diagram that the embodiment of the present invention provides; This electronic equipment comprises: successive approximation analog-to-digital conversion circuit; This circuit comprises: digital-to-analogue converter, comparator, successive approximation register and logic control circuit;
Described digital-to-analogue converter is used for the digital signal collected to be converted into analog signal, and described analog signal is sent to described comparator input terminal;
Described comparator is used for the described analog signal received to compare, and exports a binary value to described successive approximation register;
The binary value that described successive approximation register exports for storing described comparator, and generate described successive approximation analog-to-digital conversion inside circuit control signal, and described control signal is sent to described logic control circuit;
Control signal after described adjustment for adjusting the driving force of described control signal, and is sent to described digital-to-analogue converter by described logic control circuit, to realize corresponding controlling functions.
It should be noted that, described digital-to-analogue converter adopts sectional capacitance structure.
Also it should be noted that, described digital-to-analogue converter comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn, the 6th electric capacity C
mSBn, the 7th electric capacity C
a1, the 8th electric capacity C
a2, the first switch S
1, second switch S
0, the 3rd switch S, the 4th switch S
1P ~ 5P, the 5th switch S
6P ~ 10P, the 6th switch S
0P, the 7th switch S
1n ~ 5n, the 8th switch S
6n ~ 10n, the 9th switch S
0n;
6th switch S described in described first electric capacity C1 mono-termination
0Pone end, comparator negative input, described 3rd electric capacity C described in described first another termination of electric capacity C1
mSBp, described 7th electric capacity C
a1, second switch S
0with the link of the 3rd switch S;
Described 6th switch S
0Panother termination voltage V
iNPside, described 6th switch S
0P3rd termination voltage V
cMside;
Described 3rd electric capacity C
mSBp5th switch S described in another termination
6P ~ 10Pone end; Described 5th switch S
6P ~ 10Panother termination voltage V
refp, described 5th switch S
6P ~ 10P3rd termination voltage V
cMside;
Described 4th electric capacity C
lSBp4th switch S described in one termination
1P ~ 5Pone end; Described 4th electric capacity C
lSBp7th electric capacity C described in another termination
a1one end;
Described 4th switch S
1P ~ 5Panother termination voltage V
refp, described 4th switch S
1P ~ 5P3rd termination voltage V
cMside;
Described second switch S
04th switch S described in another termination
1P ~ 5Pwith described 4th electric capacity C
lSBplink;
Comparator normal phase input end described in described 3rd another termination of switch S, described second electric capacity C2, described 6th electric capacity C
mSBn, described 8th electric capacity C
a2, described first switch S
1link;
9th switch S described in described second another termination of electric capacity C2
0none end; Described 9th switch S
0nanother termination voltage V
iNN, described 9th switch S
0n3rd termination voltage V
cMside;
Described 6th electric capacity C
mSBn8th switch S described in another termination
6n ~ 10none end; Described 8th switch S
6n ~ 10nother end voltage V
refn, described 8th switch S
6n ~ 10n3rd termination voltage V
cMside;
Described 8th electric capacity C
a25th electric capacity C described in another termination
lSBnone end; Described 5th electric capacity C
lSBn7th switch S described in another termination
1n ~ 5nwith described first switch S
1link;
Described 7th switch S
1n ~ 5nother end voltage V
refn, described 7th switch S
1n ~ 5n3rd termination voltage V
cMside.
Also it should be noted that, adopt unit coupling capacitance to connect height section capacitor array.
Also it should be noted that, described comparator adopts and exports imbalance memory technology.
Also it should be noted that, the 4th switch S described in the present invention
1P ~ 5P, described 5th switch S
6P ~ 10P, described 6th switch S
0P, described 7th switch S
1n ~ 5n, described 8th switch S
6n ~ 10n, described 9th switch S
0nbe single-pole double-throw switch (SPDT), according to integrated circuit state, closing direction selected by the movable end of single-pole double throw and cutter.
Technical scheme of the present invention, by adopting sectional capacitance structure digital-to-analogue converter and optimizing successive approximation register and logic control circuit, makes circuit structure design simplify, lower power consumption; Adopt unit coupling capacitance to connect height section capacitor array, improve circuit and transform precision; Employing output imbalance memory technology reduces the random imbalance in the described comparator course of work.
The foregoing is only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.All any amendments done within the spirit and principles in the present invention, equivalent replacement, improvement etc., be all included in protection scope of the present invention.
Claims (10)
1. a successive approximation analog-to-digital conversion circuit, is characterized in that, comprising: digital-to-analogue converter, comparator, successive approximation register and logic control circuit;
Described digital-to-analogue converter is used for the digital signal collected to be converted into analog signal, and described analog signal is sent to described comparator input terminal;
Described comparator is used for the described analog signal received to compare, and exports a binary value to described successive approximation register;
The binary value that described successive approximation register exports for storing described comparator, and generate described successive approximation analog-to-digital conversion inside circuit control signal, and described control signal is sent to described logic control circuit;
Control signal after described adjustment for adjusting the driving force of described control signal, and is sent to described digital-to-analogue converter by described logic control circuit, to realize corresponding controlling functions.
2. successive approximation analog-to-digital conversion circuit according to claim 1, is characterized in that, described digital-to-analogue converter adopts sectional capacitance structure.
3. successive approximation analog-to-digital conversion circuit according to claim 2, is characterized in that, described digital-to-analogue converter comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn, the 6th electric capacity C
mSBn, the 7th electric capacity C
a1, the 8th electric capacity C
a2, the first switch S
1, second switch S
0, the 3rd switch S, the 4th switch S
1P ~ 5P, the 5th switch S
6P ~ 10P, the 6th switch S
0P, the 7th switch S
1n ~ 5n, the 8th switch S
6n ~ 10n, the 9th switch S
0n;
6th switch S described in described first electric capacity C1 mono-termination
0Pone end, comparator negative input, described 3rd electric capacity C described in described first another termination of electric capacity C1
mSBp, described 7th electric capacity C
a1, second switch S
0with the link of the 3rd switch S;
Described 6th switch S
0Panother termination voltage V
iNPside, described 6th switch S
0P3rd termination voltage V
cMside;
Described 3rd electric capacity C
mSBp5th switch S described in another termination
6P ~ 10Pone end; Described 5th switch S
6P ~ 10Panother termination voltage V
refp, described 5th switch S
6P ~ 10P3rd termination V
cM;
Described 4th electric capacity C
lSBp4th switch S described in one termination
1P ~ 5Pone end; Described 4th electric capacity C
lSBp7th electric capacity C described in another termination
a1one end;
Described 4th switch S
1P ~ 5Panother termination voltage V
refp, described 4th switch S
1P ~ 5P3rd termination voltage V
cMside;
Described second switch S
04th switch S described in another termination
1P ~ 5Pwith described 4th electric capacity C
lSBplink;
Comparator normal phase input end described in described 3rd another termination of switch S, described second electric capacity C2, described 6th electric capacity C
mSBn, described 8th electric capacity C
a2, described first switch S
1link;
9th switch S described in described second another termination of electric capacity C2
0none end; Described 9th switch S
0nanother termination voltage V
iNN, described 9th switch S
0n3rd termination voltage V
cMside;
Described 6th electric capacity C
mSBn8th switch S described in another termination
6n ~ 10none end; Described 8th switch S
6n ~ 10nother end voltage V
refn, described 8th switch S
6n ~ 10n3rd termination voltage V
cMside;
Described 8th electric capacity C
a25th electric capacity C described in another termination
lSBnone end; Described 5th electric capacity C
lSBn7th switch S described in another termination
1n ~ 5nwith described first switch S
1link;
Described 7th switch S
1n ~ 5nother end voltage V
refn, described 7th switch S
1n ~ 5n3rd termination voltage V
cMside.
4. successive approximation analog-to-digital conversion circuit according to claim 3, is characterized in that, adopts unit coupling capacitance to connect height section capacitor array.
5. successive approximation analog-to-digital conversion circuit according to claim 4, is characterized in that, described comparator adopts and exports imbalance memory technology.
6. an electronic equipment, is characterized in that, comprising: successive approximation analog-to-digital conversion circuit; This circuit comprises: digital-to-analogue converter, comparator, successive approximation register and logic control circuit;
Described digital-to-analogue converter is used for the digital signal collected to be converted into analog signal, and described analog signal is sent to described comparator input terminal;
Described comparator is used for the described analog signal received to compare, and exports a binary value to described successive approximation register;
The binary value that described successive approximation register exports for storing described comparator, and generate described successive approximation analog-to-digital conversion inside circuit control signal, and described control signal is sent to described logic control circuit;
Control signal after described adjustment for adjusting the driving force of described control signal, and is sent to described digital-to-analogue converter by described logic control circuit, to realize corresponding controlling functions.
7. electronic equipment according to claim 6, is characterized in that, described digital-to-analogue converter adopts sectional capacitance structure.
8. electronic equipment according to claim 7, is characterized in that, described digital-to-analogue converter comprises: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C
mSBp, the 4th electric capacity C
lSBp, the 5th electric capacity C
lSBn, the 6th electric capacity C
mSBn, the 7th electric capacity C
a1, the 8th electric capacity C
a2, the first switch S
1, second switch S
0, the 3rd switch S, the 4th switch S
1P ~ 5P, the 5th switch S
6P ~ 10P, the 6th switch S
0P, the 7th switch S
1n ~ 5n, the 8th switch S
6n ~ 10n, the 9th switch S
0n;
6th switch S described in described first electric capacity C1 mono-termination
0Pone end, comparator negative input, described 3rd electric capacity C described in described first another termination of electric capacity C1
mSBp, described 7th electric capacity C
a1, second switch S
0with the link of the 3rd switch S;
Described 6th switch S
0Panother termination voltage V
iNPside, described 6th switch S
0P3rd termination voltage V
cMside;
Described 3rd electric capacity C
mSBp5th switch S described in another termination
6P ~ 10Pone end; Described 5th switch S
6P ~ 10Panother termination voltage V
refp, described 5th switch S
6P ~ 10P3rd termination voltage V
cMside;
Described 4th electric capacity C
lSBp4th switch S described in one termination
1P ~ 5Pone end; Described 4th electric capacity C
lSBp7th electric capacity C described in another termination
a1one end;
Described 4th switch S
1P ~ 5Panother termination voltage V
refp, described 4th switch S
1P ~ 5P3rd termination voltage V
cMside;
Described second switch S
04th switch S described in another termination
1P ~ 5Pwith described 4th electric capacity C
lSBplink;
Comparator normal phase input end described in described 3rd another termination of switch S, described second electric capacity C2, described 6th electric capacity C
mSBn, described 8th electric capacity C
a2, described first switch S
1link;
9th switch S described in described second another termination of electric capacity C2
0none end; Described 9th switch S
0nanother termination voltage V
iNN, described 9th switch S
0n3rd termination voltage V
cMside;
Described 6th electric capacity C
mSBn8th switch S described in another termination
6n ~ 10none end; Described 8th switch S
6n ~ 10nother end voltage V
refn, described 8th switch S
6n ~ 10n3rd termination voltage V
cMside;
Described 8th electric capacity C
a25th electric capacity C described in another termination
lSBnone end; Described 5th electric capacity C
lSBn7th switch S described in another termination
1n ~ 5nwith described first switch S
1link;
Described 7th switch S
1n ~ 5nother end voltage V
refn, described 7th switch S
1n ~ 5n3rd termination voltage V
cMside.
9. electronic equipment according to claim 8, is characterized in that, adopts unit coupling capacitance to connect height section capacitor array.
10. electronic equipment according to claim 9, is characterized in that, described comparator adopts and exports imbalance memory technology.
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