CN107565955B - Input signal amplitude of oscillation enhanced signal transmission circuit - Google Patents
Input signal amplitude of oscillation enhanced signal transmission circuit Download PDFInfo
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- CN107565955B CN107565955B CN201710783941.0A CN201710783941A CN107565955B CN 107565955 B CN107565955 B CN 107565955B CN 201710783941 A CN201710783941 A CN 201710783941A CN 107565955 B CN107565955 B CN 107565955B
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Abstract
The invention belongs to IC design technical fields, specially a kind of signal circuit, the input signal amplitude of oscillation enhanced signal transmission circuit include a charge transmission MOSFET pipe S, a negative voltage transmission MOSFET pipe B, a voltage switch K, a circuit for generating negative voltage, a generating positive and negative voltage clock generation circuit, the first NMOS tube M1, the second NMOS tube M2, PMOS tube M3, first capacitor C1 and the second capacitor C2.Its advantage is that: input signal amplitude of oscillation enhanced signal transmission circuit provided by the present invention overcomes the problem that signal swing is limited in existing signal circuit, can be widely applied in various types of signal processing circuit.
Description
Technical field
The present invention relates to a kind of enhanced charge letters of input signal amplitude of oscillation for charge coupling assembly line analog to digital converter
Number transmission circuit, belongs to technical field of integrated circuits.
Technical background
With the continuous development of Digital Signal Processing, the digitlization of electronic system and it is integrated be inexorable trend.So
And the signal in reality is mostly the analog quantity of consecutive variations, need to become digital signal by analog-to-digital conversion can be input to number
It is handled and is controlled in system, thus analog-digital converter is indispensable composition portion in following Design of Digital System
Point.In application fields such as broadband connections, digital high-definition television and radars, system requirements analog-digital converter has very high simultaneously
Sampling rate and resolution ratio.High sampling is not only wanted in requirement of the portable terminal product of these application fields for analog-digital converter
Rate and high-resolution, power consumption should also minimize.
Currently, can be achieved at the same time high sampling rate and high-resolution analog-digital converter structure as pipeline organization modulus
Converter.Pipeline organization is a kind of transformational structure of multistage, and every level-one uses the analog-digital converter of the basic structure of low precision,
Input signal is by processing step by step, finally by every grade of the high-precision output of result combination producing.Its basic thought is exactly handle
The conversion accuracy generally required is evenly distributed to every level-one, and the transformation result of every level-one merges available final
Transformation result.Since pipeline organization analog-digital converter can realize best trade-off on speed, power consumption and chip area, because
This is still able to maintain higher speed and lower power consumption when realizing the analog-to-digital conversion of degree of precision.
The mode of the realization pipeline organization analog-digital converter of existing comparative maturity is the flowing water based on switched capacitor technique
Cable architecture.The work of sampling hold circuit and each height grade circuit is also all necessary in production line analog-digital converter based on the technology
Use the operational amplifier of high-gain and wide bandwidth.The speed and processing accuracy of analog-digital converter depend on used high-gain with
Speed and precision is established in the operational amplifier negative-feedback of ultra wide bandwidth.Therefore such pipeline organization Design of A/D Converter
Core is the design of the operational amplifier of used high-gain and ultra wide bandwidth.These high-gains and wide bandwidth operational amplifier
Using the speed and precision of switched-capacitor pipelines analog-digital converter is limited, become the master of such performance of analog-to-digital convertor raising
Limit bottleneck, and in the case that precision is constant analog-digital converter power consumption levels with speed the linear ascendant trend of raising.
The power consumption levels of the production line analog-digital converter based on switched-capacitor circuit are reduced, most straightforward approach is exactly to reduce or disappear
Go the use of the operational amplifier of high-gain and ultra wide bandwidth.
Charge coupling assembly line analog to digital converter is exactly a kind of operational amplifier without using high-gain and ultra wide bandwidth
There is low power consumption characteristic to be able to achieve high speed and high-precision again simultaneously for analog-digital converter, the structural module converter.Charged Couple
Production line analog-digital converter uses Charged Couple signal processing technology.In circuit, signal is indicated in the form of charge packet, charge packet
Size represent different size of semaphore, storage of the different size of charge packet between different memory nodes, transmission, plus/minus,
The processing such as compare and realizes signal processing function.Carry out the different size of charge packet of drive control not by using periodic clock
Analog-digital conversion function can be realized with the signal processing between memory node.
In charge coupling assembly line analog to digital converter, charge coupling assembly line grade circuits at different levels are transmitted by the same level charge
Control switch, multiple charge physical store nodes, multiple charge storage cells for being connected to charge-storage node, multiple comparisons
Device, multiple reference charge selection circuits controlled by comparator output result are constituted under the control of control clock.Flowing water at different levels
In the course of work of line grade circuit, the transmission of charge, compares the charge physics that the functions such as quantization surround each sub- grade at plus/minus
Memory node carries out.
Since the realization of production line analog-digital converter includes a large amount of digital circuit, and common CMOS process is to realize this
The optimised process of a little large scale digital circuits.The charge of ultrahigh speed and superhigh precision is realized by Digital Signal Processing
Production line analog-digital converter is coupled, a most crucial problem is exactly the storage transmission of charge signal, compares quantization and plus-minus
The committed steps such as operation efficiently and can be realized accurately under the conditions of existing common CMOS process.Therefore, for by big rule
Mould Digital Signal Processing is realized at high speed and high-precision charge coupling assembly line analog to digital converter, it is necessary to be provided a kind of suitable
High-precision charge signal circuit for common CMOS process.
Realization for efficient signal transmission technology, existing technical implementation way typically have patent: US2007/
0279507A1 enhanced signal transmission circuit, exemplary circuit configuration are as shown in Figure 1.The grid of charge signal transmission MOSFET pipe S
Pole VGIt is connected to the output end for the operational amplifier 1 being made of metal-oxide-semiconductor M1, M2 and M3.The output end operation of operational amplifier 1
Before charge transmission, S is in an off state, and charge to be transmitted is stored in C1On.Fig. 2 is that the operating voltage waveform of the circuit shows
It is intended to.T0 moment, Ck1 occur negative rank and more change, and Ck1n occurs positive exponent and more changes, and lead to Ni voltage VNiIt is mutated to a low potential
And the voltage V of NoNoIt is mutated to a high potential, operational amplifier 1 will respond the variation and drive MOSFET pipe S grid VGElectricity
Pressure is high level, so that S is begun to turn on；Due to the reason of potential difference, stored charge will electronically turn to No on Ni
It moves, causes VNiRise and VNoDecline, operational amplifier 1 can will equally respond the variation and drive MOSFET pipe S grid VGVoltage
It gradually decreases；At the t1 moment, work as VNiRise to voltage VRWhen, VGVoltage is gradually lowered to blanking voltage VthWhen, S is turned off again, electricity
Lotus transmission process terminates, wherein VRIt is determined by the quiescent point of cascade operational amplifier.
For signal circuit shown in Fig. 1, the outstanding problem faced under low voltage condition is that they can be handled
The input analog signal amplitude of oscillation it is limited, be unable to reach demand of the general ADC to the input analog signals difference amplitude of oscillation.Such as institute in Fig. 2
Show, when charge transmission and a maximum difference of voltage transmission are the charge ends of transmission, the source and leakage both ends of MOSFET pipe S is kept
One pressure difference VDS, for safe and reliable, this V of MOSFET pipe S for guaranteeing charge transfer processDSPressure difference is typically provided at
20% VDD supply voltage or so.Under the 1.8V voltage conditions of early period, MSVDSPressure difference is typically provided at 0.35~
0.4V, this just significantly reduces the input analog signal swing range that charge-domain ADC assembly line grade circuit can be handled.
Mainly relevant signal node is charge transfer tube to the input signal amplitude of oscillation of signal circuit shown in Fig. 1
The grid of MOSFET pipe S, four end of leakage, source and substrate.Due to the source and drain terminal of charge transfer tube MOSFET pipe S in actual circuit
Two connected sub- grade circuits of front and back are belonging respectively to, therefore the capacitor of source is the 2 of drain terminal capacitorN(N is flowing water where source again
The digit of line grade circuit), drain terminal voltage fall is the 2 of source when charge being caused to transmitNTimes, therefore effective letter of circuit
Number amplitude of oscillation is mainly shown as drain terminal voltage fall, it may be assumed that VA=VCk1n-VDS-VR, VAFor drain terminal voltage fall, VCk1nFor
The high level voltage of charge pass control signal Ck1n.Under low voltage condition, VDSOccupied 20%VDDThe pressure difference of voltage does not have
There is optimization space；By reducing VRIt can increase the signal swing of circuit, but VRMinimum voltage limited by the end S, and S is most
Low-voltage will receive the limitation of signal ' ground level ' voltage.Therefore, Yao Zeng great signal swing, it is necessary to overcome VRThe signal of voltage
' ground level '.In the present invention, to overcome VRThe signal ' ground level ' of voltage limits, by the way of negative voltage decompression, pass through by
The mode that the underlayer voltage of MOSFET pipe S connects negative voltage reduces the minimum of the end S voltage, can be substantially reduced V in this wayRVoltage
Lower limit, to achieve the purpose that increase the input signal amplitude of oscillation.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of input signal amplitude of oscillation enhanced signal is provided
Transmission circuit, specifically a kind of high-precision charge transfer circuit suitable for common CMOS process.
According to technical solution provided by the invention, it is characterized in that: including that a charge transmits MOSFET pipe S, a negative electricity
Pressure transmission MOSFET pipe B, a voltage switch K, a circuit for generating negative voltage, a generating positive and negative voltage clock generation circuit, the
One NMOS tube M1, the second NMOS tube M2, PMOS tube M3, first capacitor C1 and the second capacitor C2；
It is correspondingly connected with relationship are as follows: the grid end of the first NMOS tube M1 is connected to charge node Ni to be transmitted, i.e. charge transmits
The source electrode of MOSFET pipe S；The source and substrate of first NMOS tube M1 is connected to ground level, and the drain terminal of the first NMOS tube M1 is connected to
The source of second NMOS tube M2；The drain terminal of second NMOS tube M2 is connected to the drain terminal and charge transmission MOSFET pipe S of PMOS tube M3
Grid end, the grid end of the second NMOS tube M2 is connected to the first bias voltage, the Substrate ground level of the second NMOS tube M2；PMOS tube
The grid end of M3 is connected to the second bias voltage, and the source and substrate of PMOS tube M3 is connected to supply voltage；Charge transmission objectives section
Point No, i.e. charge transmit the drain electrode of MOSFET pipe S, meet charge pass control signal Ck1n by the second capacitor C2；Charge is to be passed
Defeated node Ni meets charge pass control signal Ck1 by first capacitor C1；The substrate of charge transmission MOSFET pipe S is connected to voltage
The substrate of the upper end of switch K, charge transmission MOSFET pipe S is also connected to the drain terminal of negative voltage transmission MOSFET pipe B；Voltage switch
The lower end earth level of K, turn-on and turn-off are controlled by charge pass control signal Ck1；The lining of negative voltage transmission MOSFET pipe B
Bottom and source are connected to the output end of circuit for generating negative voltage, and the grid end of negative voltage transmission MOSFET pipe B is connected to generating positive and negative voltage
The output end of clock generation circuit；First and second input terminals of circuit for generating negative voltage are separately connected charge pass control signal
The first and second input terminals of Ck1 and charge pass control signal Ck1n, generating positive and negative voltage clock generation circuit are separately connected charge
Transmission of control signals Ck1 and charge pass control signal Ck1n.
The input signal amplitude of oscillation enhanced signal transmission circuit, it is further characterized in that its charge transmission objectives node No
The peak signal amplitude of oscillation follows following relational expression:
V’A=VCk1n-VDS；
Wherein, V 'AThe signal swing of charge transmission objectives node No；VDSCharge transmits MOSFET when for the charge end of transmission
The source of pipe S and the pressure difference of drain terminal；VCk1nFor the high level voltage of charge pass control signal Ck1n.
The input signal amplitude of oscillation enhanced signal transmission circuit, it is further characterized in that: when it carries out charge transmission, institute
The grid for stating negative voltage transmission MOSFET pipe B connects high level, and negative voltage transmission MOSFET pipe B is in the conductive state, the charge
The substrate of transmission MOSFET pipe S connects negative voltage；After its charge end of transmission, the grid of the negative voltage transmission MOSFET pipe B
Negative voltage is connect, the negative voltage transmission MOSFET pipe B is in an off state, the Substrate ground of the charge transmission MOSFET pipe S
Level；
Wherein, the high level is the positive voltage greater than zero potential；The ground level is zero potential；The negative potential is small
In the negative voltage of ground level.
The invention has the advantages that the input signal amplitude of oscillation enhanced letter provided by the present invention suitable for common CMOS process
Number transmission circuit overcomes the problem that signal swing is limited in existing signal circuit, can be widely applied to Charged Couple
In production line analog-digital converter in Charged Couple grade flowing water circuit at different levels.
Detailed description of the invention
Fig. 1 is existing signal circuit schematic diagram；
Fig. 2 is existing signal circuit operating voltage waveform diagram；
Fig. 3 is input signal amplitude of oscillation enhanced signal transmission circuit structure principle chart of the present invention；
Fig. 4 is input signal amplitude of oscillation enhanced signal transmission circuit operating voltage waveform diagram of the present invention；
Fig. 5 is a kind of realization circuit diagram of circuit for generating negative voltage of the present invention；
Fig. 6 (a) is a kind of realization circuit diagram of generating positive and negative voltage clock generation circuit of the present invention；
Fig. 6 (b) is the voltage oscillogram of generating positive and negative voltage clock generation circuit of the present invention work；
Fig. 7 is input signal amplitude of oscillation enhanced signal transmission circuit of the present invention in charge coupling assembly line analog to digital converter
Application.
Specific embodiment
The present invention is described in more detail with example with reference to the accompanying drawing.
The input signal that the input signal amplitude of oscillation is improved using negative voltage reduction technology that the present invention that Fig. 3 show designs is put
The substrate of width enhanced signal transmission circuit structure principle chart, the MOSFET pipe S in signal circuit shown in Fig. 1 increases
One circuit for generating negative voltage and negative voltage transmission circuit.The input signal amplitude of oscillation enhanced signal transmission circuit includes one
A charge transmission MOSFET pipe S, a negative voltage transmission MOSFET pipe B, a voltage switch K, a circuit for generating negative voltage,
One generating positive and negative voltage clock generation circuit, the first NMOS tube M1, the second NMOS tube M2, PMOS tube M3, first capacitor C1 and second
Capacitor C2.
The input signal amplitude of oscillation enhanced signal transmission circuit is correspondingly connected with relationship are as follows: the grid end of the first NMOS tube M1 connects
It is connected to charge node Ni to be transmitted, the i.e. source electrode of charge transmission MOSFET pipe S；The source and substrate of first NMOS tube M1 is connected to
Ground level, the drain terminal of the first NMOS tube M1 are connected to the source of the second NMOS tube M2；The drain terminal of second NMOS tube M2 is connected to
The grid end of drain terminal and charge transmission the MOSFET pipe S of PMOS tube M3, the grid end of the second NMOS tube M2 are connected to the first bias voltage,
The Substrate ground level of second NMOS tube M2；The grid end of PMOS tube M3 is connected to the second bias voltage, the source of PMOS tube M3 and
Substrate is connected to supply voltage；Charge transmission objectives node No, i.e. charge transmit the drain electrode of MOSFET pipe S, pass through the second capacitor
C2 meets charge pass control signal Ck1n；Charge node Ni to be transmitted meets charge pass control signal Ck1 by first capacitor C1；
The substrate of charge transmission MOSFET pipe S is connected to the upper end of voltage switch K, and the substrate of charge transmission MOSFET pipe S is also connected to
The drain terminal of negative voltage transmission MOSFET pipe B；The lower end earth level of voltage switch K, turn-on and turn-off are transmitted by charge and are controlled
Signal Ck1 control；The substrate and source of negative voltage transmission MOSFET pipe B are connected to the output end of circuit for generating negative voltage, negative electricity
The grid end of pressure transmission MOSFET pipe B is connected to the output end of generating positive and negative voltage clock generation circuit；The first of circuit for generating negative voltage
It is separately connected charge pass control signal Ck1 and charge pass control signal Ck1n with the second input terminal, generating positive and negative voltage clock produces
First and second input terminals of raw circuit are separately connected charge pass control signal Ck1 and charge pass control signal Ck1n.
Foregoing circuit reduces the end S voltage by way of controlling the underlayer voltage of MOSFET pipe S with circuit for generating negative voltage
Minimum, reduce VRThe lower limit of voltage, to achieve the purpose that increase the input signal amplitude of oscillation.Fig. 4 provides the input signal amplitude of oscillation
The operating voltage waveform diagram of enhanced signal transmission circuit, VRVoltage is reduced for V 'R, the minimum of the end S voltage is negative electricity
Pressure keeps VCk1nVoltage and VDSIt is constant, it can be seen that the signal swing V of signal circuitAIncrease VR-V’RDifference electricity
Pressure.The output end signal amplitude of oscillation of the input signal amplitude of oscillation enhanced signal transmission circuit is V 'A=VCk1n-VDS-V’R, and V 'R
Minimum voltage can be ground level, so the output end signal amplitude of oscillation of the input signal amplitude of oscillation enhanced signal transmission circuit
It is up to V 'A=VCk1n-VDS, V 'AThe signal swing of charge transmission objectives node No.
Fig. 5, which show one kind, can be used in the present invention providing negative bias electricity for charge transmission MOSFET pipe S substrate in Fig. 3
A kind of schematic diagram of circuit for generating negative voltage of pressure.Conducting and pass of the circuit using similar capacitor charge and discharge and MOS switch
Disconnected characteristic realizes negative voltage output, and detailed circuit operation principle can refer to United States Patent (USP) US5831844, no longer explain herein
It states.
The negative voltage that circuit for generating negative voltage exports in the present invention transmits MOSFET pipe B by a negative voltage to pass
It is defeated.When the input signal amplitude of oscillation enhanced signal transmission circuit starts to carry out charge transmission, negative voltage transmits MOSFET pipe B
Grid connect high level, negative voltage transmits that MOSFET pipe B is in the conductive state, and the substrate of charge transmission MOSFET pipe S connects negative electricity
Pressure；After the input signal amplitude of oscillation enhanced signal transmission circuit charge end of transmission, negative voltage transmits the grid of MOSFET pipe B
Pole connects negative voltage, and negative voltage transmission MOSFET pipe B is in an off state, and the substrate that charge transmits MOSFET pipe S is transmitted in charge
It controls signal Ck1 and controls lower earth level.
The present invention controls the signal transmission of negative voltage transmission MOSFET pipe B using generating positive and negative voltage clock, and main cause is
It, must by negative voltage transmission MOSFET pipe B shutdown when the source and substrate of negative voltage transmission MOSFET pipe B are negative voltage
The grid end and source voltage terminal difference that must make negative voltage transmission MOSFET pipe B are less than its threshold voltage (V openedthB).According to common
Voltage clocks control the grid end of negative voltage transmission MOSFET pipe B, then when will appear clock low, negative voltage transmits MOSFET pipe
The grid end and source voltage terminal of B is greater than its threshold voltage (V openedthB) state, cause negative voltage transmission MOSFET pipe B cannot
Shutdown.Therefore, the grid end control clock of negative voltage transmission MOSFET pipe B must be controlled using generating positive and negative voltage clock.
High level of the present invention is the positive voltage greater than zero potential；The ground level is no-voltage；The negative potential is
Less than the negative voltage of ground level.
Fig. 6 (a) and Fig. 6 (b), which show one kind, can be used in the present invention generating for one of Fig. 3 generating positive and negative voltage clock
The circuit theory and operating voltage waveform diagram of circuit.Fig. 6 (a) is the circuit theory of the generating positive and negative voltage clock generation circuit, Fig. 6
(b) the input charge transmission of control signals Ck1n and output letter to be emulated when generating positive and negative voltage clock generation circuit work
The voltage oscillogram of number Ck1nout.The circuit is realized just using the characteristic of similar capacitor charge and discharge and digital flip-flop circuit
Negative voltage clock output, detailed circuit operation principle can (one kind be suitable for reference to Chinese patent ZL201010175033.1
The negative-voltage effective transmission circuit of standard CMOS process), principle no longer illustrates herein.
Fig. 7 is application of the present invention in charge coupling assembly line ADC.Turn as shown in the figure for charge coupling assembly line modulus
The sub- level production line circuit specific implementation of 1.5/grade Charged Couples and the sub- level production line circuit of front stage Charged Couple in parallel operation
Specific connection relationship.The sub- level production line circuit of Charged Couple is made of the signal processing channel 100p and 100n of fully differential, charge
Coupling sub- level production line circuit includes that 2 the same level charges transmit control switch (101p and 101n), 2 charge-storage nodes
(104p and 104n), 2 be connected to the charge storage capacitance (106p and 106n) of prime sub- grade circuit charge-storage node, 6
Be connected to the sub- grade circuit charge-storage node of 1.5/grade of the same level charge storage capacitance (107p, 107n, 108p, 108n), 2
Comparator, 2 reference charge selection circuits controlled by comparator output result, 2 are connected to the same level charge-storage node
The charge of next stage grade circuit transmits control switch (102p and 102n), and 2 are connected to next stage grade circuit charge storage
The charge storage capacitance (109p and 109n) of node.In upper figure, prime sub- grade circuit charge-storage node Nip, prime grade electricity
Charge storage capacitance 106p, the same level charge on road transmit control switch 101p, the sub- grade circuit charge storage section of 1.5/grade of the same level
Point 104p constitutes an input signal amplitude of oscillation enhanced signal transmission circuit of the present invention.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (2)
1. a kind of input signal amplitude of oscillation enhanced signal transmission circuit, it is characterized in that: include a charge transmission MOSFET pipe S,
One negative voltage transmission MOSFET pipe B, a voltage switch K, a circuit for generating negative voltage, a generating positive and negative voltage clock generate
Circuit, the first NMOS tube M1, the second NMOS tube M2, PMOS tube M3, first capacitor C1 and the second capacitor C2；
It is correspondingly connected with relationship are as follows: the grid end of the first NMOS tube M1 is connected to charge node Ni to be transmitted, i.e. charge transmits MOSFET
The source electrode of pipe S；The source and substrate of first NMOS tube M1 is connected to ground level, and the drain terminal of the first NMOS tube M1 is connected to second
The source of NMOS tube M2；The drain terminal of second NMOS tube M2 is connected to the drain terminal of PMOS tube M3 and the grid of charge transmission MOSFET pipe S
End, the grid end of the second NMOS tube M2 are connected to the first bias voltage, the Substrate ground level of the second NMOS tube M2；PMOS tube M3's
Grid end is connected to the second bias voltage, and the source and substrate of PMOS tube M3 is connected to supply voltage；Charge transmission objectives node No,
That is the drain electrode of charge transmission MOSFET pipe S, meets charge pass control signal Ck1n by the second capacitor C2；Charge node to be transmitted
Ni meets charge pass control signal Ck1 by first capacitor C1；The substrate of charge transmission MOSFET pipe S is connected to voltage switch K
Upper end, charge transmission MOSFET pipe S substrate be also connected to negative voltage transmission MOSFET pipe B drain terminal；Under voltage switch K
Ground level is terminated, turn-on and turn-off are controlled by charge pass control signal Ck1；Negative voltage transmit MOSFET pipe B substrate and
Source is connected to the output end of circuit for generating negative voltage, and the grid end of negative voltage transmission MOSFET pipe B is connected to generating positive and negative voltage clock
The output end of generation circuit；First and second input terminals of circuit for generating negative voltage are separately connected charge pass control signal Ck1
With charge pass control signal Ck1n, the first and second input terminals of generating positive and negative voltage clock generation circuit are separately connected charge transmission
Control signal Ck1 and charge pass control signal Ck1n；
When carrying out charge transmission, the grid of the negative voltage transmission MOSFET pipe B connects high level, and negative voltage transmits MOSFET pipe
B is in the conductive state, and the substrate of the charge transmission MOSFET pipe S connects negative voltage；After the charge end of transmission, the negative voltage
The grid of transmission MOSFET pipe B connects negative voltage, and the negative voltage transmission MOSFET pipe B is in an off state, the charge transmission
The Substrate ground level of MOSFET pipe S；
Wherein, the high level is the positive voltage greater than zero potential；The ground level is zero potential；The negative voltage is less than ground
The voltage of level.
2. input signal amplitude of oscillation enhanced signal transmission circuit according to claim 1, it is characterised in that the charge transmission
The peak signal amplitude of oscillation of destination node No follows following relational expression:
V’A=VCk1n-VDS；
Wherein, V 'AFor the signal swing of charge transmission objectives node No；VDSCharge transmits MOSFET pipe when for the charge end of transmission
The source of S and the pressure difference of drain terminal；VCk1nFor the high level voltage of charge pass control signal Ck1n.
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| CN108809313A (en) * | 2018-06-19 | 2018-11-13 | 黄山学院 | Using the low-voltage charge transfer circuit of negative voltage and Bootstrap |
| CN108766500A (en) * | 2018-06-19 | 2018-11-06 | 广州领知信息技术有限公司 | High-speed boosting type signal transmission switchs |
| CN108806757A (en) * | 2018-06-19 | 2018-11-13 | 广州领知信息技术有限公司 | High-speed boosting type signal sampling transmitting switch |
| CN109177868A (en) * | 2018-06-19 | 2019-01-11 | 黄山市瑞兴汽车电子有限公司 | Automobile dome light touch screen control circuit with emergency help function |
| CN108847846A (en) * | 2018-06-19 | 2018-11-20 | 黄山学院 | Low-voltage long arc charge transfer circuit |
| CN108809286A (en) * | 2018-06-19 | 2018-11-13 | 苏州睿度智能科技有限公司 | The insensitive enhanced signal transmitting switch of technological fluctuation |
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| TWI474597B (en) * | 2006-05-31 | 2015-02-21 | Intersil Americas LLC | Apparatus for transferring charge |
| CN101860368B (en) * | 2010-05-10 | 2012-12-05 | 中国电子科技集团公司第五十八研究所 | Negative-voltage effective transmission circuit suitable for standard CMOS process |
| CN101867290A (en) * | 2010-06-17 | 2010-10-20 | 清华大学 | Charge pump circuit with low power consumption |
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