CN108809286A - The insensitive enhanced signal transmitting switch of technological fluctuation - Google Patents
The insensitive enhanced signal transmitting switch of technological fluctuation Download PDFInfo
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- CN108809286A CN108809286A CN201810627147.1A CN201810627147A CN108809286A CN 108809286 A CN108809286 A CN 108809286A CN 201810627147 A CN201810627147 A CN 201810627147A CN 108809286 A CN108809286 A CN 108809286A
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- mirror image
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The invention belongs to IC design technical field, specially a kind of insensitive enhanced signal transmitting switch of technological fluctuation, including：One charge transmission MOSFET pipes S, a Bootstrap boost pressure circuit, the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the first capacitance C1 and the second capacitance C2, a charge transmission mirror image MOSFET pipes MSR, the first mirror image NMOS tube M1R, the second mirror image NMOS tube M2R, the first mirror image PMOS tube M3R, current source I1, voltage source V1 and error amplifier AE.Its advantage is that overcome in existing signal transmission switching circuit that signal swing is limited and common mode charge easily by PVT influences of fluctuations the problem of, can be widely applied in various types of signal processing circuit.
Description
Technical field
The present invention relates to a kind of charge signal transmitting switches for charge-domain pipelined analog-digital converter, specially a kind of
Enhanced charge signal transmission switching circuit, belongs to technical field of integrated circuits.
Background technology
With the continuous development of Digital Signal Processing, the digitlization of electronic system and it is integrated be inexorable trend.So
And the signal in reality is mostly the analog quantity of consecutive variations, need to become digital signal by analog-to-digital conversion can be input to number
It is handled and is controlled in system, thus analog-digital converter is indispensable composition portion in following Design of Digital System
Point.In application fields such as broadband connections, digital high-definition television and radars, system requirements analog-digital converter has very high simultaneously
Sampling rate and resolution ratio.High sampling is not only wanted in requirement of the portable terminal product of these application fields for analog-digital converter
Rate and high-resolution, power consumption should also minimize.
Currently, can be achieved at the same time high sampling rate and high-resolution analog-digital converter structure is pipeline organization modulus
Converter.Pipeline organization is a kind of transformational structure of multistage, and the analog-digital converter of the basic structure of low precision is used per level-one,
Input signal is by processing step by step, finally by every grade of the high-precision output of result combination producing.Its basic thought is exactly handle
The conversion accuracy generally required is evenly distributed to every level-one, per level-one transformation result merge can obtain it is final
Transformation result.Since pipeline organization analog-digital converter can realize best trade-off on speed, power consumption and chip area, because
This still can keep higher speed and lower power consumption when realizing the analog-to-digital conversion of degree of precision.
The mode of the realization pipeline organization analog-digital converter of existing comparative maturity is the flowing water based on switched capacitor technique
Cable architecture.The work of sampling hold circuit and each height grade circuit is also all necessary in production line analog-digital converter based on the technology
Use the operational amplifier of high-gain and wide bandwidth.The speed and processing accuracy of analog-digital converter depend on used high-gain with
Speed and precision are established in the operational amplifier negative-feedback of ultra wide bandwidth.Therefore such pipeline organization Design of A/D Converter
Core is the design of the operational amplifier of used high-gain and ultra wide bandwidth.These high-gains and wide bandwidth operational amplifier
Using the speed and precision for limiting switched-capacitor pipelines analog-digital converter, become the master of such performance of analog-to-digital convertor raising
Limit bottleneck, and in the case that precision is constant analog-digital converter power consumption levels with speed the linear ascendant trend of raising.
The power consumption levels of the production line analog-digital converter based on switched-capacitor circuit are reduced, most straightforward approach is exactly to reduce or disappear
Go the use of the operational amplifier of high-gain and ultra wide bandwidth.
Charge-domain pipelined analog-digital converter is exactly a kind of mould without using high-gain and the operational amplifier of ultra wide bandwidth
There is low power consumption characteristic can realize high speed and high-precision again simultaneously for number converter, the structural module converter.Charge-domain flowing water
Line analog-digital converter uses charge-domain signal processing technology.In circuit, signal is indicated in the form of charge packet, the size of charge packet
Represent different size of semaphore, storage, transmission, plus/minus, comparison etc. of the different size of charge packet between different memory nodes
Signal processing function is realized in processing.Carry out the different size of charge packet of drive control in different storages by using periodic clock
Signal processing between node can realize analog-digital conversion function.
In charge-domain pipelined analog-digital converter, charge-domain pipelined sub- grade circuits at different levels are by this grade of charge transmission control
It is switch, multiple charge physical store nodes, multiple charge storage cells for being connected to charge-storage node, multiple comparators, more
A reference charge selection circuit that output control is exported by comparator is constituted under the control of control clock.Each level production line grade
In the course of work of circuit, the transmission of charge, compares the charge physical store section that the functions such as quantization surround each sub- grade at plus/minus
Point carries out.
Since the realization of production line analog-digital converter includes a large amount of digital circuit, and common CMOS process is to realize this
The optimised process of a little large scale digital circuits.The charge of ultrahigh speed and superhigh precision is realized by Digital Signal Processing
Domain pipelined analog-digital converter, most crucial problem are exactly the storage transmission of charge signal, compare quantization and plus-minus fortune
The committed steps such as calculation efficiently and can be realized accurately under the conditions of existing common CMOS process.Therefore, it is by extensive
Digital Signal Processing is realized at high speed and the charge-domain pipelined analog-digital converter of high-precision, it is necessary to be provided one kind and is suitable for
The high-precision charge signal transmission of common CMOS process switchs.
Realization for efficient signal transmission technology, existing technical implementation way typically have patent：US2007/
0279507A1 enhanced signals transmitting switch (BCT), exemplary circuit configuration is as shown in Figure 1.Charge signal transmits MOSFET pipes
The grid V of SGIt is connected to by the output end of metal-oxide-semiconductor M1, M2 and M3 operational amplifier 1 constituted.The output of operational amplifier 1
Before holding the transmission of operation charge, S is off state, and charge to be transmitted is stored in C1On.Fig. 2 is the operating voltage of the circuit
Waveform diagram.T0 moment, Ck1 occur negative rank and more change, and Ck1n occurs positive exponent and more changes, and leads to Ni voltages VNiIt is mutated to one
The voltage V of low potential and NoNoIt is mutated to a high potential, operational amplifier 1 will respond the variation and drive MOSFET pipe S grid
Pole VGVoltage is high level so that S is begun to turn on；Due to the reason of potential difference, stored charge will be electronically on Ni
It is shifted to No, causes VNiRise and VNoDecline, operational amplifier 1 can will equally respond the variation and drive MOSFET pipe S grids
VGVoltage continuously decreases；At the t1 moment, work as VNiRise to voltage VRWhen, VGVoltage is gradually lowered to blanking voltage VthWhen, S is closed again
Disconnected, charge transfer process terminates, wherein VRIt is determined by the quiescent point of cascade operational amplifier.
The quantity of electric charge Q that circuit shown in Fig. 1 is transmitted within a clock cycleTC can be used1Upper charge variable quantity indicates.
In above formula, VCK1(t0)、VCK1(t1)、VNi(t0) it is the fixed amount directly controlled by reference voltage；VNi(t0) by
Signal charge quantity to be transmitted determines, and VNi(t1) it is approached in the charge end of transmission to voltage VR.In entire charge transfer process,
VNiTo VRThe speed and precision approached directly determine the charge transmission speed and precision of BCT circuits.If VRIt is precise and stable, then it passes
The quantity of electric charge transmitted during defeated is the linear function of signal charge to be transmitted.But due to VRBy cascade operational amplifier
Quiescent point determine, VRPVT (technological fluctuation, supply voltage noise, temperature change) is fluctuated very sensitive.Assuming that by
V is fluctuated in PVTRProduce the variation of Δ V, corresponding VNi(t1) voltage variety of Δ V will be will produce.By (1) formula, we can be with
See that Δ V can be directly in QTUpper generation Δ Q=Δs V*C1The error quantity of electric charge.In charge-domain pipelined ADC, the error is direct
It is transferred to late-class circuit, therefore to realize that high-precision charge transmits, which must control effectively.
In addition to common mode problem, an outstanding problem that BCT shown in Fig. 1 is also faced under low voltage condition, which is them, to be located
The input analog signal amplitude of oscillation of reason is limited, is unable to reach demands of the general ADC to the input analog signals difference amplitude of oscillation.In Fig. 2
Shown, when a maximum difference of charge transmission and voltage transmission is the charge end of transmission, the source and leakage both ends of MOSFET pipes S are protected
A pressure difference V is heldDS, to ensure safe and reliable, this V of MOSFET pipes S of charge transfer processDSPressure difference is generally positioned
In 20% VDD supply voltages or so.Under the 1.8V voltage conditions of early period, MSVDSPressure difference is typically provided at 0.35~
0.4V, this just significantly reduces the input analog signal swing range that charge-domain ADC assembly line grade circuits can be handled.With Fig. 1
The input signal amplitude of oscillation of shown BCT grid, leakage, source and substrate that mainly relevant signal node is charge transfer tube MOSFET pipes S
Four ends.Since source is belonging respectively to front and back two sub- grade circuits being connected, the capacitance of source with drain terminal in actual circuit
It is the 2 of drain terminal capacitanceN(N is the digit of sub- grade circuit where source) again, drain terminal voltage fall is when charge being caused to transmit
The 2 of sourceNTimes, therefore the useful signal amplitude of oscillation of circuit is mainly shown as drain terminal voltage fall, i.e.,：VA=VCK1n-VDS-VR,
VCK1nThe high level voltage of signal CK1n in order to control.Under low voltage condition, VDSOccupied 20%VDDThe pressure difference of voltage does not have
Optimize space；VCK1nVoltage is the reference voltage of overall importance of chip, and theoretical maximum can be VDD, but its maximum value is also in practice
It is limited by G terminal voltages, and G terminal voltage maximum values are only supply voltage VDD, there is apparent limitation.Therefore, to increase the signal of BCT
The amplitude of oscillation, it is necessary to overcome VCK1nThe V of voltageDDLimitation.
In the present invention, BCT common modes tender subject, V is controlled using mirror image control technology in order to controlRVoltage, to inhibit
BCT common mode charges are influenced by PVT；To overcome VCK1nThe V of voltageDDLimitation will when charge transmits using Bootstrap technology
G terminal voltages raise a VDDVoltage, such VCK1nThe upper limit of voltage can be increased to VDDVoltage, to increase the signal pendulum of BCT
Width.
Invention content
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of insensitive enhanced letter of technological fluctuation is provided
Number transmitting switch, is a kind of high-precision charge transfer circuit suitable for common CMOS process.
A kind of insensitive enhanced signal transmitting switch of technological fluctuation, it is characterized in that transmitting MOSFET pipes including a charge
S, a Bootstrap boost pressure circuit, the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the first capacitance C1 and
Two capacitance C2, charge transmission mirror image MOSFET pipes MSR, the first mirror image NMOS tube M1R, the second mirror image NMOS tube M2R, first
Mirror image PMOS tube M3R, current source I1, voltage source V1 and error amplifier AE；
The connection relation of the insensitive enhanced signal transmitting switch of technological fluctuation is：The grid end of first NMOS tube M1 connects
It is connected to charge node Ni to be transmitted, the i.e. source electrode of charge transmission MOSFET pipes S, is also connected to the voltage of Bootstrap boost pressure circuit
Input terminal；The source of first NMOS tube M1 is connected to ground level, and the drain terminal of the first NMOS tube M1 is connected to the second NMOS tube M2's
Source, the substrate of the first NMOS tube M1 are connected to the error output of the substrate and error amplifier AE of the first mirror image NMOS tube M1R
End；The drain terminal of second NMOS tube M2 is connected to the drain terminal of the first PMOS tube M3 and the grid end G of charge transmission MOSFET pipes S, and second
The grid end of NMOS tube M2 is connected to the first bias voltage, the Substrate ground level of the second NMOS tube M2；The grid of first PMOS tube M3
End is connected to the second bias voltage, and the source and substrate of the first PMOS tube M3 are connected to the voltage output of Bootstrap boost pressure circuit
Hold Vboost；The source of first mirror image NMOS tube M1R is connected to ground level, and the drain terminal of the first mirror image NMOS tube M1R is connected to second
The source of mirror image NMOS tube M2R；The drain terminal of second mirror image NMOS tube M2R is connected to the drain terminal and electricity of the first mirror image PMOS tube M3R
Lotus transmits the grid end of mirror image MOSFET pipes MSR, and the grid end of the second mirror image NMOS tube M2R is connected to the first bias voltage, the second mirror
As the Substrate ground level of NMOS tube M2R；The grid end of first mirror image PMOS tube M3R is connected to the second bias voltage, the first mirror image
The source and substrate of PMOS tube M3R is connected to the voltage output end V of Bootstrap boost pressure circuitboost；Charge transmission objectives node
No, i.e. charge transmit the drain electrode of MOSFET pipes S, and control signal Ck1n is met by the second capacitance C2；Charge node Ni to be transmitted is logical
It crosses the first capacitance C1 and meets control signal Ck1；Charge transmits MOSFET pipes S and the substrate of charge transmission mirror image MOSFET pipes MSR is equal
It is connected to ground level；The input end of clock connection control signal Ck1 of Bootstrap boost pressure circuit；The negative voltage of error amplifier AE
Input terminal connects reference voltage V 'RError output, error amplifier AE positive voltages input terminal connect the first mirror image NMOS simultaneously
The current input terminal of the grid end of pipe M1R, the source and current source I1 of charge transmission mirror image MOSFET pipes MSR；The electricity of current source I1
Flow output end earth level；The high-voltage output terminal of voltage source V1 connects the drain terminal of charge transmission mirror image MOSFET pipes MSR, voltage source
The low-voltage output of V1 terminates ground level.
The insensitive enhanced signal transmitting switch of technological fluctuation, it is further characterized in that：The NMOS tube M1, NMOS tube
M2, PMOS tube M3 and charge transmission MOSFET pipes S constitute original BCT, mirror image NMOS tube M1R, mirror image NMOS tube M2R, mirror image
PMOS tube M3R and charge transmission mirror image MOSFET pipes MSR constitute mirror image BCT；The mirror image BCT is corresponding with original BCT circuits
Metal-oxide-semiconductor size is linear equal proportion relationship.
The insensitive enhanced signal transmitting switch of technological fluctuation, it is further characterized in that：The MOSFET pipes S and charge
Transmitting mirror image MOSFET pipes MSR uses deep N-well NMOS tube, the underlayer voltage of two metal-oxide-semiconductors in this way to become adjustable.
The insensitive enhanced signal transmitting switch of technological fluctuation, it is further characterized in that：The current source I1It is designed
Must be very small, for charge transmission mirror image MOSFET pipes MSR to be biased in the state that will end, and the first mirror image
The grid voltage V of NMOS tube M1RSValue be equal to reference voltage V 'R。
The insensitive enhanced signal transmitting switch of technological fluctuation, it is further characterized in that：When carrying out charge transmission, grid
Pressure bootstrapping boost pressure circuit is in pressurized state, and the grid of the charge transmission MOSFET pipes is high level VDD+VNi, charge voltage
It is in the conduction state to transmit MOSFET pipes；After the charge end of transmission, Bootstrap boost pressure circuit is in charged state, the electricity
Lotus transmits the grounded-grid level of MOSFET pipes, and the charge transmission MOSFET pipes are off state；Wherein, VDDFor power supply electricity
Pressure, VNiFor the source voltage of MOSFET pipes.
It is an advantage of the invention that：Technological fluctuation provided by the present invention suitable for common CMOS process is insensitive enhanced
Signal transmission switchs, and overcomes signal swing in existing signal transmission switch and is limited with common mode charge easily by PVT influences of fluctuations
Problem can be widely applied in charge-domain pipelined analog-digital converter in charge-domain grade flowing water circuit at different levels.
Below with reference to drawings and examples, the present invention is described in detail.
Description of the drawings
Fig. 1 is existing signal transmission on-off principle figure.
Fig. 2 is that existing signal transmission switchs operating voltage waveform diagram.
Fig. 3 is that present invention process fluctuates insensitive enhanced signal transmitting switch structure principle chart.
Fig. 4 is that present invention process fluctuates insensitive enhanced signal transmitting switch operating voltage waveform diagram.
Fig. 5 is a kind of realization circuit diagram of Bootstrap boost pressure circuit of the present invention.
Fig. 6 is that present invention process fluctuates insensitive enhanced signal transmitting switch in charge-domain pipelined analog-digital converter
Application.
Specific implementation mode
Embodiment is below in conjunction with the accompanying drawings described in more detail the present invention with example.
What the present invention that Fig. 3 show designed is controlled common mode fluctuation using mirror image control technology and is pressurized using Bootstrap
Technology is come the insensitive enhanced signal transmitting switch structure principle chart of technological fluctuation that improves the input signal amplitude of oscillation, in Fig. 1 institutes
Show signal transmission switch in MOSFET pipes S source electrode and power vd D between increase a Bootstrap boost pressure circuit, also increase
An image copying circuit is added.The insensitive enhanced signal transmitting switch of technological fluctuation includes：One charge transmission
MOSFET pipes S, a Bootstrap boost pressure circuit, the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the first electricity
Hold C1 and the second capacitance C2, charge transmission mirror image MOSFET pipes MSR, the first mirror image NMOS tube M1R, a second mirror image NMOS tube
M2R, the first mirror image PMOS tube M3R, current source I1, voltage source V1 and error amplifier AE.
The connection relation of the insensitive enhanced signal transmitting switch of technological fluctuation is：The grid end of first NMOS tube M1 connects
It is connected to charge node Ni to be transmitted, the i.e. source electrode of charge transmission MOSFET pipes S, is also connected to the voltage of Bootstrap boost pressure circuit
Input terminal；The source of first NMOS tube M1 is connected to ground level, and the drain terminal of the first NMOS tube M1 is connected to the second NMOS tube M2's
Source, the substrate of the first NMOS tube M1 are connected to the error output of the substrate and error amplifier AE of the first mirror image NMOS tube M1R
End；The drain terminal of second NMOS tube M2 is connected to the drain terminal of the first PMOS tube M3 and the grid end G of charge transmission MOSFET pipes S, and second
The grid end of NMOS tube M2 is connected to the first bias voltage, the Substrate ground level of the second NMOS tube M2；The grid of first PMOS tube M3
End is connected to the second bias voltage, and the source and substrate of the first PMOS tube M3 are connected to the voltage output of Bootstrap boost pressure circuit
Hold Vboost；The source of first mirror image NMOS tube M1R is connected to ground level, and the drain terminal of the first mirror image NMOS tube M1R is connected to second
The source of mirror image NMOS tube M2R；The drain terminal of second mirror image NMOS tube M2R is connected to the drain terminal and electricity of the first mirror image PMOS tube M3R
Lotus transmits the grid end of mirror image MOSFET pipes MSR, and the grid end of the second mirror image NMOS tube M2R is connected to the first bias voltage, the second mirror
As the Substrate ground level of NMOS tube M2R；The grid end of first mirror image PMOS tube M3R is connected to the second bias voltage, the first mirror image
The source and substrate of PMOS tube M3R is connected to the voltage output end V of Bootstrap boost pressure circuitboost；Charge transmission objectives node
No, i.e. charge transmit the drain electrode of MOSFET pipes S, and control signal Ck1n is met by the second capacitance C2；Charge node Ni to be transmitted is logical
It crosses the first capacitance C1 and meets control signal Ck1；Charge transmits MOSFET pipes S and the substrate of charge transmission mirror image MOSFET pipes MSR is equal
It is connected to ground level；The input end of clock connection control signal Ck1 of Bootstrap boost pressure circuit；The negative voltage of error amplifier AE
Input terminal connects reference voltage V 'RError output, error amplifier AE positive voltages input terminal connect the first mirror image NMOS simultaneously
The current input terminal of the grid end of pipe M1R, the source and current source I1 of charge transmission mirror image MOSFET pipes MSR；The electricity of current source I1
Flow output end earth level；The high-voltage output terminal of voltage source V1 connects the drain terminal of charge transmission mirror image MOSFET pipes MSR, voltage source
The low-voltage output of V1 terminates ground level.
Wherein, the control signal Ck1 and control signal Ck1n is high level not overlapping bursts signal.
In circuit shown in Fig. 3, NMOS tube M1, NMOS tube M2, PMOS tube M3 and charge transmission MOSFET pipes S constitute original
BCT, mirror image NMOS tube M1R, mirror image NMOS tube M2R, mirror image PMOS tube M3R and charge transmission mirror image MOSFET pipes MSR constitute mirror
As BCT.To reduce power consumption, 4 image copying metal-oxide-semiconductors metal-oxide-semiconductor size corresponding with original BCT circuits is closed for linear equal proportion
System, can be with scaled down.I.e.：The size ratio of NMOS tube M1 and mirror image NMOS tube M1R is K, NMOS tube M2 and mirror image NMOS tube
The size ratio that the size ratio of M2R is similarly K, PMOS tube M3 and mirror image PMOS tube M3R is similarly K, charge transmit MOSFET pipes S with
The size ratio of charge transmission mirror image MOSFET pipes MSR is similarly K, and wherein K is any positive number.It is reduction circuit work(in actual circuit
Consumption generally selects K as 1/5, the 1/10 equal decimal less than 1.
To realize that preferably control, charge transmission MOSFET pipes S and charge transmission mirror image MOSFET pipes MSR have used depth
The underlayer voltage of N trap NMOS tubes, in this way two metal-oxide-semiconductors becomes adjustable.To realize mirror image circuit to original BCT circuits in charge
Transmission when closing to an end state accurately control, current source I in Fig. 31It is designed to be very small, for charge to be transmitted mirror image
MOSFET pipes MSR is biased in the state that will end, and the value of the grid voltage of the first mirror image NMOS tube M1R should with it is original
V in BCT circuitsRIt is identical, and it is equal to reference voltage V 'R.Vs of the error amplifier AE that gain is K in figure for detectionSWith
MSR underlayer voltages VADJBetween error, the error amplifier is using negative-feedback connection structure by VSSize clamp in V 'R, and V 'R
It may be used and do not generated by the reference signal of PVT influences of fluctuations accurately, ensure that the V in original BCT circuits in this wayRAccurately controlled
System, therefore the PVT surge suppression capabilities of entirety BCT circuits greatly improve.
In actual circuit, the switched-capacitor circuit that low rate may be used in error amplifier AE realizes the circuit to reduce
Circuit power consumption, reason are the pace of change of PVT fluctuations more slowly.Current source I1 and voltage source V1 are using conventional biasing
Current generating circuit and bias-voltage generating circuit can be realized.
Fig. 4 provides the operating voltage waveform diagram of the insensitive enhanced signal transmitting switch of technological fluctuation, by using
G terminal voltages are raised a V by grid Bootstrap technology when charge transmitsDDVoltage, such VCK1nThe upper limit of voltage can improve
To VDDVoltage, to achieve the purpose that increase BCT signal swings.VCK1nVoltage is raised to V 'CK1n, the theoretic upper limit can be with
It is increased to VDD, it can be seen that the signal swing V ' of BCT circuitsAIncrease (V 'CK1n-VCK1n)。
Fig. 5 show a kind of schematic diagram for the Bootstrap boost pressure circuit can be used for the present invention.Its principle is as follows：Clock
When Ck1 is high level, metal-oxide-semiconductor Mb2, Mb6 conducting, metal-oxide-semiconductor Mb7 is by Mb4 conductings so that metal-oxide-semiconductor Mb1 is also switched on；Circuit is logical
It crosses metal-oxide-semiconductor Mb1 and Mb2 to charge to capacitance Cb1 so that the voltage at the both ends capacitance Cb1 is close to supply voltage VDD, in capacitance
V is stored on CblDD* the electricity of Cb1, Bootstrap boost pressure circuit are in charged state.When clock Ck1 is lower from height, MOS
Pipe Mb2, Mb6 cut-off, metal-oxide-semiconductor Mb7 conductings, Mb4 conductings；Power supply is by metal-oxide-semiconductor Mb4, Mb7 to node VboostElectricity parasitic over the ground
Capacity charge so that node VboostVoltage increases, metal-oxide-semiconductor Mb1 cut-offs, Mb5, Mb3 conducting；Input signal is lifted by metal-oxide-semiconductor Mb3
Capacitance Cb1 bottom crowns voltage is equal to input voltage V until its valueNi；Since the charge stored on capacitance Cb1 changed in clock CK
There is no discharge loop in journey, the charge being stored thereon remains unchanged, and the voltage of capacitance Cbl top crowns will synchronize rising, directly
It is equal to V to its valueDD+VNi, Bootstrap function is realized, Bootstrap boost pressure circuit is in pressurized state.
It is known that in conjunction with the waveform diagram of Fig. 4.When carrying out charge transmission, Bootstrap boost pressure circuit is in supercharging
The grid of state, the charge transmission MOSFET pipes is high level VDD+VNi, it is in the conduction state that charge transmits MOSFET pipes S；
After the charge end of transmission, Bootstrap boost pressure circuit is in charged state, the grounded-grid of the charge transmission MOSFET pipes S
Level, the charge transmission MOSFET pipes are off state.Wherein, VDDFor supply voltage, VNiMOSFET pipes are transmitted for charge
The source voltage of S.
Fig. 6 is application of the present invention in charge-domain pipelined ADC.It is charge-domain pipelined analog-digital converter as shown in the figure
In 1.5/grade charge-domains sub- level production line circuit specific implementation and the sub- level production line circuit of front stage charge-domain specific connection
Relationship.The sub- level production line circuit of charge-domain is made of the signal processing channel 100p and 100n of fully differential, charge-domain sub- grade flowing water
Line circuit includes 2 insensitive enhanced signal transmitting switches of technological fluctuation (101p and 101n) of the present invention, 2 charges
Memory node (104p and 104n), 2 be connected to prime sub- grade circuit charge-storage node charge storage capacitance (106p and
106n), 6 be connected to the sub- grade circuit charge-storage node of 1.5/grade of this grade charge storage capacitance (107p, 107n, 108p,
108n), 2 comparators, 2 reference charge selection circuits that output control is exported by comparator, 2 are connected to this grade of charge and deposit
Store up the insensitive enhanced signal transmitting switch of technological fluctuation of the present invention of the next stage grade circuit of node.(102p and
102n), 2 charge storage capacitances (109p and 109n) for being connected to next stage grade circuit charge-storage node.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (5)
1. a kind of insensitive enhanced signal transmitting switch of technological fluctuation, it is characterized in that：Including a charge transmission MOSFET pipe
S, a Bootstrap boost pressure circuit, the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the first capacitance C1 and
Two capacitance C2, charge transmission mirror image MOSFET pipes MSR, the first mirror image NMOS tube M1R, the second mirror image NMOS tube M2R, first
Mirror image PMOS tube M3R, current source I1, voltage source V1 and error amplifier AE；
The connection relation of the insensitive enhanced signal transmitting switch of technological fluctuation is：The grid end of first NMOS tube M1 is connected to
Charge node Ni to be transmitted, i.e. charge transmit the source electrode of MOSFET pipes S, are also connected to the control source of Bootstrap boost pressure circuit
End；The source of first NMOS tube M1 is connected to ground level, and the drain terminal of the first NMOS tube M1 is connected to the source of the second NMOS tube M2,
The substrate of first NMOS tube M1 is connected to the error output of the substrate and error amplifier AE of the first mirror image NMOS tube M1R；The
The drain terminal of two NMOS tube M2 is connected to the grid end G of the drain terminal and charge transmission MOSFET pipes S of the first PMOS tube M3, the second NMOS tube
The grid end of M2 is connected to the first bias voltage, the Substrate ground level of the second NMOS tube M2；The grid end of first PMOS tube M3 connects
To the second bias voltage, the source and substrate of the first PMOS tube M3 are connected to the voltage output end of Bootstrap boost pressure circuit
Vboost；The source of first mirror image NMOS tube M1R is connected to ground level, and the drain terminal of the first mirror image NMOS tube M1R is connected to the second mirror
As the source of NMOS tube M2R；The drain terminal of second mirror image NMOS tube M2R is connected to the drain terminal and charge of the first mirror image PMOS tube M3R
The grid end of mirror image MOSFET pipes MSR is transmitted, the grid end of the second mirror image NMOS tube M2R is connected to the first bias voltage, the second mirror image
The Substrate ground level of NMOS tube M2R；The grid end of first mirror image PMOS tube M3R is connected to the second bias voltage, the first mirror image
The source and substrate of PMOS tube M3R is connected to the voltage output end V of Bootstrap boost pressure circuitboost；Charge transmission objectives node
No, i.e. charge transmit the drain electrode of MOSFET pipes S, and control signal Ck1n is met by the second capacitance C2；Charge node Ni to be transmitted is logical
It crosses the first capacitance C1 and meets control signal Ck1；Charge transmits MOSFET pipes S and the substrate of charge transmission mirror image MOSFET pipes MSR is equal
It is connected to ground level；The input end of clock connection control signal Ck1 of Bootstrap boost pressure circuit；The negative voltage of error amplifier AE
Input terminal connects reference voltage V 'R, error amplifier AE positive voltages input terminal simultaneously connect the first mirror image NMOS tube M1R grid
The current input terminal of the source and current source I1 of mirror image MOSFET pipes MSR is transmitted at end, charge；The current output terminal of current source I1 connects
Ground level；The high-voltage output terminal of voltage source V1 connects the drain terminal of charge transmission mirror image MOSFET pipes MSR, the low-voltage of voltage source V1
Output end earth level；Wherein, the control signal Ck1 and control signal Ck1n is high level not overlapping bursts signal.
2. the insensitive enhanced signal transmitting switch of technological fluctuation according to claim 1, it is characterised in that：The NMOS tube
The size ratio of the M1 and mirror image NMOS tube M1R is K, and the NMOS tube M2 is same as the size ratio of mirror image NMOS tube M2R
It is similarly K, the charge transmission MOSFET pipes S and institute for the size ratio of K, the PMOS tube M3 and the mirror image PMOS tube M3R
The size ratio for stating charge transmission mirror image MOSFET pipes MSR is similarly K；Wherein, K is any positive number.
3. the insensitive enhanced signal transmitting switch of technological fluctuation according to claim 1, it is characterised in that：The charge passes
Defeated MOSFET pipes S and charge transmission mirror image MOSFET pipes MSR use deep N-well NMOS tube.
4. the insensitive enhanced signal transmitting switch of technological fluctuation according to claim 1, it is characterised in that：The current source
I1It is designed to be very small, for charge transmission mirror image MOSFET pipes MSR to be biased in the state that will end, and the
The grid voltage V of one mirror image NMOS tube M1RSValue be equal to reference voltage V 'R。
5. the insensitive enhanced signal transmitting switch of technological fluctuation according to claim 1, it is characterised in that：When progress charge
When transmission, Bootstrap boost pressure circuit is in pressurized state, and the grid of the charge transmission MOSFET pipes is high level VDD+VNi,
It is in the conduction state that charge voltage transmits MOSFET pipes；After the charge end of transmission, Bootstrap boost pressure circuit is in charging shape
State, the grounded-grid level of the charge transmission MOSFET pipes, the charge transmission MOSFET pipes are off state；Wherein,
VDDFor supply voltage, VNiFor the source voltage of MOSFET pipes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810627147.1A CN108809286A (en) | 2018-06-19 | 2018-06-19 | The insensitive enhanced signal transmitting switch of technological fluctuation |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810627147.1A CN108809286A (en) | 2018-06-19 | 2018-06-19 | The insensitive enhanced signal transmitting switch of technological fluctuation |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019242396A1 (en) * | 2018-06-19 | 2019-12-26 | 黄山学院 | Low voltage charge transfer circuit using negative voltage and gate voltage bootstrapping |
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| CN101454843A (en) * | 2006-05-31 | 2009-06-10 | 肯奈特公司 | Boosted charge transfer pipeline |
| CN107565955A (en) * | 2017-08-29 | 2018-01-09 | 黄山市祁门新飞电子科技发展有限公司 | Input signal amplitude of oscillation enhanced signal transmission circuit |
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|---|---|---|---|---|
| CN101454843A (en) * | 2006-05-31 | 2009-06-10 | 肯奈特公司 | Boosted charge transfer pipeline |
| CN107565955A (en) * | 2017-08-29 | 2018-01-09 | 黄山市祁门新飞电子科技发展有限公司 | Input signal amplitude of oscillation enhanced signal transmission circuit |
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| HUANG SONGREN等: "A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit", 《JOURNAL OF SEMICONDUCTORS》 * |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019242396A1 (en) * | 2018-06-19 | 2019-12-26 | 黄山学院 | Low voltage charge transfer circuit using negative voltage and gate voltage bootstrapping |
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