WO2019242396A1

WO2019242396A1 - Low voltage charge transfer circuit using negative voltage and gate voltage bootstrapping

Info

Publication number: WO2019242396A1
Application number: PCT/CN2019/083606
Authority: WO
Inventors: 陈珍海; 许媛; 侯丽; 何宁业; 刘琦; 宁仁霞; 吕海江; 魏敬和
Original assignee: 黄山学院
Priority date: 2018-06-19
Filing date: 2019-04-22
Publication date: 2019-12-26
Also published as: CN108809313A

Abstract

A low voltage charge transfer circuit using negative voltage and gate voltage bootstrapping, comprising a charge transfer MOSFET (S), a gate voltage bootstrap boost circuit, a negative voltage transfer MOSFET (B), a voltage switch (K), a negative voltage production circuit, a positive and negative voltage clock production circuit, a first NMOS transistor (M1), a second NMOS transistor (M2), a PMOS transistor (M3), a first capacitor (C1), and a second capacitor (C2). The present circuit overcomes the problem of limited signal swing in existing signal transmission circuits, and can be widely used in various types of signal processing circuits.

Description

Low-voltage charge transfer circuit using negative voltage and gate voltage bootstrap

Technical field

The invention relates to an input signal swing-enhanced charge signal transmission circuit for a charge domain pipelined analog-to-digital converter, and belongs to the technical field of integrated circuits.

technical background

With the continuous development of digital signal processing technology, the digitization and integration of electronic systems is an inevitable trend. However, most of the signals in reality are continuously changing analog quantities, which need to be converted into digital signals through analog-to-digital conversion before they can be input into digital systems for processing and control. Therefore, analog-to-digital converters will be indispensable in the future digital system design Part. In applications such as broadband communications, digital high-definition television, and radar, the system requires an analog-to-digital converter with a very high sampling rate and resolution. The requirements for analog-to-digital converters for portable terminal products in these applications not only require high sampling rates and high resolution, but their power consumption should also be minimized.

At present, an analog-to-digital converter structure capable of achieving both a high sampling rate and a high resolution is a pipelined analog-to-digital converter. The pipeline structure is a multi-stage conversion structure. Each stage uses an analog-to-digital converter with a low-precision basic structure. The input signal is processed step by step. Finally, the results of each stage are combined to generate a high-precision output. The basic idea is to evenly distribute the overall required conversion accuracy to each level, and the conversion results of each level can be combined to get the final conversion result. Because the pipelined analog-to-digital converter can achieve the best compromise in speed, power consumption, and chip area, it can still maintain higher speed and lower power consumption when achieving higher-precision analog-to-digital conversion.

A more mature way to implement a pipelined analog-to-digital converter is a pipelined structure based on switched capacitor technology. The work of the sample-and-hold circuit and each sub-stage circuit in the pipeline analog-to-digital converter based on this technology must also use high-gain and wide-bandwidth operational amplifiers. The speed and processing accuracy of the analog-to-digital converter depends on the speed and accuracy of the negative feedback establishment of the high-gain and ultra-wide bandwidth operational amplifiers used. Therefore, the core of the design of this type of pipelined analog-to-digital converter is the design of the operational amplifier with high gain and ultra-wide bandwidth. The use of these high-gain and wide-bandwidth operational amplifiers has limited the speed and accuracy of switched-capacitor pipelined analog-to-digital converters, and has become the main limiting bottleneck for the performance improvement of these types of analog-to-digital converters. Consumption level increases linearly with increasing speed. The most direct way to reduce the power consumption of pipelined analog-to-digital converters based on switched capacitor circuits is to reduce or eliminate the use of high-gain and ultra-wideband operational amplifiers.

The charge-domain pipelined analog-to-digital converter is an analog-to-digital converter that does not use operational amplifiers with high gain and ultra-wide bandwidth. The structure of the analog-to-digital converter has low power consumption characteristics while achieving high speed and high accuracy. The charge-domain pipelined analog-to-digital converter uses charge-domain signal processing technology. In the circuit, the signal is expressed in the form of a charge packet. The size of the charge packet represents the amount of signals of different sizes. The storage, transmission, addition / subtraction, and comparison of charge packets of different sizes between different storage nodes implement signal processing functions. By using a periodic clock to drive and control the signal processing of charge packets of different sizes between different storage nodes, the analog-to-digital conversion function can be realized.

In the charge-domain pipelined analog-to-digital converter, the charge-stage pipelined sub-level circuits at each level are controlled by the charge transfer switch at the current level, multiple charge physical storage nodes, multiple charge storage elements connected to the charge storage node, multiple comparators, A plurality of reference charge selection circuits controlled by the comparator output results are configured under the control of a control clock. During the working process of the pipeline sub-stages of each level, the functions of charge transfer, addition / subtraction, and comparison and quantification are all performed around the physical storage nodes of the charge of the sub-stages.

Because the implementation of the pipelined analog-to-digital converter includes a large number of digital circuits, the ordinary CMOS process is the best process to implement these large-scale digital circuits. To use digital signal processing technology to achieve ultra-high-speed and ultra-high-precision charge-domain pipelined analog-to-digital converters, one of the core issues is the key steps of charge signal storage and transmission, comparison and quantization, and addition and subtraction operations in existing ordinary CMOS. Can be efficiently and accurately achieved under process conditions. Therefore, in order to realize high-speed and high-precision charge-domain pipelined analog-to-digital converters by means of large-scale digital signal processing technology, it is necessary to provide a high-precision charge signal transmission circuit suitable for ordinary CMOS processes.

For the realization of high-efficiency signal transmission technology, the existing technology is typically patented: US2007 / 0279507A1 enhanced signal transmission circuit, and its typical circuit structure is shown in Figure 1. Signal charge transfer gate V _G S of the MOSFET is connected to the output terminal of the operational amplifier composed of MOS transistors M1, M2 and M3 1 is. Before output of the operational amplifier a charge transfer operation, S is in the OFF state, the charge to be transferred is stored on C _1. Figure 2 is a schematic diagram of the working voltage waveform of the circuit. At t0, Ck1 undergoes a negative step change and Ck1n undergoes a positive step change, which causes the Ni voltage V _{Ni to} change to a low potential and the No voltage V _No to a high potential. Operational amplifier 1 will respond to the change and drive the MOSFET. The voltage of the gate _{G of the} tube S is high, so that S starts to conduct; due to the potential difference, the charge stored on Ni will be transferred to No in the form of electrons, causing V _{Ni to} rise and V _{No to} fall. Operational amplifier 1 will It will also respond to this change and drive the MOSFET S gate's V _G voltage to gradually decrease; at time t1, when V _Ni rises to the voltage V _R , the V _G voltage gradually decreases to the cut-off voltage V _th , S turns off again, and the charge transfers The process ends, where V _{R is} determined by the static operating point of the cascode operational amplifier.

For the signal transmission circuit shown in Figure 1, a prominent problem faced under low voltage conditions is that the input analog signal swings they can handle are limited, and they cannot meet the requirements of universal ADCs for input analog signal differential swings. As shown in Figure 2, one of the biggest differences between charge transfer and voltage transfer is that at the end of charge transfer, a voltage difference V _{DS is} maintained between the source and drain of MOSFET tube S. To ensure the safety and reliability of the charge transfer process, the MOSFET tube This V _DS voltage drop of S is usually set around 20% of the VDD supply voltage. Under the previous 1.8V voltage condition, the V _DS voltage drop of M _S is usually set between 0.35 and 0.4V, which significantly reduces the range of input analog signal swing that the charge-domain ADC pipeline sub-circuit can handle.

The signal nodes mainly related to the input signal swing of the signal transmission circuit shown in FIG. 1 are the gate, drain, source, and substrate terminals of the charge transfer tube MOSFET tube S. In the actual circuit, the source terminal and the drain terminal are two sub-circuits connected to each other. Therefore, the capacitance of the source terminal is 2 ^N times the capacitance of the drain terminal (N is the number of bits of the sub-circuit in which the source terminal is located). The voltage drop at the drain is 2 ^N times the source, so the effective signal swing of the circuit is mainly represented by the voltage drop at the drain, that is, V _A = V _CK1n -V _DS -V _R , and V _CK1n is the height of the control signal CK1n. Level voltage. Under low voltage conditions, the voltage difference of 20% V _DD voltage occupied by V _DS has no room for optimization; V _CK1n voltage is the chip's global reference voltage, and its theoretical maximum value can be V _DD , but in practice its maximum value is still Limited by the voltage at the G terminal, and the maximum value of the voltage at the G terminal can only be the power supply voltage V _DD , which is obviously limited; the minimum voltage of V _R is limited by the S terminal, and the minimum voltage of S is limited by the signal 'ground level' voltage . Therefore, to increase the signal swing V _DD must overcome limit signal "ground level" and the voltage V _R _V CK1n voltage. In the present invention, the V _DD limitation of the V _CK1n voltage is overcome, and the gate voltage bootstrap technology is used to raise the G terminal voltage by a V _DD voltage during the charge transfer. In this way, the upper limit of the V _CK1n voltage can be increased to the V _DD voltage; The V _R voltage signal's ground level is limited. The negative voltage step-down method is used to reduce the minimum value of the S terminal voltage by connecting the substrate voltage of the MOSFET S to the negative voltage. This can significantly reduce the V _R voltage. Lower limit, thereby increasing the signal swing of the BCT.

Summary of the Invention

The object of the present invention is to overcome the shortcomings in the prior art, and to provide a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap, which is a high-precision charge transfer circuit suitable for a common CMOS process.

The technical solution of the low voltage charge transfer circuit using the negative voltage and gate voltage bootstrap according to the present invention is characterized by including a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, and a negative voltage transfer MOSFET tube B. A voltage switch K, a negative voltage generating circuit, a positive and negative voltage clock generating circuit, a first NMOS tube M1, a second NMOS tube M2, a PMOS tube M3, a first capacitor C1 and a second capacitor C2;

The corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage. The substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V _{boost of the} gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer The drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET The drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit The gate terminal of the negative voltage transmission MOSFET B is connected to the output terminal of the positive and negative voltage clock generating circuit; the first and second input terminals of the negative voltage generating circuit are connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n, respectively. The first and second input terminals of the voltage clock generating circuit are respectively connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n; the clock input terminal of the gate voltage bootstrap boost circuit is connected to the charge transfer control signal Ck1; The signal Ck1 and the charge transfer control signal Ck1n are high-level non-overlapping pulse signals, the high level is a positive voltage greater than zero potential, the ground level is zero potential, and the negative potential is less than ground potential. Negative voltage.

The low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap is further characterized in that: when performing charge transfer, the gate voltage bootstrap boost circuit is in a boosted state, and the gate of the charge transfer MOSFET tube is Very high level V _DD + V _Ni , the charge voltage transfer MOSFET tube is in an on state; after the charge transfer is completed, the gate voltage bootstrap boost circuit is in a charging state, and the gate of the charge transfer MOSFET tube is grounded. Level, the charge transfer MOSFET is in an off state; wherein V _DD is the power supply voltage and V _Ni is the source voltage of the MOSFET.

The low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap is further characterized in that: when a charge transfer is performed, the gate of the negative voltage transfer MOSFET B is connected to a high level, and the negative voltage transfer MOSFET B is connected to a high level. In the conducting state, the substrate of the charge transfer MOSFET S is connected to a negative voltage; when the charge transfer is completed, the gate of the negative voltage transfer MOSFET B is connected to a negative voltage, and the negative voltage transfer MOSFET B is turned off. Off state, the substrate ground level of the charge transfer MOSFET S.

The advantage of the present invention is that the low voltage charge transfer circuit using negative voltage and gate voltage bootstrap provided by the present invention is suitable for ordinary CMOS process, which overcomes the problem of limited signal swing in the existing signal transmission circuit and can be widely used. It is applied to the charge domain sub-stage pipeline circuits in the charge domain pipelined analog-to-digital converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an existing signal transmission circuit;

FIG. 2 is a schematic diagram of a working voltage waveform of an existing signal transmission circuit;

3 is a schematic structural diagram of a low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention;

4 is a schematic diagram of a working voltage waveform of a low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention;

5 is a circuit diagram of an implementation of a gate voltage bootstrap boost circuit according to the present invention;

FIG. 6 is an implementation circuit diagram of the negative voltage generating circuit according to the present invention; FIG.

7 (a) is a schematic circuit diagram of an implementation circuit of the positive and negative voltage clock generating circuit according to the present invention;

FIG. 7 (b) is a voltage waveform diagram of the positive and negative voltage clock generating circuit according to the present invention;

FIG. 8 shows the application of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap in a charge-domain pipelined analog-to-digital converter according to the present invention.

detailed description

The present invention will be described in further detail below with reference to the drawings and examples.

FIG. 3 is a schematic structural diagram of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap designed according to the present invention. A negative voltage is added to the substrate of the MOSFET tube S in the signal transmission circuit shown in FIG. 1. The generating circuit and the negative voltage transmission circuit add a gate voltage bootstrap booster circuit between the source of the MOSFET S and the power supply VDD. The low-voltage charge transfer circuit using a negative voltage and gate voltage bootstrap includes a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, a negative voltage transfer MOSFET tube B, a voltage switch K, and a negative voltage generation. Circuit, a positive and negative voltage clock generating circuit, a first NMOS tube M1, a second NMOS tube M2, a PMOS tube M3, a first capacitor C1 and a second capacitor C2.

The corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage. The substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V _{boost of the} gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer The drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET The drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit The gate terminal of the negative voltage transmission MOSFET B is connected to the output terminal of the positive and negative voltage clock generating circuit; the first and second input terminals of the negative voltage generating circuit are connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n, respectively. The first and second input terminals of the voltage clock generating circuit are respectively connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n; the clock input terminal of the gate voltage bootstrap boost circuit is connected to the charge transfer control signal Ck1.

FIG. 4 is a schematic diagram of a working voltage waveform of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention. By using the gate bootstrap boost technology, the voltage at the G terminal is raised by a V _DD voltage during the charge transfer, so that the upper limit of the V _CK1n voltage can be increased to the V _DD voltage, thereby achieving the purpose of increasing the BCT signal swing. The voltage of V _CK1n is increased to V ' _CK1n . The theoretical upper limit can be increased to V _DD . It can be seen that the signal swing V' _A of the BCT circuit has increased (V ' _CK1n -V _CK1n ). , V _R voltage is reduced to V ' _R , and the minimum value of the S terminal voltage is negative voltage. It can be seen that the signal swing V _A of the BCT circuit increases the difference voltage between V _R -V' _R. At the same time, the negative voltage and After the gate voltage bootstrap boost technology, the signal swing of the output end of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap according to the present invention has been increased by (V ' _CK1n -V _CK1n ) + (V _R -V ' _R ).

FIG. 5 shows a schematic diagram of a gate voltage bootstrap boost circuit that can be used in the present invention. The principle is as follows: When the clock Ck1 is at a high level, the MOS tubes Mb2 and Mb6 are turned on, the MOS tube Mb7 is turned off and Mb4 is turned on, so that the MOS tube Mb1 is also turned on; the circuit charges the capacitor Cb1 through the MOS tubes Mb1 and Mb2, so that The voltage across Cb1 is close to the power supply voltage V _DD , so the capacity of V _DD * Cb1 is stored on the capacitor Cb1, and the gate voltage bootstrap boost circuit is in a charging state. When the clock Ck1 changes from high to low, the MOS transistors Mb2 and Mb6 are turned off, the MOS transistors Mb7 are turned on, and Mb4 is turned on; the power source charges the parasitic capacitance of the node V _boost to ground through the MOS tubes Mb4 and Mb7, so that the node V _boost The voltage rises, MOS tube Mb1 is turned off, Mb5 and Mb3 are turned on; the input signal raises the voltage of the lower plate of capacitor Cb1 through MOS tube Mb3 until its value is equal to the input voltage V _Ni ; because the charge stored on capacitor Cb1 is in the process of clock CK change There is no discharge circuit, the charge stored on it remains unchanged, and the voltage of the plate on the capacitor Cb1 rises synchronously until its value is equal to V _DD + V _Ni , which realizes the gate voltage bootstrap function and the gate voltage bootstrap boost The circuit is pressurized.

It can be known in combination with the waveform diagram of FIG. 4. When charge transfer is performed, the gate voltage bootstrap booster circuit is in a boosted state, the gate of the charge transfer MOSFET tube is at a high level V _DD + V _Ni , and the charge transfer MOSFET tube S is in an on state; when the charge transfer ends Then, the gate voltage bootstrap boost circuit is in a charging state, the gate of the charge transfer MOSFET tube S is grounded, and the charge transfer MOSFET tube is in an off state. Among them, V _DD is the power supply voltage, and V _Ni is the source voltage of the charge transfer MOSFET S.

FIG. 6 is a schematic diagram of a negative voltage generating circuit that can be used in the present invention to provide a negative bias voltage for the substrate of the charge transfer MOSFET S of FIG. 3. This circuit uses similar capacitor charging and discharging and MOS switch on and off characteristics to achieve negative voltage output. The detailed circuit working principle can refer to US patent US5831844, which will not be explained here.

The negative voltage output by the negative voltage generating circuit in the present invention is transmitted through a negative voltage transmitting MOSFET tube B. When the input signal swing enhanced signal transmission circuit starts to perform charge transfer, the gate of the negative voltage transfer MOSFET B is connected to a high level, the negative voltage transfer MOSFET B is in an on state, and the liner of the charge transfer MOSFET S is lined up. The negative voltage is connected to the bottom; after the input signal swing-enhanced signal transmission circuit finishes the charge transmission, the gate of the negative voltage transmission MOSFET B is connected to a negative voltage, the negative voltage transmission MOSFET B is in an off state, and the charge transmission MOSFET tube The substrate of S is grounded under the control of the charge transfer control signal Ck1.

The present invention uses a positive and negative voltage clock to control the signal transmission of the negative voltage transmission MOSFET tube B. The main reason is that when the source terminal and the substrate of the negative voltage transmission MOSFET tube B are both negative voltage, the negative voltage transmission MOSFET tube B is turned off. Off, the voltage difference between the gate terminal and the source terminal of the negative voltage transmission MOSFET B must be less than the threshold voltage (V _thB ) that is turned on. If a common voltage clock is used to control the gate terminal of the negative voltage transmission MOSFET B, when the clock level is low, the gate and source voltages of the negative voltage transmission MOSFET B are greater than the threshold voltage (V _thB ) that is turned on. As a result, the negative voltage transmitting MOSFET B cannot be turned off. Therefore, the gate control clock of the negative voltage transmitting MOSFET B must be controlled by using a positive and negative voltage clock.

In the present invention, the high level is a positive voltage greater than zero potential; the ground level is zero voltage; the negative potential is a negative voltage less than the ground level; the charge transfer control signal Ck1 and the charge transfer control signal Ck1n are High-level non-overlapping pulse signals.

Fig. 7 (a) and Fig. 7 (b) show a circuit principle and a working voltage waveform diagram of a positive-negative voltage clock generating circuit shown in Fig. 3 which can be used in the present invention. FIG. 7 (a) is a circuit principle of the positive and negative voltage clock generating circuit, and FIG. 7 (b) is a voltage waveform of the input charge transfer control signal Ck1n and the output signal Ck1nout obtained by simulation when the positive and negative voltage clock generating circuit operates. Illustration. This circuit uses similar characteristics of capacitor charging and discharging and digital flip-flop circuits to achieve positive and negative voltage clock output. For detailed circuit working principles, please refer to Chinese patent ZL201010175033.1 (a negative voltage effective transmission circuit suitable for standard CMOS technology). The principle is not explained here.

FIG. 8 shows the application of the present invention in a charge domain pipeline ADC. The figure shows the specific implementation of the 1.5-bit / stage charge-domain sub-stage pipeline circuit in the charge-domain pipelined analog-to-digital converter and the specific connection relationship between the charge-domain sub-stage pipeline circuits in the front and back stages. The charge domain sub-stage pipeline circuit is composed of fully differential

signal processing channels

100p and 100n. The charge domain sub-stage pipeline circuit includes two low-voltage charge transfer circuits (101p and 101n) using negative voltage and gate voltage bootstrap according to the present invention. ), 2 charge storage nodes (104p and 104n), 2 charge storage capacitors (106p and 106n) connected to the charge storage node of the previous-stage sub-circuit, and 6 charge storage nodes connected to the 1.5-bit / level sub-circuit of this stage The node's charge storage capacitors (107p, 107n, 108p, 108n), two comparators, two reference charge selection circuits controlled by the output of the comparator, and two sub-level circuits connected to the charge storage node of this level According to the present invention, a low-voltage charge transfer circuit (102p and 102n) using a negative voltage and a gate voltage bootstrap, two charge storage capacitors (109p and 109n) connected to a charge storage node of a next-stage sub-circuit.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall be included in the protection of the present invention. Within range.

Claims

A low-voltage charge transfer circuit using a negative voltage and gate voltage bootstrap is characterized in that it includes a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, a negative voltage transfer MOSFET tube B, and a voltage switch K A negative voltage generating circuit, a positive and negative voltage clock generating circuit, a first NMOS tube M1, a second NMOS tube M2, a PMOS tube M3, a first capacitor C1 and a second capacitor C2;

The corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage. The substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer The drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET The drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit The gate terminal of the negative voltage transmission MOSFET B is connected to the output terminal of the positive and negative voltage clock generating circuit; the first and second input terminals of the negative voltage generating circuit are connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n, respectively. The first and second input terminals of the voltage clock generating circuit are respectively connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n; the clock input terminal of the gate voltage bootstrap boost circuit is connected to the charge transfer control signal Ck1;

The charge transfer control signal Ck1 and the charge transfer control signal Ck1n are high-level non-overlapping pulse signals; the high level is a positive voltage greater than zero potential; the ground level is zero potential; the negative potential Is a negative voltage less than ground.
The low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to claim 1, characterized in that: when the charge transfer is performed, the gate voltage bootstrap boost circuit is in a boosted state, and the charge transfer MOSFET The gate of the tube S is at a high level V DD + V Ni , and the charge voltage transfer MOSFET tube S is in an on state; when the charge transfer ends, the gate voltage bootstrap boost circuit is in a charging state, and the charge transfer MOSFET tube The gate level of S, and the charge transfer MOSFET S is in an off state;

Among them, V DD is the power supply voltage, and V Ni is the source voltage of the MOSFET.
The input signal swing-enhanced signal transmission circuit according to claim 1, wherein: when a charge is transmitted, a gate of the negative voltage transmission MOSFET B is connected to a high level, and the negative voltage transmission MOSFET B is in a conductive state. In the on state, the substrate of the charge transfer MOSFET S is connected to a negative voltage; when the charge transfer is completed, the gate of the negative voltage transfer MOSFET B is connected to a negative voltage, and the negative voltage transfer MOSFET B is in an off state. The ground level of the substrate of the charge transfer MOSFET S.