WO2019242396A1 - Circuit de transfert de charge basse tension utilisant un amorçage de tension négative et de tension de grille - Google Patents

Circuit de transfert de charge basse tension utilisant un amorçage de tension négative et de tension de grille Download PDF

Info

Publication number
WO2019242396A1
WO2019242396A1 PCT/CN2019/083606 CN2019083606W WO2019242396A1 WO 2019242396 A1 WO2019242396 A1 WO 2019242396A1 CN 2019083606 W CN2019083606 W CN 2019083606W WO 2019242396 A1 WO2019242396 A1 WO 2019242396A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
charge transfer
gate
mosfet
negative voltage
Prior art date
Application number
PCT/CN2019/083606
Other languages
English (en)
Chinese (zh)
Inventor
陈珍海
许媛
侯丽
何宁业
刘琦
宁仁霞
吕海江
魏敬和
Original Assignee
黄山学院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 黄山学院 filed Critical 黄山学院
Publication of WO2019242396A1 publication Critical patent/WO2019242396A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values

Definitions

  • the invention relates to an input signal swing-enhanced charge signal transmission circuit for a charge domain pipelined analog-to-digital converter, and belongs to the technical field of integrated circuits.
  • analog-to-digital converters will be indispensable in the future digital system design Part.
  • applications such as broadband communications, digital high-definition television, and radar, the system requires an analog-to-digital converter with a very high sampling rate and resolution.
  • the requirements for analog-to-digital converters for portable terminal products in these applications not only require high sampling rates and high resolution, but their power consumption should also be minimized.
  • an analog-to-digital converter structure capable of achieving both a high sampling rate and a high resolution is a pipelined analog-to-digital converter.
  • the pipeline structure is a multi-stage conversion structure. Each stage uses an analog-to-digital converter with a low-precision basic structure. The input signal is processed step by step. Finally, the results of each stage are combined to generate a high-precision output.
  • the basic idea is to evenly distribute the overall required conversion accuracy to each level, and the conversion results of each level can be combined to get the final conversion result. Because the pipelined analog-to-digital converter can achieve the best compromise in speed, power consumption, and chip area, it can still maintain higher speed and lower power consumption when achieving higher-precision analog-to-digital conversion.
  • a more mature way to implement a pipelined analog-to-digital converter is a pipelined structure based on switched capacitor technology.
  • the work of the sample-and-hold circuit and each sub-stage circuit in the pipeline analog-to-digital converter based on this technology must also use high-gain and wide-bandwidth operational amplifiers.
  • the speed and processing accuracy of the analog-to-digital converter depends on the speed and accuracy of the negative feedback establishment of the high-gain and ultra-wide bandwidth operational amplifiers used. Therefore, the core of the design of this type of pipelined analog-to-digital converter is the design of the operational amplifier with high gain and ultra-wide bandwidth.
  • the charge-domain pipelined analog-to-digital converter is an analog-to-digital converter that does not use operational amplifiers with high gain and ultra-wide bandwidth.
  • the structure of the analog-to-digital converter has low power consumption characteristics while achieving high speed and high accuracy.
  • the charge-domain pipelined analog-to-digital converter uses charge-domain signal processing technology.
  • the signal is expressed in the form of a charge packet.
  • the size of the charge packet represents the amount of signals of different sizes.
  • the storage, transmission, addition / subtraction, and comparison of charge packets of different sizes between different storage nodes implement signal processing functions. By using a periodic clock to drive and control the signal processing of charge packets of different sizes between different storage nodes, the analog-to-digital conversion function can be realized.
  • the charge-stage pipelined sub-level circuits at each level are controlled by the charge transfer switch at the current level, multiple charge physical storage nodes, multiple charge storage elements connected to the charge storage node, multiple comparators, A plurality of reference charge selection circuits controlled by the comparator output results are configured under the control of a control clock.
  • the functions of charge transfer, addition / subtraction, and comparison and quantification are all performed around the physical storage nodes of the charge of the sub-stages.
  • the ordinary CMOS process is the best process to implement these large-scale digital circuits.
  • digital signal processing technology to achieve ultra-high-speed and ultra-high-precision charge-domain pipelined analog-to-digital converters, one of the core issues is the key steps of charge signal storage and transmission, comparison and quantization, and addition and subtraction operations in existing ordinary CMOS. Can be efficiently and accurately achieved under process conditions. Therefore, in order to realize high-speed and high-precision charge-domain pipelined analog-to-digital converters by means of large-scale digital signal processing technology, it is necessary to provide a high-precision charge signal transmission circuit suitable for ordinary CMOS processes.
  • FIG. 1 For the realization of high-efficiency signal transmission technology, the existing technology is typically patented: US2007 / 0279507A1 enhanced signal transmission circuit, and its typical circuit structure is shown in Figure 1.
  • Signal charge transfer gate V G S of the MOSFET is connected to the output terminal of the operational amplifier composed of MOS transistors M1, M2 and M3 1 is. Before output of the operational amplifier a charge transfer operation, S is in the OFF state, the charge to be transferred is stored on C 1.
  • Figure 2 is a schematic diagram of the working voltage waveform of the circuit. At t0, Ck1 undergoes a negative step change and Ck1n undergoes a positive step change, which causes the Ni voltage V Ni to change to a low potential and the No voltage V No to a high potential.
  • Operational amplifier 1 will respond to the change and drive the MOSFET.
  • the voltage of the gate G of the tube S is high, so that S starts to conduct; due to the potential difference, the charge stored on Ni will be transferred to No in the form of electrons, causing V Ni to rise and V No to fall.
  • Operational amplifier 1 will It will also respond to this change and drive the MOSFET S gate's V G voltage to gradually decrease; at time t1, when V Ni rises to the voltage V R , the V G voltage gradually decreases to the cut-off voltage V th , S turns off again, and the charge transfers The process ends, where V R is determined by the static operating point of the cascode operational amplifier.
  • the signal nodes mainly related to the input signal swing of the signal transmission circuit shown in FIG. 1 are the gate, drain, source, and substrate terminals of the charge transfer tube MOSFET tube S.
  • the source terminal and the drain terminal are two sub-circuits connected to each other. Therefore, the capacitance of the source terminal is 2 N times the capacitance of the drain terminal (N is the number of bits of the sub-circuit in which the source terminal is located).
  • V CK1n voltage is the chip's global reference voltage, and its theoretical maximum value can be V DD , but in practice its maximum value is still Limited by the voltage at the G terminal, and the maximum value of the voltage at the G terminal can only be the power supply voltage V DD , which is obviously limited; the minimum voltage of V R is limited by the S terminal, and the minimum voltage of S is limited by the signal 'ground level' voltage . Therefore, to increase the signal swing V DD must overcome limit signal "ground level" and the voltage V R V CK1n voltage.
  • the V DD limitation of the V CK1n voltage is overcome, and the gate voltage bootstrap technology is used to raise the G terminal voltage by a V DD voltage during the charge transfer.
  • the upper limit of the V CK1n voltage can be increased to the V DD voltage;
  • the V R voltage signal's ground level is limited.
  • the negative voltage step-down method is used to reduce the minimum value of the S terminal voltage by connecting the substrate voltage of the MOSFET S to the negative voltage. This can significantly reduce the V R voltage. Lower limit, thereby increasing the signal swing of the BCT.
  • the object of the present invention is to overcome the shortcomings in the prior art, and to provide a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap, which is a high-precision charge transfer circuit suitable for a common CMOS process.
  • the technical solution of the low voltage charge transfer circuit using the negative voltage and gate voltage bootstrap according to the present invention is characterized by including a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, and a negative voltage transfer MOSFET tube B.
  • the corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage.
  • the substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer
  • the drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET
  • the drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit
  • the first and second input terminals of the voltage clock generating circuit are respectively connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n; the clock input terminal of the gate voltage bootstrap boost circuit is connected to the charge transfer control signal Ck1;
  • the signal Ck1 and the charge transfer control signal Ck1n are high-level non-overlapping pulse signals, the high level is a positive voltage greater than zero potential, the ground level is zero potential, and the negative potential is less than ground potential. Negative voltage.
  • the low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap is further characterized in that: when performing charge transfer, the gate voltage bootstrap boost circuit is in a boosted state, and the gate of the charge transfer MOSFET tube is Very high level V DD + V Ni , the charge voltage transfer MOSFET tube is in an on state; after the charge transfer is completed, the gate voltage bootstrap boost circuit is in a charging state, and the gate of the charge transfer MOSFET tube is grounded. Level, the charge transfer MOSFET is in an off state; wherein V DD is the power supply voltage and V Ni is the source voltage of the MOSFET.
  • the low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap is further characterized in that: when a charge transfer is performed, the gate of the negative voltage transfer MOSFET B is connected to a high level, and the negative voltage transfer MOSFET B is connected to a high level. In the conducting state, the substrate of the charge transfer MOSFET S is connected to a negative voltage; when the charge transfer is completed, the gate of the negative voltage transfer MOSFET B is connected to a negative voltage, and the negative voltage transfer MOSFET B is turned off. Off state, the substrate ground level of the charge transfer MOSFET S.
  • the advantage of the present invention is that the low voltage charge transfer circuit using negative voltage and gate voltage bootstrap provided by the present invention is suitable for ordinary CMOS process, which overcomes the problem of limited signal swing in the existing signal transmission circuit and can be widely used. It is applied to the charge domain sub-stage pipeline circuits in the charge domain pipelined analog-to-digital converter.
  • FIG. 1 is a schematic diagram of an existing signal transmission circuit
  • FIG. 2 is a schematic diagram of a working voltage waveform of an existing signal transmission circuit
  • FIG. 3 is a schematic structural diagram of a low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention
  • FIG. 4 is a schematic diagram of a working voltage waveform of a low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention
  • FIG. 5 is a circuit diagram of an implementation of a gate voltage bootstrap boost circuit according to the present invention.
  • FIG. 6 is an implementation circuit diagram of the negative voltage generating circuit according to the present invention.
  • FIG. 7 (a) is a schematic circuit diagram of an implementation circuit of the positive and negative voltage clock generating circuit according to the present invention.
  • FIG. 7 (b) is a voltage waveform diagram of the positive and negative voltage clock generating circuit according to the present invention.
  • FIG. 8 shows the application of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap in a charge-domain pipelined analog-to-digital converter according to the present invention.
  • FIG. 3 is a schematic structural diagram of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap designed according to the present invention.
  • a negative voltage is added to the substrate of the MOSFET tube S in the signal transmission circuit shown in FIG. 1.
  • the generating circuit and the negative voltage transmission circuit add a gate voltage bootstrap booster circuit between the source of the MOSFET S and the power supply VDD.
  • the low-voltage charge transfer circuit using a negative voltage and gate voltage bootstrap includes a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, a negative voltage transfer MOSFET tube B, a voltage switch K, and a negative voltage generation. Circuit, a positive and negative voltage clock generating circuit, a first NMOS tube M1, a second NMOS tube M2, a PMOS tube M3, a first capacitor C1 and a second capacitor C2.
  • the corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage.
  • the substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer
  • the drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET
  • the drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit
  • FIG. 4 is a schematic diagram of a working voltage waveform of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention.
  • the gate bootstrap boost technology By using the gate bootstrap boost technology, the voltage at the G terminal is raised by a V DD voltage during the charge transfer, so that the upper limit of the V CK1n voltage can be increased to the V DD voltage, thereby achieving the purpose of increasing the BCT signal swing.
  • the voltage of V CK1n is increased to V ' CK1n .
  • the theoretical upper limit can be increased to V DD . It can be seen that the signal swing V' A of the BCT circuit has increased (V ' CK1n -V CK1n ).
  • V R voltage is reduced to V ' R
  • the minimum value of the S terminal voltage is negative voltage. It can be seen that the signal swing V A of the BCT circuit increases the difference voltage between V R -V' R. At the same time, the negative voltage and After the gate voltage bootstrap boost technology, the signal swing of the output end of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap according to the present invention has been increased by (V ' CK1n -V CK1n ) + (V R -V ' R ).
  • FIG. 5 shows a schematic diagram of a gate voltage bootstrap boost circuit that can be used in the present invention.
  • the principle is as follows: When the clock Ck1 is at a high level, the MOS tubes Mb2 and Mb6 are turned on, the MOS tube Mb7 is turned off and Mb4 is turned on, so that the MOS tube Mb1 is also turned on; the circuit charges the capacitor Cb1 through the MOS tubes Mb1 and Mb2, so that The voltage across Cb1 is close to the power supply voltage V DD , so the capacity of V DD * Cb1 is stored on the capacitor Cb1, and the gate voltage bootstrap boost circuit is in a charging state.
  • the gate voltage bootstrap booster circuit When charge transfer is performed, the gate voltage bootstrap booster circuit is in a boosted state, the gate of the charge transfer MOSFET tube is at a high level V DD + V Ni , and the charge transfer MOSFET tube S is in an on state; when the charge transfer ends Then, the gate voltage bootstrap boost circuit is in a charging state, the gate of the charge transfer MOSFET tube S is grounded, and the charge transfer MOSFET tube is in an off state.
  • V DD is the power supply voltage
  • V Ni is the source voltage of the charge transfer MOSFET S.
  • FIG. 6 is a schematic diagram of a negative voltage generating circuit that can be used in the present invention to provide a negative bias voltage for the substrate of the charge transfer MOSFET S of FIG. 3.
  • This circuit uses similar capacitor charging and discharging and MOS switch on and off characteristics to achieve negative voltage output.
  • the detailed circuit working principle can refer to US patent US5831844, which will not be explained here.
  • the negative voltage output by the negative voltage generating circuit in the present invention is transmitted through a negative voltage transmitting MOSFET tube B.
  • the gate of the negative voltage transfer MOSFET B is connected to a high level, the negative voltage transfer MOSFET B is in an on state, and the liner of the charge transfer MOSFET S is lined up.
  • the negative voltage is connected to the bottom; after the input signal swing-enhanced signal transmission circuit finishes the charge transmission, the gate of the negative voltage transmission MOSFET B is connected to a negative voltage, the negative voltage transmission MOSFET B is in an off state, and the charge transmission MOSFET tube
  • the substrate of S is grounded under the control of the charge transfer control signal Ck1.
  • the present invention uses a positive and negative voltage clock to control the signal transmission of the negative voltage transmission MOSFET tube B.
  • the main reason is that when the source terminal and the substrate of the negative voltage transmission MOSFET tube B are both negative voltage, the negative voltage transmission MOSFET tube B is turned off. Off, the voltage difference between the gate terminal and the source terminal of the negative voltage transmission MOSFET B must be less than the threshold voltage (V thB ) that is turned on. If a common voltage clock is used to control the gate terminal of the negative voltage transmission MOSFET B, when the clock level is low, the gate and source voltages of the negative voltage transmission MOSFET B are greater than the threshold voltage (V thB ) that is turned on. As a result, the negative voltage transmitting MOSFET B cannot be turned off. Therefore, the gate control clock of the negative voltage transmitting MOSFET B must be controlled by using a positive and negative voltage clock.
  • the high level is a positive voltage greater than zero potential; the ground level is zero voltage; the negative potential is a negative voltage less than the ground level; the charge transfer control signal Ck1 and the charge transfer control signal Ck1n are High-level non-overlapping pulse signals.
  • FIG. 7 (a) and Fig. 7 (b) show a circuit principle and a working voltage waveform diagram of a positive-negative voltage clock generating circuit shown in Fig. 3 which can be used in the present invention.
  • FIG. 7 (a) is a circuit principle of the positive and negative voltage clock generating circuit
  • FIG. 7 (b) is a voltage waveform of the input charge transfer control signal Ck1n and the output signal Ck1nout obtained by simulation when the positive and negative voltage clock generating circuit operates. Illustration.
  • This circuit uses similar characteristics of capacitor charging and discharging and digital flip-flop circuits to achieve positive and negative voltage clock output.
  • Chinese patent ZL201010175033.1 a negative voltage effective transmission circuit suitable for standard CMOS technology. The principle is not explained here.
  • FIG. 8 shows the application of the present invention in a charge domain pipeline ADC.
  • the figure shows the specific implementation of the 1.5-bit / stage charge-domain sub-stage pipeline circuit in the charge-domain pipelined analog-to-digital converter and the specific connection relationship between the charge-domain sub-stage pipeline circuits in the front and back stages.
  • the charge domain sub-stage pipeline circuit is composed of fully differential signal processing channels 100p and 100n.
  • the charge domain sub-stage pipeline circuit includes two low-voltage charge transfer circuits (101p and 101n) using negative voltage and gate voltage bootstrap according to the present invention.
  • a low-voltage charge transfer circuit (102p and 102n) using a negative voltage and a gate voltage bootstrap, two charge storage capacitors (109p and 109n) connected to a charge storage node of a next-stage sub-circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un circuit de transfert de charge basse tension utilisant un amorçage de tension négative et de tension de grille comprenant un MOSFET de transfert de charge (S), un circuit survolteur d'amorçage de tension de grille, un MOSFET de transfert de tension négative (B), un commutateur de tension (K), un circuit de production de tension négative, un circuit de production d'horloge à tension positive et négative, un premier transistor NMOS (M1), un second transistor NMOS (M2), un transistor PMOS (M3), un premier condensateur (C1) et un second condensateur (C2). Le présent circuit surmonte le problème de la dynamique de signal limitée dans des circuits de transmission de signaux existants et peut être largement utilisé dans divers types de circuits de traitement de signaux.
PCT/CN2019/083606 2018-06-19 2019-04-22 Circuit de transfert de charge basse tension utilisant un amorçage de tension négative et de tension de grille WO2019242396A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810627194.6 2018-06-19
CN201810627194.6A CN108809313A (zh) 2018-06-19 2018-06-19 采用负电压和栅压自举的低电压电荷传输电路

Publications (1)

Publication Number Publication Date
WO2019242396A1 true WO2019242396A1 (fr) 2019-12-26

Family

ID=64083390

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/083606 WO2019242396A1 (fr) 2018-06-19 2019-04-22 Circuit de transfert de charge basse tension utilisant un amorçage de tension négative et de tension de grille

Country Status (2)

Country Link
CN (1) CN108809313A (fr)
WO (1) WO2019242396A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108809313A (zh) * 2018-06-19 2018-11-13 黄山学院 采用负电压和栅压自举的低电压电荷传输电路

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201887738U (zh) * 2010-10-09 2011-06-29 中国电子科技集团公司第五十八研究所 一种高线性度cmos自举采样开关
CN106505979A (zh) * 2016-11-09 2017-03-15 电子科技大学 一种栅压自举开关电路
CN107565955A (zh) * 2017-08-29 2018-01-09 黄山市祁门新飞电子科技发展有限公司 输入信号摆幅增强型信号传输电路
CN108766500A (zh) * 2018-06-19 2018-11-06 广州领知信息技术有限公司 高速增压型信号传输开关
CN108809286A (zh) * 2018-06-19 2018-11-13 苏州睿度智能科技有限公司 工艺波动不敏感增强型信号传输开关
CN108809313A (zh) * 2018-06-19 2018-11-13 黄山学院 采用负电压和栅压自举的低电压电荷传输电路
CN108806757A (zh) * 2018-06-19 2018-11-13 广州领知信息技术有限公司 高速增压型信号采样传输开关
CN108809312A (zh) * 2018-06-19 2018-11-13 黄山学院 低电压电荷域流水线adc子级电路
CN108847846A (zh) * 2018-06-19 2018-11-20 黄山学院 低电压大摆幅电荷传输电路

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201887738U (zh) * 2010-10-09 2011-06-29 中国电子科技集团公司第五十八研究所 一种高线性度cmos自举采样开关
CN106505979A (zh) * 2016-11-09 2017-03-15 电子科技大学 一种栅压自举开关电路
CN107565955A (zh) * 2017-08-29 2018-01-09 黄山市祁门新飞电子科技发展有限公司 输入信号摆幅增强型信号传输电路
CN108766500A (zh) * 2018-06-19 2018-11-06 广州领知信息技术有限公司 高速增压型信号传输开关
CN108809286A (zh) * 2018-06-19 2018-11-13 苏州睿度智能科技有限公司 工艺波动不敏感增强型信号传输开关
CN108809313A (zh) * 2018-06-19 2018-11-13 黄山学院 采用负电压和栅压自举的低电压电荷传输电路
CN108806757A (zh) * 2018-06-19 2018-11-13 广州领知信息技术有限公司 高速增压型信号采样传输开关
CN108809312A (zh) * 2018-06-19 2018-11-13 黄山学院 低电压电荷域流水线adc子级电路
CN108847846A (zh) * 2018-06-19 2018-11-20 黄山学院 低电压大摆幅电荷传输电路

Also Published As

Publication number Publication date
CN108809313A (zh) 2018-11-13

Similar Documents

Publication Publication Date Title
Li et al. A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications
KR101888103B1 (ko) 분산형 부트스트랩 스위치
US8581769B2 (en) Multiplying digital-to-analog converter configured to maintain impedance balancing
US8610422B2 (en) Dynamic biasing of an amplifier using capacitive driving of internal bias voltages
CN107565955B (zh) 输入信号摆幅增强型信号传输电路
CN104113341A (zh) 一种12位中等速率逐次逼近型模数转换器
CN104124971A (zh) 基于逐次逼近原理的两级流水线型模数转换器
CN112564709B (zh) 一种基于误差反馈式的噪声整形逐次逼近模数转换器
CN105071806A (zh) 应用于高速模数转换器的高线性度输入信号缓冲器
CN112671382B (zh) 一种栅压自举开关电路
US20080180136A1 (en) Pre-charge sample-and-hold circuit
WO2019242396A1 (fr) Circuit de transfert de charge basse tension utilisant un amorçage de tension négative et de tension de grille
CN110690884A (zh) 一种采用cmos传输门的栅压自举开关电路
CN110943726A (zh) 一种多通道多级并行超高速采样保持电路
CN111585518B (zh) 适用于噪声整形结构adc的高速低功耗差分动态运算放大器
US9106240B1 (en) Multiplying digital-to-analog converter and pipeline analog-to-digital converter using the same
CN112134566B (zh) 应用于sar adc的动态逻辑控制电路
TWI726822B (zh) 訊號轉換裝置
Ha et al. A study of 10-bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology
CN107800435B (zh) 一种电容阵列寄生效应的补偿电路和抵消方法
CN108847846A (zh) 低电压大摆幅电荷传输电路
CN202261240U (zh) 用于电荷耦合流水线adc的电荷传输电路
CN108766500A (zh) 高速增压型信号传输开关
CN219181502U (zh) 流水线型模数转换器
CN108809286A (zh) 工艺波动不敏感增强型信号传输开关

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19822683

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19822683

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19822683

Country of ref document: EP

Kind code of ref document: A1