CN107395201A - It is a kind of to be combined the streamline successive approximation analog to digital C quantified with time domain based on voltage domain - Google Patents

Abstract

The invention relates to a pipeline successive approximation ADC based on combined quantization of voltage domain and time domain, which belongs to the technical field of analog integrated circuits. A two-stage pipeline structure is adopted. The input terminal of the first-stage ADC is connected to the input signal, and the first output terminal outputs the first-stage quantization result obtained after quantizing the upper bits of the input signal, and the second output terminal outputs the input signal that has not been quantized. The processed part is input to the input terminal of the second-stage ADC after passing through the buffer, and the output terminal of the second-stage ADC outputs the quantized second-stage quantization result, and the first-stage quantization result and the second-stage quantization result are used as the final output codeword The high-order and low-order bits are coded sequentially to obtain the final quantization result. The second-stage ADC adopts the SAR analog-to-digital converter with the combination of voltage domain and time domain quantization, which can realize the output code word of two bits per cycle, which effectively improves the conversion rate; because the quantization of the time domain is more accurate at low voltage, a A unit gain buffer is used to realize the conversion between the two stages, which improves the linearity and effectively improves the circuit precision.

Description

A Pipelined Successive Approximation ADC Based on Combined Quantization in Voltage Domain and Time Domain

technical field

The invention belongs to the technical field of analog integrated circuits, and in particular relates to a pipeline successive approximation analog-to-digital converter which adopts voltage domain and time domain combined quantization.

Background technique

In recent years, with the rapid development of computer, communication and multimedia technologies, the degree of digitalization in the global high-tech field has continued to deepen. In many electronic systems, analog-to-digital converters are needed to convert analog signals such as voltage and current into digital codes before processing. , to take advantage of the powerful data processing capabilities of large scale digital integrated circuits.

With the innovation of semiconductor manufacturing process and the drop of chip power supply voltage, the design of high-performance analog-to-digital converters faces new challenges. Traditional successive approximation SAR ADCs and pipelined ADCs are difficult to achieve high conversion rate, high precision and low power consumption performance indicators, and often need to sacrifice certain indicators to meet other requirements.

A traditional SAR ADC consists of a comparator, a digital-to-analog converter and digital control logic. The digital control logic sequentially determines the value of each bit of the output code according to the output result of the comparator. Using the binary algorithm method of successive approximation requires N quantization periods for each conversion, and after N comparisons, the conversion rate is greatly limited. In addition, the traditional SAR analog-to-digital converter only uses the voltage comparison result output by the comparator and ignores other information that the comparator can provide, so that each quantization can only be performed in units, which also severely limits the SAR analog-to-digital converter. The slew rate of the converter.

The traditional pipelined A/D converter is a multi-stage converter, each stage has a sample-and-hold circuit, and an inter-stage amplifier to amplify the quantization margin of this stage, and then output it to the subsequent stage for further quantization. The sample-and-hold circuit makes it only necessary for each pipeline stage to complete quantization and residual amplification in one cycle, without the need for the entire converter to complete the conversion at one time, so the conversion rate will not decrease with the increase of the number of stages, but due to the need to use To an interstage amplifier with precise gain, the overall power consumption is relatively large, especially under the advanced technology of low-voltage short channel, it is more difficult to realize a high-gain operational amplifier for designing a feedback network with stable gain.

Contents of the invention

Aiming at the deficiencies of the traditional analog-to-digital converter circuit structure in terms of precision, conversion rate and power consumption, the present invention provides a pipeline successive approximation ADC based on the combination of voltage domain and time domain quantization, using a two-stage pipeline structure, the second The stage is implemented by a SAR analog-to-digital converter combined with quantization in the voltage domain and time domain, which can make full use of the characteristics of the small input voltage amplitude and realize the optimization of the overall circuit performance.

Technical scheme of the present invention is:

A pipelined successive approximation ADC based on the combination of voltage domain and time domain quantization, including first-stage ADC, second-stage ADC and buffer,

The input terminal of the first-stage ADC is connected to the input signal, and the first output terminal outputs the first-stage quantization result obtained after the high-order bits of the input signal are quantized by the first-stage ADC, and the second output terminal outputs the input signal. The part that has not been processed by the first-stage ADC is input to the input terminal of the second-stage ADC after passing through the buffer, and the output terminal of the second-stage ADC outputs the quantized signal input by the second-stage ADC. The second-level quantization result, the first-level quantization result and the second-level quantization result are used as the high and low bits of the final output codeword and are sequentially encoded to obtain the final quantization result;

The second-stage ADC includes a time-domain reference analog-to-digital converter, a voltage-domain reference analog-to-digital converter and a digital logic control module,

The analog-to-digital converter of the time domain reference includes a first comparator and a first capacitor array of N bits, and the first capacitor array includes two groups connected to the first input terminal and the second input terminal of the first comparator respectively The same capacitor group, each group of capacitor groups includes N quantization capacitors and a parasitic unit capacitor, and the N quantization capacitors are connected to the ground or to one of the ground potential, common-mode potential or reference potential through a switch, so The parasitic unit capacitance is respectively connected to one of ground potential, common mode potential or reference potential through switches;

The analog-to-digital converter of the voltage domain reference includes a second comparator and a second capacitor array of N bits, the output terminal of the second capacitor array is connected to the input terminal of the second comparator, and the input terminals are respectively connected by switches connected to one of ground potential, an input signal into the second-stage ADC, or a reference voltage;

The input terminal of the digital logic control module is connected to the output terminals of the first comparator and the second comparator, and the output terminal thereof is used as the output terminal of the second-stage ADC.

Specifically, the first-stage ADC is a successive approximation ADC.

Specifically, the buffer is a unity gain buffer.

Specifically, the first capacitor array and the second capacitor array are even-numbered capacitor arrays.

Specifically, the first comparator and the second comparator are the same comparator.

The beneficial effects of the present invention are: the present invention utilizes the overall structure of the two-stage pipeline, and adopts the combined quantization method of the voltage domain and the time domain in the second stage, which can realize the output code word of two bits per cycle, and effectively improves the conversion rate of the circuit ; In the embodiment, the first-stage ADC is a successive approximation ADC, and the buffer is a unity-gain buffer. Since the quantization in the time domain is more accurate at low voltage, it is not necessary to convert the residual of the previous stage like a traditional Pipelined analog-to-digital converter. The differential voltage is amplified, and only a unity gain buffer is used to realize the conversion between the two stages, the linearity is improved, and the accuracy of the overall circuit is effectively improved; at the same time, the implementation of each pipeline stage by the SAR analog-to-digital converter can effectively reduce the overall power consumption of the circuit.

Description of drawings

Fig. 1 is the overall circuit system architecture of the pipeline successive approximation ADC based on the combination of voltage domain and time domain quantization proposed by the present invention;

Figure 2 is a diagram illustrating the principle of the combined quantization process in the voltage domain and time domain;

Fig. 3 is the circuit schematic diagram of the traditional SAR analog-to-digital converter used in the first stage ADC in the embodiment;

Fig. 4 is the schematic diagram of the SAR analog-to-digital converter that uses 10-bit voltage domain and time domain combined quantization in the second stage ADC in the embodiment;

Fig. 5 is a timing diagram of quantization of the overall circuit in the embodiment.

detailed description

The pipeline successive approximation ADC structure of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that: the parameters in the implementation examples do not affect the generality of the present invention.

As shown in Figure 1, it is the overall circuit system architecture of the pipeline successive approximation ADC based on the combination of voltage domain and time domain quantization proposed by the present invention, including a first-stage ADC, a second-stage ADC and a buffer, and the first-stage ADC's The input terminal is connected to the input signal, and its first output terminal outputs the first-level quantization result obtained after the high-order bit of the input signal is quantized by the first-level ADC, and its second output terminal outputs the input signal that has not been processed by the first-level ADC The part of the buffer is input to the input end of the second-stage ADC, and the output end of the second-stage ADC outputs the second-stage quantization result quantized by the second-stage ADC, and the first-stage quantization The result and the second-level quantization result are used as the high and low bits of the final output codeword and are encoded in sequence to obtain the final quantization result; the second-level ADC includes an analog-to-digital converter of a time-domain reference, an analog-to-digital converter of a voltage-domain reference, and A digital logic control module, the analog-to-digital converter of the time domain reference includes a first comparator and a first capacitor array of N bits, and the first capacitor array includes two groups that are respectively connected to the first input terminal of the first comparator and The same capacitor group connected to the second input terminal, each group of capacitor groups includes N quantization capacitors and a parasitic unit capacitor, and the N quantization capacitors are connected to the ground or to the ground potential, common mode potential or reference potential through switches. One connection of the parasitic unit capacitance is connected to one of the ground potential, the common mode potential or the reference potential through a switch; the analog-to-digital converter of the voltage domain reference includes a second comparator and an N-bit second capacitor array , the output terminal of the second capacitor array is connected to the input terminal of the second comparator, and its input terminal is connected to one of the ground potential, the input signal or the reference voltage input to the second-stage ADC through a switch; The input terminal of the digital logic control module is connected to the output terminals of the first comparator and the second comparator, and the output terminal thereof is used as the output terminal of the second-stage ADC.

In this embodiment, the first-stage ADC is a successive approximation ADC, its structure is shown in FIG. 3 , and the buffer is a unity gain buffer. In this embodiment, quantization is realized by means of a two-stage pipeline, and each stage of ADC is a successive approximation analog-to-digital converter. The input signal is quantized in the first stage, and the amplitude of the input signal is continuously reduced in the successive approximation. The output delay of the comparator increases exponentially with the decrease of the input voltage amplitude of the comparator, and the greater the difference between the comparison time and the amplitude, the higher the accuracy of the comparison. Utilizing such a feature, it is not necessary to amplify the residual voltage after the quantization of the first stage, and only need to cascade a unity gain buffer to pass the output voltage of the first stage to the second stage as the input voltage.

In this embodiment, the second-stage ADC is illustrated with a 10-bit analog-to-digital converter, as shown in Figure 4. It is worth noting that the present invention is not only applicable to the combination of the voltage domain and the time domain of the second-stage ADC using 10 bits. Quantized SAR ADC. The connection mode of the voltage domain reference ADC 502 is consistent with that of the traditional SAR ADC. The lower plate of the highest capacitor of the time-domain reference analog-to-digital converter 501 is always at ground potential, and the lower plates of the corresponding third, fifth, seventh, and ninth capacitors are also always at ground potential. The lower plates of other capacitors are respectively connected to the reference voltage VREF, the ground potential GND and the common mode potential Vcm through switches. The function of this digital-to-analog converter is to sequentially provide 1/4VREF, 1/16VREF, 1/32VREF, 1 Voltage amplitude of /64VREF and 1/128VREF. Take the first quantization as an example, as shown in Figure 2, each output result of the first comparator contains two bits of information, one is the comparison result between the input voltage and the reference voltage, and the other is the input voltage Associated output delay time 1. When an identical second comparator is added, and the input voltage difference is 1/4 of the reference voltage of each cycle, the output time delay 0 of the second comparator is the reference time of each comparison cycle. Comparing this time with the delay time 1 of the first comparator can judge the relationship between the input voltage difference of the first comparator and 1/4VREF, so that each quantization is divided into 4 intervals, and the quantization of two digits is completed. .

The first capacitor array and the second capacitor array in this embodiment use even-numbered capacitor arrays, but they can also be odd-numbered capacitor arrays. When using odd-numbered capacitor arrays, one bit is quantized at the last time.

The quantization timing diagram of this embodiment is shown in Figure 5. The first-stage and second-stage analog-to-digital converters are quantized in a pipelined manner, and the first-stage ADC performs successive approximation according to the traditional SAR working method, and each cycle quantizes 1 Bits go through the process of sampling, quantizing and buffering. The second-stage ADC uses the combination of voltage domain and time domain to realize quantization of 2 bits per cycle, which improves the conversion rate of the circuit. The first-stage ADC and the second-stage ADC realize the quantization at the same time through the working mode of the pipeline, which improves the overall conversion rate. The low power consumption characteristic of the converter, which also reduces the power consumption of the whole circuit. To sum up, the present invention has better characteristics in terms of circuit conversion rate, quantization accuracy and power consumption.

It should be clear to those skilled in the art that insubstantial changes or improvements made without departing from the spirit of the present invention should all fall within the protection scope of the claims of the present invention.

Claims (5)

1. a kind of combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, it is characterised in that including the first order ADC, second level ADC and buffer,

The input connection input signal of the first order ADC, its first output end export the first order ADC to input signal A high position quantified after obtained first order quantized result, not by first order ADC in its second output end output input signal The part of processing and the input that second level ADC is inputted after the buffer, the output end output institute of the second level ADC Second level ADC is stated to inputting the second level quantized result after signal therein quantifies, the first order quantized result and the Two level quantized result obtains final quantization result as a high position for final output code word with low level and after encoding successively；

The second level ADC includes the analog-digital converter of time-domain reference, the analog-digital converter of voltage domain benchmark and Digital Logic control Molding block,

The analog-digital converter of the time-domain reference includes the first capacitor array of first comparator and N positions, the first electric capacity battle array Row include two groups of identical capacitance groups being connected respectively with the first input end of first comparator and the second input, every group of electric capacity Group includes a N number of quantization electric capacity and parasitic specific capacitance, described N number of to quantify the alternate ground connection of electric capacity or pass through switch difference Be connected with one in ground potential, common mode current potential or reference potential, the parasitic specific capacitance by switch respectively with ground potential, A connection in common mode current potential or reference potential；

The analog-digital converter of the voltage domain benchmark includes the second comparator and the second capacitor array of N positions, second electric capacity The output end of array connects the input of second comparator, its input by switch respectively with ground potential, be input to the A connection in input signal or reference voltage in two level ADC；

The input of the Digital Logic control module connects the first comparator and the output end of the second comparator, and it is exported Hold the output end as the second level ADC.

2. according to claim 1 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists In the first order ADC is SAR ADC.

3. according to claim 2 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists In the buffer is unit gain buffer.

4. according to claim 1 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists In first capacitor array and the second capacitor array are the capacitor array of even bit.

5. according to claim 1 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists In the first comparator and the second comparator are identical comparator.