CN107395201A - It is a kind of to be combined the streamline successive approximation analog to digital C quantified with time domain based on voltage domain - Google Patents
It is a kind of to be combined the streamline successive approximation analog to digital C quantified with time domain based on voltage domain Download PDFInfo
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- CN107395201A CN107395201A CN201710605483.1A CN201710605483A CN107395201A CN 107395201 A CN107395201 A CN 107395201A CN 201710605483 A CN201710605483 A CN 201710605483A CN 107395201 A CN107395201 A CN 107395201A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
It is a kind of to be combined the streamline successive approximation analog to digital C quantified with time domain based on voltage domain, belong to Analogous Integrated Electronic Circuits technical field.Using two stage pipeline structures, first order ADC input connection input signal, the high several first order quantized results obtained after being quantified in its first output end output input signal, its second output end exports part not processed in input signal and second level ADC input is inputted after buffer, second level quantized result after second level ADC output end output quantization, first order quantized result and second level quantized result obtain final quantization result as a high position for final output code word with low level and after encoding successively.Second level ADC is combined the SAR analog-digital converters quantified using voltage domain with time domain, can be realized the output codons of each cycle two, be effectively increased switching rate；Because the quantization of time domain is more accurate under low pressure, the conversion between two-stage can be realized with a unity gain buffer, improve the linearity, effectively increase circuit precision.
Description
Technical field
It is more particularly to a kind of to be combined what is quantified with time domain using voltage domain the invention belongs to Analogous Integrated Electronic Circuits technical field
The analog-digital converter of streamline successive approximation.
Background technology
In recent years, computer, communication and multimedia technology rapid development, the digitized degree of the high frontier in the whole world constantly add
It is deep, it is required for using analog-digital converter in many electronic systems the analog signals such as voltage, electric current is converted into digital coding
Handled again afterwards, to utilize the powerful data-handling capacity of large-scale digital ic.
With the innovation and the decline of chip power supply voltage of semiconductor fabrication process, high performance Design of A/D Converter face
Face new challenge.Traditional Approach by inchmeal SAR analog-digital converters are difficult to high turn with streamline Pipelined analog-to-digital conversion devices
Change speed, high accuracy and the performance indications of low-power consumption, it is often necessary to sacrifice some index to meet other requirements.
Traditional SAR analog-digital converters are made up of comparator, digital-to-analogue converter and digital control logic.Digital control logic
The exports coding value of each is determined according to the output result of comparator successively.It is each using the Bisection Algorithms mode of Approach by inchmeal
Conversion is required for N number of quantization cycle, and experience n times compare, and its switching rate is limited by very large.In addition, it is traditional
SAR analog-digital converters only make use of the voltage comparative result of comparator output and have ignored other letters that comparator can provide
Breath so that every time quantify can only unit carry out, this also seriously limits the switching rate of SAR analog-digital converters.
Traditional streamline Pipelined analog-to-digital conversion devices belong to multiphase converter, have sampling hold circuit per one-level,
And there is quantization surplus of the interstage amplifier to this grade to be amplified, then export and make further quantify to rear class.Sampling is protected
Hold circuit and amplify so that only needing each pipeline stages to be respectively completed quantization in a cycle with residual error, without whole converter
It is disposable to complete conversion, therefore switching rate will not decline with the increase of series but accurate due to needing to use gain
Interstage amplifier, overall power is larger, particularly under the advanced technologies of low pressure short channel, realizes the operational amplifier of high-gain
Seem more difficult to the stable feedback network of designing gain.
The content of the invention
For weak point of traditional analog-digital converter circuit structure in terms of precision, switching rate and power consumption, this hair
It is bright to provide a kind of streamline successive approximation analog to digital C for being combined and being quantified with time domain based on voltage domain, using two stage pipeline structures, the
Two level is combined the SAR analog-digital converters quantified with time domain using voltage domain and realized, input voltage amplitude can be made full use of smaller
The characteristics of, realize the optimization of overall circuit performance.
The technical scheme is that：
It is a kind of to be combined the streamline successive approximation analog to digital C quantified, including first order ADC, the second level with time domain based on voltage domain
ADC and buffer,
The input connection input signal of the first order ADC, its first output end export the first order ADC to input
The first order quantized result that a high position for signal obtains after being quantified, its second output end are exported in input signal not by the first order
The part of ADC processing and the input that second level ADC is inputted after the buffer, the output end of the second level ADC are defeated
Go out the second level ADC to inputting the second level quantized result after signal therein quantifies, the first order quantized result
With a high position of the second level quantized result as final output code word final quantization result is obtained with low level and after encoding successively；
The second level ADC includes the analog-digital converter of time-domain reference, the analog-digital converter of voltage domain benchmark and numeral and patrolled
Collect control module,
The analog-digital converter of the time-domain reference includes the first capacitor array of first comparator and N positions, first electricity
Holding array includes two groups of identical capacitance groups being connected respectively with the first input end of first comparator and the second input, every group
Capacitance group includes a N number of quantization electric capacity and parasitic specific capacitance, described N number of to quantify the alternate ground connection of electric capacity or pass through switch
Be connected respectively with one in ground potential, common mode current potential or reference potential, the parasitic specific capacitance by switch respectively with ground
A connection in current potential, common mode current potential or reference potential；
Second capacitor array of the analog-digital converter of the voltage domain benchmark including the second comparator and N positions, described second
The output end of capacitor array connects the input of second comparator, its input by switch respectively with ground potential, input
Connected to the input signal in the ADC of the second level or one in reference voltage；
The input of the Digital Logic control module connects the first comparator and the output end of the second comparator, its
Output end of the output end as the second level ADC.
Specifically, the first order ADC is SAR ADC.
Specifically, the buffer is unit gain buffer.
Specifically, first capacitor array and the capacitor array that the second capacitor array is even bit.
Specifically, the first comparator and the second comparator are identical comparator.
Beneficial effects of the present invention are：The present invention utilizes the overall architecture of two level production lines, and voltage domain is used in the second level
The mode quantified is combined with time domain, it is possible to achieve the output codons that each cycle is two, effectively increase the switching rate of circuit；It is real
It is SAR ADC to apply first order ADC in example, and buffer is unit gain buffer, due to time domain quantization under low pressure
It is more accurate, thus without need to be amplified the residual error voltage of previous stage as traditional Pipelined analog-digital converters, only need to use
One unity gain buffer realizes the conversion between two-stage, and the linearity has lifting, effectively improve the precision of integrated circuit；Together
When with SAR analog-digital converters realize that each pipeline stages can effectively reduce the power consumption of integrated circuit.
Brief description of the drawings
Fig. 1 is the overall electricity of the streamline successive approximation analog to digital C proposed by the present invention for being combined and being quantified with time domain based on voltage domain
Road system architecture；
Fig. 2 is that voltage domain is combined quantization Principle of Process explanation figure with time domain；
Fig. 3 is the circuit theory diagrams that first order ADC uses traditional SAR analog-digital converters in embodiment；
Fig. 4 is that second level ADC is combined the SAR analog-digital converters quantified using the voltage domain of 10 with time domain in embodiment
Schematic diagram；
Fig. 5 is that integrated circuit quantifies timing diagram in embodiment.
Embodiment
Below in conjunction with the accompanying drawings the streamline successive approximation analog to digital C-structure of the present invention is made further to explain with specific embodiment
State.It should be noted that：Parameter in embodiment has no effect on the generality of the present invention.
It is the streamline successive approximation analog to digital C proposed by the present invention for being combined and being quantified with time domain based on voltage domain as shown in Figure 1
Integrated circuit system architecture, including first order ADC, second level ADC and buffer, the input connection of the first order ADC are defeated
Enter signal, its first output end exports the first order amount obtained after the first order ADC is quantified a high position for input signal
Change result, its second output end exports not by the first order ADC parts handled and defeated after the buffer in input signal
Enter second level ADC input, the output end output of the second level ADC passes through the second level after second level ADC quantizations
Quantized result, the high position and low level and successively of the first order quantized result and second level quantized result as final output code word
Final quantization result is obtained after coding；The second level ADC includes analog-digital converter, the modulus of voltage domain benchmark of time-domain reference
Converter and digital Logic control module, the analog-digital converter of the time-domain reference include the first electricity of first comparator and N positions
Hold array, what first capacitor array was connected with the first input end of first comparator and the second input respectively including two groups
Identical capacitance group, every group of capacitance group include N number of quantization electric capacity and a parasitic specific capacitance, and N number of quantization electric capacity is alternate
Ground connection or be connected respectively with one in ground potential, common mode current potential or reference potential by switch, the parasitic unit is electric
Hold and be connected respectively with one in ground potential, common mode current potential or reference potential by switch；The modulus of the voltage domain benchmark turns
Parallel operation includes the second comparator and the second capacitor array of N positions, output end connection second ratio of second capacitor array
Compared with the input of device, its input is electric with ground potential, the input signal being input in the ADC of the second level or benchmark respectively by switching
A connection in pressure；The input of the Digital Logic control module connects the defeated of the first comparator and the second comparator
Go out end, output end of its output end as the second level ADC.
First order ADC is SAR ADC in the present embodiment, and its structure is as shown in figure 3, buffer delays for unit gain
Rush device.The present embodiment realizes quantization by way of two level production lines, is gradually-appoximant analog-digital converter per one-level ADC.Input
Signal quantifies by the first order, and the amplitude of input signal constantly reduces in Approach by inchmeal.Comparator output delay with than
Exponentially increase compared with the reduction of device input voltage amplitude, and compare the precision that the time is bigger with the variation of amplitude, compares
Also it is higher.Using such a characteristic, it is not required to the residual error voltage after the first order is quantified and is amplified, only need to cascades a unit
The output voltage of the first order is delivered to the second level as input voltage by gain buffer.
Second level ADC is illustrated with the analog-digital converter of one 10 in the present embodiment, as shown in figure 4, being worth saying
Bright is that the present invention is applicable not only to the SAR analog-digital converters that second level ADC is combined quantization using the voltage domain of 10 with time domain.
The connected mode of voltage domain benchmark analog-digital converter 502 is consistent with the connected mode of traditional SAR analog-digital converters.Time-domain reference mould
The highest order electric capacity bottom crown of number converter 501 earthing potential all the time, corresponding 3rd, the 5th, the 7th with the 9th
Also earthing potential, other electric capacity bottom crowns in addition can connect reference voltage respectively to electric capacity bottom crown by switch all the time
VREF, ground potential GND and common mode current potential Vcm, the effect of this digital analog converter are that 1/ is sequentially provided in quantizing process
4VREF, 1/16VREF, 1/32VREF, 1/64VREF and 1/128VREF voltage magnitude.To quantify for the first time to illustrate,
As shown in Fig. 2 each output result of first comparator includes two information, one be input voltage and reference voltage ratio
Relatively result, one is the output delay time 1 related to input voltage size in addition.Compare when increasing an identical second
Device, when input voltage difference is the 1/4 of the reference voltage in each cycle, the output time delay 0 of the second comparator is exactly each ratio
Compared with the fiducial time in cycle.The delay time 1 of the time and first comparator are compared and may determine that the defeated of first comparator
Enter voltage difference and 1/4VREF magnitude relationship, so as to which each quantization is divided into 4 sections, complete the quantization of two.
The first capacitor array and the second capacitor array in the present embodiment use the capacitor array of even bit, but can also be
Odd bits, just quantify one using last time during odd bits capacitor array.
The present embodiment quantifies timing diagram as shown in figure 5, the first order, second level analog-digital converter are by the way of streamline
Quantified, first order ADC according to traditional SAR working method carry out Approach by inchmeal, each periodic quantization 1, experience sampling,
Quantify and buffer the process kept.Second level ADC realizes each periodic quantization 2 using voltage domain with the mode that time domain is combined
Position, improve the speed of circuit conversion.First order ADC and second level ADC are realized at the same time by the working method of streamline
Interior quantization, improves overall switching rate, and the present embodiment uses the implementation of two-stage SAR rather than overall streamline
The low power consumption characteristic of SAR analog-to-digital conversion devices is allowed for, this can also reduce the power consumption of whole circuit.In summary, the present invention exists
Switching rate, quantified precision and power consumption of circuit etc. have preferable characteristic.
Those skilled in the art it should be appreciated that be altered or modified in the unsubstantiality that is done of spirit for not departing from the present invention,
The scope of the claims in the present invention protection should all be belonged to.
Claims (5)
1. a kind of combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, it is characterised in that including the first order
ADC, second level ADC and buffer,
The input connection input signal of the first order ADC, its first output end export the first order ADC to input signal
A high position quantified after obtained first order quantized result, not by first order ADC in its second output end output input signal
The part of processing and the input that second level ADC is inputted after the buffer, the output end output institute of the second level ADC
Second level ADC is stated to inputting the second level quantized result after signal therein quantifies, the first order quantized result and the
Two level quantized result obtains final quantization result as a high position for final output code word with low level and after encoding successively；
The second level ADC includes the analog-digital converter of time-domain reference, the analog-digital converter of voltage domain benchmark and Digital Logic control
Molding block,
The analog-digital converter of the time-domain reference includes the first capacitor array of first comparator and N positions, the first electric capacity battle array
Row include two groups of identical capacitance groups being connected respectively with the first input end of first comparator and the second input, every group of electric capacity
Group includes a N number of quantization electric capacity and parasitic specific capacitance, described N number of to quantify the alternate ground connection of electric capacity or pass through switch difference
Be connected with one in ground potential, common mode current potential or reference potential, the parasitic specific capacitance by switch respectively with ground potential,
A connection in common mode current potential or reference potential；
The analog-digital converter of the voltage domain benchmark includes the second comparator and the second capacitor array of N positions, second electric capacity
The output end of array connects the input of second comparator, its input by switch respectively with ground potential, be input to the
A connection in input signal or reference voltage in two level ADC；
The input of the Digital Logic control module connects the first comparator and the output end of the second comparator, and it is exported
Hold the output end as the second level ADC.
2. according to claim 1 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists
In the first order ADC is SAR ADC.
3. according to claim 2 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists
In the buffer is unit gain buffer.
4. according to claim 1 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists
In first capacitor array and the second capacitor array are the capacitor array of even bit.
5. according to claim 1 combined the streamline successive approximation analog to digital C quantified based on voltage domain with time domain, its feature exists
In the first comparator and the second comparator are identical comparator.
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| CN201710605483.1A CN107395201B (en) | 2017-07-24 | 2017-07-24 | Assembly line successive approximation ADC based on voltage domain and time domain combined quantization |
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| CN108075778A (en) * | 2017-11-29 | 2018-05-25 | 四川知微传感技术有限公司 | Pipeline SAR-ADC circuit structure |
| CN108599763A (en) * | 2018-05-11 | 2018-09-28 | 成都华微电子科技有限公司 | SAR types ADC is with active amplifier type capacitance redistribution array |
| CN109977458A (en) * | 2019-02-03 | 2019-07-05 | 北京大学 | A kind of mixed analog to digital converter |
| CN112653468A (en) * | 2020-12-15 | 2021-04-13 | 西安电子科技大学 | Novel timing sequence assembly line ADC based on interstage buffer isolation |
| CN114499529A (en) * | 2022-04-01 | 2022-05-13 | 浙江地芯引力科技有限公司 | Analog-digital converter circuit, analog-digital converter, and electronic apparatus |
| CN114614822A (en) * | 2022-04-12 | 2022-06-10 | 电子科技大学 | Interstage gain nonlinear calibration method of pipeline-SAR ADC |
| CN115149948A (en) * | 2022-07-15 | 2022-10-04 | 电子科技大学 | Pipelined SAR ADC with high linearity characteristic |
| WO2023092887A1 (en) * | 2021-11-24 | 2023-06-01 | 深圳市中兴微电子技术有限公司 | Pipelined successive-approximation analog-to-digital converter, integrated circuit, and electronic device |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108075778A (en) * | 2017-11-29 | 2018-05-25 | 四川知微传感技术有限公司 | Pipeline SAR-ADC circuit structure |
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| CN108599763A (en) * | 2018-05-11 | 2018-09-28 | 成都华微电子科技有限公司 | SAR types ADC is with active amplifier type capacitance redistribution array |
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| CN112653468B (en) * | 2020-12-15 | 2023-05-26 | 西安电子科技大学 | Time sequence assembly line ADC based on interstage buffer isolation |
| CN112653468A (en) * | 2020-12-15 | 2021-04-13 | 西安电子科技大学 | Novel timing sequence assembly line ADC based on interstage buffer isolation |
| WO2023092887A1 (en) * | 2021-11-24 | 2023-06-01 | 深圳市中兴微电子技术有限公司 | Pipelined successive-approximation analog-to-digital converter, integrated circuit, and electronic device |
| CN114499529B (en) * | 2022-04-01 | 2022-07-19 | 浙江地芯引力科技有限公司 | Analog-digital converter circuit, analog-digital converter, and electronic apparatus |
| CN114499529A (en) * | 2022-04-01 | 2022-05-13 | 浙江地芯引力科技有限公司 | Analog-digital converter circuit, analog-digital converter, and electronic apparatus |
| CN114614822A (en) * | 2022-04-12 | 2022-06-10 | 电子科技大学 | Interstage gain nonlinear calibration method of pipeline-SAR ADC |
| CN115149948A (en) * | 2022-07-15 | 2022-10-04 | 电子科技大学 | Pipelined SAR ADC with high linearity characteristic |
| CN115149948B (en) * | 2022-07-15 | 2024-10-01 | 电子科技大学 | PIPELINED SAR ADC with high linearity characteristic |
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