CN115149948A - Pipelined SAR ADC with high linearity characteristic - Google Patents

Abstract

The invention belongs to the technical field of ADC (analog to digital converter), and particularly relates to a Pipelined SARADC with low power consumption and high linearity. The structure of the invention mainly separates the MDAC from the first-stage sub SAR ADC, the first-stage sub SAR ADC only needs to quantize 6bit of the signal, then the quantized digital signal is transmitted to the MDAC, and the residual error of the MDAC is subtracted and amplified to the next-stage sub ADC for quantization. Compared with the traditional Pipeline ADC, the scheme of the invention can use the lower polar plate for sampling, eliminates the kickback noise of the first stage and the comparator and the damage of clock feed-through to residual signals, reduces the non-linearity of parasitic capacitance of the upper polar plate of the sub-ADC, eliminates the clock feed-through and charge injection of an amplifier switch, and greatly improves the linearity of the Pipeline SAR ADC.

Description

Pipelined SAR ADC with high linearity characteristic

Technical Field

The invention belongs to the technical field of ADCs, and particularly relates to a pipeline SAR ADC with high linearity.

Background

At present, the Pipelined-SAR ADC has the main advantages of keeping low power consumption and small area, and combining technologies such as multi-channel, time interleaving, multi-bit per step, multi-comparator and the like, so that the architecture is concerned in the research field of analog-to-digital converters. The Pipelined-SAR ADC is composed of a sample-and-hold circuit, a sub-ADC and an interstage amplifier, wherein the sub-ADC adopts a successive approximation type analog-to-digital converter (SAR ADC) to replace a traditional Flash type ADC (Flash ADC), and the advantage of the method is that the resolution of each stage can be effectively increased, so that a plurality of stages are not needed to realize higher resolution. Due to the fact that the Pipeled-SAR ADC has the influences of non-ideal factors such as clock feed-through effect of a sampling switch tube, charge injection effect, capacitance mismatch of a sampling capacitor, limited gain and non-linear effect of an interstage amplifier, and imbalance of a comparator, the factors limit the accuracy which the Pipeled-SAR ADC can achieve. These partial non-idealities can then be reduced by adjustment of the structure.

The conventional Pipelined SAR ADC generally adopts a structure as shown in FIG. 1, which is a 14bit Pipelined SAR ADC and is a 6+9 structure, and has one-bit inter-level redundancy.

The Pipelined SAR ADC comprises an SH (gate voltage bootstrapped switch), a capacitor array, a comparator, an SAR LOGIC, an amplifier and a second-stage 9-bit SAR ADC module.

The SH (sample and hold module), the capacitor alignment, the comparator and the SAR LOGIC are combined into a first-stage SAR ADC, and the second-stage 9-bit SAR ADC also comprises the SH, the capacitor alignment, the comparator and the SAR LOGIC module.

The ADC quantization process is as follows: firstly, VIN and VIP sample signals to an upper plate of a capacitor through an SH (gate voltage bootstrap switch), then the signals sampled by the upper plate are compared through a comparator, the output results of the comparator are respectively 0 and 1, then the comparator result is processed through SAR LOGIC, and then the voltage of a lower plate of the capacitor with corresponding weight is changed, so that the voltage of the upper plate of the capacitor array is changed. This is the quantization of the first stage SAR ADC.

After the first-stage SAR ADC quantization is finished, amplifying the residual voltage of the upper polar plate on the first-stage SAR ADC capacitor array to the next-stage 9-bit SAR ADC through a residual amplifier for quantization. Compared with a Pipeline ADC, the use of a comparator and an amplifier is reduced, and the power consumption is greatly reduced.

However, this structure is only suitable for a precision of 12 bits or less, and is hardly satisfied for a precision of 12 bits or more. The reason is 4 points:

(1) The sampling mode is upper plate sampling, and the accuracy of the upper plate sampling is difficult to achieve more than 12 bits. And the structure adopts the lower polar plate for sampling, so that the common mode switch is difficult to meet. The sampling precision of the first-stage SAR determines the precision of the whole ADC, and the sampling needs to wait for the amplification of the amplifier to be finished, so the time for resetting the common-mode switch of the first-stage SAR ADC is too short, the common-mode switch resets the upper polar plate to VCM, a very large size is needed, and a very large nonlinear parasitic capacitor can be brought by the large size.

(2) The kickback noise and the clock feed-through of the comparator damage the residual signal, and then the signal is transmitted to the next stage sub ADC for quantization through the amplifier, and the quantized signal is multiplied by the kickback noise and the clock feed-through damage the residual signal of the first stage comparator. And if the input MOS transistor of the comparator is reduced to reduce its kickback noise and clock feedthrough, its thermal noise will be greatly increased.

(3) The parasitic capacitance of the upper polar plate of the sub-ADC is nonlinear, the parasitic capacitance of the upper polar plate not only has the grid capacitance of the comparator, but also has the grid capacitance of the amplifier and the parasitic capacitance of the switch, and the nonlinearity of the parasitic capacitance of the switch can greatly increase the quantization result of the first-stage SAR, so that the precision of the whole ADC is influenced.

(4) The clock feed-through and charge injection of the amplifier switch can damage signals due to the clock feed-through and charge injection at the moment of opening when the switch works greatly.

Disclosure of Invention

In view of the above problems, the present invention provides a Pipelined SAR ADC having a high linearity characteristic.

The technical scheme adopted by the invention is as follows:

a pipeline SAR ADC with high linearity characteristics comprises a first-stage SAR ADC, an MDAC module and a second-stage SAR ADC;

the first-stage SAR ADC comprises a first grid voltage bootstrap switch, a first capacitor array, a first SAR logic module, a second grid voltage bootstrap switch, a second capacitor array, a second SAR logic module and a comparator; the input end of the first grid voltage bootstrap switch is connected with a VIN signal in the differential input signal, and the output of the first grid voltage bootstrap switch is connected with the first SAR logic module and the inverting input end of the comparator after passing through the first capacitor array; the input end of the second grid voltage bootstrap switch is connected with a VIP signal in the differential input signals, and the output of the second grid voltage bootstrap switch is connected with the second SAR logic module and the non-inverting input end of the comparator after passing through the second capacitor array; the first SAR logic module and the second SAR logic module are connected with the output of the comparator; the first grid voltage bootstrap switch and the second grid voltage bootstrap switch are used for respectively sampling differential input signals to upper plates of a first capacitor array and a second capacitor array, the comparator is used for comparing the sampling signals of the upper plates, the first SAR logic module and the second SAR logic module are used for changing the voltage of the upper plates of the capacitors with the weights corresponding to the first capacitor array and the second capacitor array according to the comparison result of the comparator, the voltage of the upper plates of the capacitor arrays is changed, the first SAR logic module and the second SAR logic module obtain a first-stage quantization result after the quantization is finished, and the first-stage quantization result is transmitted to the MDAC module;

the MDAC module comprises a first SH and LATCH module, a second SH and LATCH module, an amplifier, a third capacitor array and a fourth capacitor array, wherein the first SH and LATCH module and the second SH and LATCH module comprise a grid voltage bootstrap switch and a LATCH circuit, the first SH and LATCH module and the second SH and LATCH module are respectively connected with differential input signals and sample the differential input signals simultaneously with the first-stage SAR ADC, the first SH and LATCH module and the second SH and LATCH module store received first-stage quantization results through the LATCH circuit, the MDAC module carries out residual subtraction on self sampling signals and the first-stage quantization results so as to form residual difference voltage between the third capacitor array and the fourth capacitor array, and the residual difference voltage is amplified by the amplifier and then transmitted to the second-stage SAR ADC;

the second SAR ADC is a 9-bit SAR ADC, and the input amplified signal is quantized to obtain a final quantization result.

The invention has the beneficial effects that: the linearity is greatly improved while the low power consumption advantage of the traditional Pipelined SAR ADC architecture is kept.

Drawings

Fig. 1 is a schematic diagram of a conventional pipeline SAR ADC.

Fig. 2 is a schematic diagram of a Pipelined SAR ADC of the present invention.

Detailed Description

The invention is described in detail below with reference to the attached drawing figures:

the Pipelined SAR ADC structure of the invention is shown in FIG. 2 and comprises an SH (sample-and-hold module), a first-stage SAR capacitor array, a comparator, an SAR LOGIC, an amplifier and a capacitor array of the amplifier, and a second-stage 9-bit SAR ADC module.

The SH (sample and hold module), the capacitor alignment, the comparator and the SAR LOGIC are combined into a first-stage SARAADC, and the second-stage 9-bit SAR ADC also comprises the SH, the capacitor alignment, the comparator and the SAR LOGIC module.

Capacitor array of amplifier and amplifier itself combined into MDAC module

The ADC quantization process is as follows: VIN and VIP sample the signal to the upper plate of the capacitor through SH (grid voltage bootstrap switch), then the signal sampled by the upper plate is compared through a comparator, the output result of the comparator is 0 and 1, then the comparator result is processed through SAR LOGIC, and then the voltage of the lower plate of the capacitor corresponding to the weight is changed, so that the voltage of the upper plate of the capacitor array is changed. This is the quantization of the first stage SAR ADC.

Different from the traditional result, when the first-stage SAR ADC is used for sampling, the capacitor on the MDAC is used for sampling in the same way, and after the first-stage SAR ADC is quantized, the quantized result is transmitted to the capacitor array of the MDAC, so that the capacitor array of the MDAC forms residual voltage, and the residual voltage is amplified by a residual amplifier to be quantized to the next-stage 9-bit SAR ADC.

Compared with the traditional Pipeline ADC, the ADC has the same use times of the comparator and the amplifier in one sampling period, the total capacitance value is basically not greatly improved, the low power consumption is kept, and the linearity of the ADC is greatly improved. The structure of the invention mainly separates the MDAC from the first-stage sub SAR ADC, and the first-stage sub SAR ADC only needs to quantize 6 bits of the signal. And then, the quantized digital signal is transferred to an MDAC, and the MDAC residual is subtracted and amplified to a next-stage sub-ADC for quantization.

The sampling time of the first-stage sub SAR ADC is greatly increased, the sampling is carried out without waiting for the amplification of the amplifier, and the sampling can be carried out when the amplifier amplifies. Taking a 500M SPS Pipelined SAR ADC as an example, the sampling time is changed from original 300p to present 1.3n, a sampling switch can adopt simple complementary switch for sampling, the sampled signal only needs to meet the accuracy of 6 bits, and the total capacitance value of a CDAC capacitor array of a first-stage sub SAR ADC also does not need to meet the level of KT/C noise in quantization noise, so that the original low power consumption is maintained.

The MDAC integrates the functions of sampling, residual subtraction and amplification, can adopt lower polar plate sampling, and the common mode switch of the upper polar plate is input at the same end point in the operational amplifier, and when the sampling is finished, the residual subtraction and amplification are carried out, the voltage value of the point is basically the same, so that the problem that the signal precision is greatly influenced by the nonlinearity of the parasitic capacitance can be solved.

And signals quantized by the first-stage sub SAR ADC and signals transmitted to the next stage by the MDAC are separated, so that the damage of kickback noise and clock feed-through of the comparator to residual signals is avoided.

And the MDAC of the structure, the clock feed-through of the amplifier switch and the charge injection do not generate differential mode errors to the signals basically.

Claims (1)

1. A Pipelined SAR ADC with high linearity characteristic is characterized by comprising a first-stage SAR ADC, an MDAC module and a second-stage SAR ADC;

the first-stage SAR ADC comprises a first grid voltage bootstrap switch, a first capacitor array, a first SAR logic module, a second grid voltage bootstrap switch, a second capacitor array, a second SAR logic module and a comparator; the input end of the first grid voltage bootstrap switch is connected with a VIN signal in the differential input signal, and the output of the first grid voltage bootstrap switch is connected with the first SAR logic module and the inverting input end of the comparator after passing through the first capacitor array; the input end of the second grid voltage bootstrap switch is connected with a VIP signal in the differential input signals, and the output of the second grid voltage bootstrap switch is connected with the second SARlogic module and the non-inverting input end of the comparator after passing through the second capacitor array; the first SAR logic module and the second SAR logic module are connected with the output of the comparator; the first grid voltage bootstrap switch and the second grid voltage bootstrap switch are used for respectively sampling differential input signals to upper plates of a first capacitor array and a second capacitor array, the comparator is used for comparing the upper plate sampling signals, the first SAR logic module and the second SAR logic module are used for changing the voltage of the upper plates of the capacitors with weights corresponding to the first capacitor array and the second capacitor array according to the comparison result of the comparator, the first SAR logic module and the second SAR logic module obtain a first-stage quantization result after the quantization is finished, and the first-stage quantization result is transmitted to the MDAC module;

the MDAC module comprises a first SH and LATCH module, a second SH and LATCH module, an amplifier, a third capacitor array and a fourth capacitor array, wherein the first SH and LATCH module and the second SH and LATCH module comprise a grid voltage bootstrap switch and a LATCH circuit, the first SH and LATCH module and the second SH and LATCH module are respectively connected with a differential input signal and sample the differential input signal simultaneously with the first-stage SAR ADC, the first SH and LATCH module and the second SH and LATCH module store a received first-stage quantization result through the LATCH circuit, the MDAC module carries out residual subtraction on a self-sampling signal and the first-stage quantization result so as to form residual voltage on the third capacitor array and the fourth capacitor array, and the residual voltage is amplified by the amplifier and then transmitted to the second-stage SAR ADC;

the second SAR ADC is a 9-bit SAR ADC, and the input amplified signal is quantized to obtain a final quantization result.

Images