CN110190849A - A kind of gradual approaching A/D converter - Google Patents
A kind of gradual approaching A/D converter Download PDFInfo
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- CN110190849A CN110190849A CN201910305819.1A CN201910305819A CN110190849A CN 110190849 A CN110190849 A CN 110190849A CN 201910305819 A CN201910305819 A CN 201910305819A CN 110190849 A CN110190849 A CN 110190849A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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- Analogue/Digital Conversion (AREA)
Abstract
The present invention discloses a kind of gradual approaching A/D converter, comprising: the input terminal of the first bootstrapped switch is connect with the first signal input part, and the input terminal of the second bootstrapped switch is connect with second signal input terminal；The first input end of differential capacitance array is connect with the output end of the first bootstrapped switch, second input terminal of differential capacitance array is connect with the output end of the second bootstrapped switch, first output end of differential capacitance array and the first non-inverting input terminal of comparator connect, and the second output terminal of differential capacitance array and the first inverting input terminal of comparator connect；The signal output end of comparator is connect with the signal input part of SAR logic module, and the ready signal output end of comparator is connect with the ready signal input part of SAR logic module, and the signal output end of SAR logic module and the input terminal of register connect；The control signal output of SAR logic module is connect with the control signal input of differential capacitance array.The present invention is low in energy consumption, structure is simple.
Description
Technical field
The invention belongs to digital-to-analogue conversion fields, and in particular to a kind of gradual approaching A/D converter.
Background technique
It is also higher and higher that the rapid development of digital technology in recent years results in requirement of the various systems to analog-digital converter, newly
The modulus conversion technique of type continues to bring out.
The noise shaping techniques of Sigma-Delta ADC are combined with SAR ADC, can SAR in high-resolution applications
In limitation.High-precision application can be realized under the premise of guaranteeing low-power consumption.
Presently, there are noise shaping SAR ADC structure in, can be from SAR in the framework fed back there is only error
Quantization error Q is taken out on the pole plate of the capacitor array of ADC.But when there are feedforward path, it is being taken out on capacitor array and
It is not quantization error, this makes during realizing noise transfer function (NTF), and there is more limitations.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of conversions of successive approximation modulus
Device.The technical problem to be solved in the present invention is achieved through the following technical solutions:
A kind of gradual approaching A/D converter, comprising: the first signal input part, second signal input terminal, the first bootstrapping
Switch, the second bootstrapped switch, differential capacitance array, comparator, SAR logic module and register；
The input terminal of first bootstrapped switch is connect with first signal input part, second bootstrapped switch it is defeated
Enter end to connect with the second signal input terminal；
The differential capacitance array is set to first bootstrapped switch and second bootstrapped switch and the comparator
Between, the first input end of the differential capacitance array is connect with the output end of first bootstrapped switch, the differential capacitance
Second input terminal of array is connect with the output end of second bootstrapped switch, the first output end of the differential capacitance array with
First non-inverting input terminal of the comparator connects, the second output terminal of the differential capacitance array and the first of the comparator
Inverting input terminal connection；
The signal output end of the comparator is connect with the signal input part of the SAR logic module, the comparator
Ready signal output end is connect with the ready signal input part of the SAR logic module, and the signal of the SAR logic module is defeated
Outlet is connect with the input terminal of the register；The control signal output of the SAR logic module and the differential capacitance battle array
The control signal input of column connects.
It in one embodiment of the invention, further include the first feedforward path module and the second feedforward path module, it is described
The input terminal of first feedforward path module is connect with the more than first difference signal output end of the differential capacitance array, before described first
The first output end, the second output terminal for presenting channel module are same mutually defeated with the second non-inverting input terminal of the comparator, third respectively
Enter end connection；More than second difference signal output end of the input terminal of the second feedforward path module and the differential capacitance array connects
Connect, the third output end of the second feedforward path module, the 4th output end respectively with the second anti-phase input of the comparator
End, the connection of third inverting input terminal.
In one embodiment of the invention, the differential capacitance array includes first capacitor device array and the second capacitor
Array；The output end of first capacitor device array described in the input terminal and the first signal input part of the first capacitor device array and institute
State the first non-inverting input terminal connection of comparator；The input terminal of second array of capacitors and the second signal input terminal connect
It connects, the output end of second array of capacitors is connect with the first inverting input terminal of the comparator；The SAR logic module
Control signal output include first control signal output end and second control signal output end, the first control signal is defeated
Outlet and the second control signal output end are connect with the first capacitor device array and second array of capacitors respectively.
In one embodiment of the invention, the first feedforward path module and the second feedforward path module are wrapped
Include noise coupling loop, FIR filter circuit, iir filter circuit, the FIR filter electricity of the first feedforward path module
The weighted capacitors group C of the input terminal on road and the first capacitor device array0、C1...CN-2Top crown, second capacitor
The redundant capacitor C of arrayRTop crown connection, the first output end of the FIR filter circuit of the first feedforward path module
It is connect with the first input end of noise coupling loop, the second output of the FIR filter circuit of the first feedforward path module
End is connect with the input terminal of the iir filter, and the of the first output end of the iir filter and the noise coupling loop
The connection of two input terminals, the output end of the noise coupling loop are connect with the third non-inverting input terminal of the comparator, the FIR
The second output terminal of filter is connect with the second noninverting input of the comparator；The FIR of the second feedforward path module
The weighted capacitors group C of the input terminal of filter circuit and second array of capacitors0、C1...CN-2Top crown, described
The redundant capacitor C of two array of capacitorsRTop crown connection, the of the FIR filter circuit of the second feedforward path module
One output end is connect with the first input end of the noise coupling loop, the FIR filter electricity of the second feedforward path module
The second output terminal on road is connect with the input terminal of the iir filter, the first output end and the noise of the iir filter
Second input terminal of coupling loop connects, the output end of the noise coupling loop and the third inverting input terminal of the comparator
Connection, the second output terminal of the FIR filter are connect with the second inverting input terminal of the comparator.
In one embodiment of the invention, further include decimation filter, the input terminal of the decimation filter with it is described
The output end of register connects.
In one embodiment of the invention, the first capacitor device array, second array of capacitors include: superfluous
Remaining capacitor CR, several weighted capacitors group C being successively connected in parallel0、C1...CN-1, it is C that wherein redundant capacitor, which is capacitance, the
One weighted capacitors group includes the capacitor that a capacitance is C；Second weighted capacitors group C2It is 2C's including a capacitance
Capacitor；N-1 weighted capacitors group includes capacitor CN-1, capacitance 2N-1C, N >=2.
In one embodiment of the invention, the weighted capacitors group C of the first capacitor device array0、C1...CN-2It is upper
The redundant capacitor C of pole plate, the first capacitor device arrayRTop crown connect the first signal input part, the first capacitor device battle array
The weighted capacitors group C of column0、C1...CN-2Bottom crown connect the first single pole multiple throw group SN, first hilted broadsword more throw out
Pass group SN selective connection power end Vref, reference power source end VcmOr ground terminal GND, the redundant electric of the first capacitor device array
Hold CRReference power source end Vcm, the control signal output of the SAR logic module and the first single pole multiple throw group SN
Connection.
In one embodiment of the invention, the weighted capacitors group C of second array of capacitors0、C1...CN-2It is upper
The redundant capacitor C of pole plate, second array of capacitorsRTop crown connect second signal input terminal, the second capacitor battle array
The weighted capacitors group C of column0、C1...CN-2Bottom crown connect the second single pole multiple throw group SP, second hilted broadsword more throw out
Pass group SP selective connection power end Vref, reference power source end VcmOr ground terminal GND, the redundant electric of second array of capacitors
Hold CRReference power source end Vcm, the control signal output of the SAR logic module and the second single pole multiple throw group SP
Connection.
In one embodiment of the invention, the first capacitor device array further includes the first signaling switch Sin, described
One single pole multiple throw group SN passes through the first signaling switch SinWith the weighted capacitors group C of the first capacitor device array0、
C1...CN-2Bottom crown connection.
In one embodiment of the invention, second array of capacitors further includes second signal switch Sip, described
Two single pole multiple throw group SP pass through the second signal switch SipWith the weighted capacitors group C of second array of capacitors0、
C1...CN-2Bottom crown connection.
Beneficial effects of the present invention:
Gradual approaching A/D converter of the invention is realized by differential capacitance array, comparator and SAR logic module
Three rank noise shaping gradual approaching A/D converters, so that analog-digital converter is low in energy consumption, structure is simple.Also add feedforward
Channel module, the error amount that can be quantified by feed-forward module, and noise transfer function is promoted by quantization error Q
(NTF) order, to realizing feedforward with error feedback arrangement knot merga pass noise coupling technology in original two rank
On the basis of increase single order noise shaping, thus realize three rank shapings.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of gradual approaching A/D converter provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram for gradual approaching A/D converter that another embodiment of the invention provides；
Fig. 3 is a kind of circuit of the first feedforward path of gradual approaching A/D converter module provided in an embodiment of the present invention
Schematic diagram；
Fig. 4 is a kind of circuit of the second feedforward path of gradual approaching A/D converter module provided in an embodiment of the present invention
Schematic diagram；
Fig. 5 is a kind of timing diagram of gradual approaching A/D converter provided in an embodiment of the present invention；
Fig. 6 is a kind of signal flow diagram of gradual approaching A/D converter provided in an embodiment of the present invention；
Fig. 7 is the signal stream that a kind of gradual approaching A/D converter provided in an embodiment of the present invention extracts quantization error
Figure；
Fig. 8 is the concrete signal that a kind of gradual approaching A/D converter provided in an embodiment of the present invention extracts quantization error
Flow graph；
Fig. 9 is a kind of baud of the noise transfer function of gradual approaching A/D converter provided in an embodiment of the present invention
Figure.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Referring to Figure 1, Fig. 1 is a kind of structural representation of gradual approaching A/D converter provided in an embodiment of the present invention
Figure, a kind of gradual approaching A/D converter, comprising: the first signal input part, second signal input terminal, the first bootstrapped switch,
Second bootstrapped switch, differential capacitance array, comparator, SAR logic module and register；
The input terminal of first bootstrapped switch is connect with first signal input part, second bootstrapped switch it is defeated
Enter end to connect with the second signal input terminal；
The differential capacitance array is set to first bootstrapped switch and second bootstrapped switch and the comparator
Between, the first input end of the differential capacitance array is connect with the output end of first bootstrapped switch, the differential capacitance
Second input terminal of array is connect with the output end of second bootstrapped switch, the first output end of the differential capacitance array with
First non-inverting input terminal of the comparator connects, the second output terminal of the differential capacitance array and the first of the comparator
Inverting input terminal connection；
The signal output end of the comparator is connect with the signal input part of the SAR logic module, the comparator
Ready signal output end is connect with the ready signal input part of the SAR logic module, and the signal of the SAR logic module is defeated
Outlet is connect with the input terminal of the register；The control signal output of the SAR logic module and the differential capacitance battle array
The control signal input of column connects.
Specifically, the first signal input part, second signal input terminal are respectively used to generate the first input signal VinWith second
Input signal Vip, the first bootstrapped switch is to the first input signal VinIt is sampled to obtain the first discrete analog signal VXN and be sent
To differential capacitance array, the second bootstrapped switch is to the second input signal VipIt is sampled to obtain the second discrete analog signal VXP simultaneously
It is sent to differential capacitance array, comparator, which passes through, will sample the first discrete analog signal VXN on differential capacitance array and the
Two discrete analog signal VXP are compared, and export comparison result Di, and the ready signal output end of comparator is defeated at the same time
Ready signal out, and change difference to control SAR logic module and store comparison result Di and generate control signal
Voltage value on capacitor array is used to be compared next time, and SAR logic module is obtained according to comparison result Di for controlling difference
Divide value of the control signal Ctr of capacitor array to control VXP and VXN on differential capacitance array, when comparator completes 9 comparisons
Afterwards, register exports the comparison result D8-D0 of n times under same clock control.
Fig. 2 is referred to, Fig. 2 is a kind of structure for gradual approaching A/D converter that another embodiment of the invention provides
Schematic diagram further includes in one embodiment of the invention the first feedforward path module and the second feedforward path module, and described
The input terminal of one feedforward path module is connect with the more than first difference signal output end of the differential capacitance array, first feedforward
First output end of channel module, second output terminal respectively with the second non-inverting input terminal of the comparator, third homophase input
End connection；More than second difference signal output end of the input terminal of the second feedforward path module and the differential capacitance array connects
Connect, the third output end of the second feedforward path module, the 4th output end respectively with the second anti-phase input of the comparator
End, the connection of third inverting input terminal.
In one embodiment of the invention, the differential capacitance array includes first capacitor device array and the second capacitor
Array；The output end of first capacitor device array described in the input terminal and the first signal input part of the first capacitor device array and institute
State the first non-inverting input terminal connection of comparator；The input terminal of second array of capacitors and the second signal input terminal connect
It connects, the output end of second array of capacitors is connect with the first inverting input terminal of the comparator；The SAR logic module
Control signal output include first control signal output end and second control signal output end, the first control signal is defeated
Outlet and the second control signal output end are connect with the first capacitor device array and second array of capacitors respectively.
Specifically, capacitor Ca、Cb….ClCapacitance be respectively as follows: 18C, 30C, 30C, 30C, 20C, 30C, 12C, 2C, 1C,
Wherein C is unit capacitor by 20C, 1C, 30C.
In one embodiment of the invention, the first feedforward path module and the second feedforward path module are wrapped
Include noise coupling loop, FIR filter circuit, iir filter circuit, the FIR filter electricity of the first feedforward path module
The weighted capacitors group C of the input terminal on road and the first capacitor device array0、C1...CN-2Top crown, second capacitor
The redundant capacitor C of arrayRTop crown connection, the first output end of the FIR filter circuit of the first feedforward path module
It is connect with the first input end of noise coupling loop, the second output of the FIR filter circuit of the first feedforward path module
End is connect with the input terminal of the iir filter, and the of the first output end of the iir filter and the noise coupling loop
The connection of two input terminals, the output end of the noise coupling loop are connect with the third non-inverting input terminal of the comparator, the FIR
The second output terminal of filter is connect with the second noninverting input of the comparator；The FIR of the second feedforward path module
The weighted capacitors group C of the input terminal of filter circuit and second array of capacitors0、C1...CN-2Top crown, described
The redundant capacitor C of two array of capacitorsRTop crown connection, the of the FIR filter circuit of the second feedforward path module
One output end is connect with the first input end of the noise coupling loop, the FIR filter electricity of the second feedforward path module
The second output terminal on road is connect with the input terminal of the iir filter, the first output end and the noise of the iir filter
Second input terminal of coupling loop connects, the output end of the noise coupling loop and the third inverting input terminal of the comparator
Connection, the second output terminal of the FIR filter are connect with the second inverting input terminal of the comparator.
Specifically, as shown in Figure 3 and Figure 4, the first feedforward path module and the second feedforward path module include 21
A switch S1、S2、S3…….S19With 5 reset switch SR1、SR2、SR3、SR4、SR5, capacitor Ca、Cb、Cc、Cd、Ce、Cf、Cg、Ch、
Ci、Cj、Ck、Cl, 40 times of amplifiers, 28 times of amplifiers, integrators.The weighting electricity of a termination first capacitor device array of switch S1
Container group C0、C1...CN-2Top crown, the first capacitor device array redundant capacitor CRTop crown connection, the other end with
The input terminal connection of 40 times of amplifiers, the output end and switch S of 40 times of amplifiers3One end connection, switch S3The other end and electricity
Hold ChTop crown connection, capacitor ChBottom crown ground connection；Switch S2One end and capacitor ChTop crown connection, the other end with
Capacitor CiTop crown connection, capacitor CiBottom crown ground connection；First reset switch SR1One end and capacitor CiTop crown connect
It connects, other end ground connection；The anti-phase output end switch S of 40 times of amplifiers4One end connection, switch S4The other end and capacitor Ca's
Top crown connection, capacitor CaBottom crown ground connection；Switch S6A termination capacitor CaTop crown, the other end and capacitor CbIt is upper
Substrate connection, capacitor CbBottom crown ground connection；The output end of 40 times of amplifiers also with switch S7One end connection, switch S7It is another
One end respectively with switch S5One end, capacitor CcTop crown connection, switch S5The other end and capacitor CbTop crown connection, electricity
Hold CcBottom crown ground connection；Switch S13A termination capacitor CcTop crown, it is another termination 28 times of amplifiers input terminal, 28 times
The output end and switch S of amplifier14One end connection, switch S14The other end and capacitor CjTop crown connection, capacitor Cj's
Bottom crown ground connection；Switch S14One end connect with the top crown of capacitor Cj, the other end and capacitor CkTop crown connection, capacitor Ck
Bottom crown ground connection；Third reset switch SR3A termination capacitor CkTop crown, other end ground connection；Switch S18A termination capacitor
CkTop crown, the input terminal of the other end and integrator connects, the output end of integrator and the third non-inverting input terminal of comparator
Connection (the third inverting input terminal of the output end of integrator and comparator connects in the second feedforward path module)；5th reset is opened
Close SR5A termination capacitor CbTop crown, the other end ground connection；The S of second reset switchR2A termination capacitor CdTop crown,
Other end ground connection；Capacitor CdBottom crown ground connection；Switch S8A termination capacitor CdTop crown, another termination capacitor CcIt is upper
Pole plate；Switch S16A termination capacitor CdTop crown, another termination capacitor CeTop crown, capacitor CeBottom crown ground connection；Switch
S15A termination capacitor Ce, the output end of 28 times of amplifiers of another termination；Switch S19A termination capacitor CiTop crown, it is another
Termination capacitor CkTop crown；Switch S12A termination capacitor CcTop crown, another termination capacitor ClTop crown, capacitor ClUnder
Pole plate ground connection, capacitor ClTop crown (C in the second feedforward path module is also connect with the second non-inverting input terminal of comparatorlIt is upper
Second inverting input terminal of pole plate and comparator connection)；Switch S9A termination capacitor CcTop crown, another termination capacitor Cf
Top crown, capacitor CfBottom crown ground connection；4th reset switch SR4A termination capacitor CfTop crown, the other end ground connection；
Switch S10A termination capacitor CfTop crown, another termination capacitor CgTop crown, capacitor CgBottom crown ground connection；Switch S11's
One termination capacitor CgTop crown, it is another termination 28 times of amplifiers reversed-phase output.
In one embodiment of the invention, further include decimation filter, the input terminal of the decimation filter with it is described
The output end of register connects.
Specifically, due to the embodiment of the present invention by the way of over-sampling to the first input signal and the second input signal into
Row sampling, it is therefore desirable to which decimation filter carries out the operation that drop is adopted and filtered to output result.
In one embodiment of the invention, the first capacitor device array, second array of capacitors include: superfluous
Remaining capacitor CR, several weighted capacitors group C being successively connected in parallel0、C1...CN-1, it is C that wherein redundant capacitor, which is capacitance, the
One weighted capacitors group includes the capacitor that a capacitance is C；Second weighted capacitors group C2It is 2C's including a capacitance
Capacitor；N-1 weighted capacitors group includes capacitor CN-1, capacitance 2N-1C, N >=2.
In one embodiment of the invention, the weighted capacitors group C of the first capacitor device array0、C1...CN-2It is upper
The redundant capacitor C of pole plate, the first capacitor device arrayRTop crown connect the first signal input part, the first capacitor device battle array
The weighted capacitors group C of column0、C1...CN-2Bottom crown connect the first single pole multiple throw group SN, first hilted broadsword more throw out
Pass group SN selective connection power end Vref, reference power source end VcmOr ground terminal GND, the redundant electric of the first capacitor device array
Hold CRReference power source end Vcm, the control signal output of the SAR logic module and the first single pole multiple throw group SN
Connection.
In one embodiment of the invention, the weighted capacitors group C of second array of capacitors0、C1...CN-2It is upper
The redundant capacitor C of pole plate, second array of capacitorsRTop crown connect second signal input terminal, the second capacitor battle array
The weighted capacitors group C of column0、C1...CN-2Bottom crown connect the second single pole multiple throw group SP, second hilted broadsword more throw out
Pass group SP selective connection power end Vref, reference power source end VcmOr ground terminal GND, the redundant electric of second array of capacitors
Hold CRReference power source end Vcm, the control signal output of the SAR logic module and the second single pole multiple throw group SP
Connection.
Specifically, first capacitor device array includes 9 weighted capacitance groups, therefore, available first weighted capacitors
The capacitance of group is C, the capacitance of the second weighted capacitors group is 2C, the capacitance of third weighted capacitors group is 4C, the 4th
The capacitance of weighted capacitors group is 8C, the capacitance of the 5th weighted capacitors group is the capacitor of 16C, the 6th weighted capacitors group
Amount is 32C, the capacitance of the 7th weighted capacitors group is 64C, the capacitance of the 8th weighted capacitors group is 128C, the 9th weighting
The capacitance of capacitor group is 256C, redundant capacitor CRCapacitance be C.
In one embodiment of the invention, the first capacitor device array further includes the first signaling switch Sin, described
One single pole multiple throw group SN passes through the first signaling switch SinWith the weighted capacitors group C of the first capacitor device array0、
C1...CN-2Bottom crown connection.
In one embodiment of the invention, second array of capacitors further includes second signal switch Sip, described
Two single pole multiple throw group SP pass through the second signal switch SipWith the weighted capacitors group C of second array of capacitors0、
C1...CN-2Bottom crown connection.
Further, as shown in figure 5, the embodiment of the invention also includes clock signals Sampled signalComparison clock signalFirst reset clock signalSecond reset clock signalThird reset clock signalFirst signal input part and second signal input terminal exist
Clock signalControl under, switch SinWith switch SipConducting, the sampling through the first bootstrapped switch and the second bootstrapped switch obtain
First discrete analog signal VXN and the second discrete analog signal VXP, and by the first discrete analog signal VXN and the second walk-off-mode
Quasi- signal VXP is kept on the first capacitor array and the second capacitor array of differential capacitance array；Comparator is when relatively
Clock signalControl under complete 9 comparisons, the obtained remaining difference Vres of quantization is stored in difference while exporting digital code
On capacitor array；In clock signalControl under, switch S1、S3、S4、S7Conducting, FIR filter are obtained from differential capacitance array
To remaining difference Vres, 40 times of amplifiers in the first feedforward path module or the second feedforward path module amplify remaining difference signal Vres
Capacitor C is stored in after 40 timesaWith capacitor CcAnd Ch；In clockControl under, switch S2、S5Conducting, capacitor CbWith capacitor CcIt is complete
Shared, the capacitor C at chargehWith capacitor CiIt is shared to complete charge；In clockControl under, switch S8、S19Conducting, capacitor Cc with
Capacitor CdIt is shared to complete charge, capacitor CiWith capacitor CkIt is shared to complete charge；In clockControl under, switch S6Conducting, electricity
Hold CcWith CfIt is shared to complete charge, capacitor CaWith capacitor CbIt is shared to complete charge, in addition, as shown, wrapping in feedforward path module
Include two identical CfModule, CfModule includes switch S9, switch S10, the 4th reset switch SR4With capacitor Cf, in clock signalControl under, and in same period, clock signalAlternately control switch S10On and off, and
Pass through the second reset clock signalThird reset clock signalTo capacitor CfIt is resetted, realizes single order delay function
Energy；In clockControl under, switch S12、S18Conducting, capacitor CcWith capacitor ClCharge is completed through switch conduction to share, and is realized
The function of First-order Integral, CkIntegrated device carries out single order true integral and accesses the third non-inverting input terminal of comparator (needing
That bright is Ca-ClIn, only capacitor ClEach period clearing is not needed, wherein connect with 40 times of amplifiers and 28 times of amplifiers
Capacitor Cc、Cl、CkIt is resetted by 40 times of amplifiers and 28 times of amplifiers, capacitor Ca-CkThen by the first reset clock signalSecond reset clock signalThird reset clock signalIt is resetted, so only capacitor Cl has integral function
Can)；In clockControl under, switch S11、S14、S15Conducting, 28 times of amplifiers are by capacitor CcThe charge of upper storage carries out 28 times
Amplify and amplification result is stored in 28 times of amplifier outs；In clockControl under, switch S16、S10、S17Conducting, Cd
With CeIt is shared to complete charge, CfWith CgIt is shared to complete charge, CjWith CkIt is shared to complete charge, in addition, in different cycles, clock To switch S9、S10Alternately control is carried out, realizes the function of single order delay.After each end cycle, resetted first
Clock signalControl under reset switch SR1、SR2、SR3、SR5Conducting.
Specifically, the relational expression at each signal node are as follows:
As shown in fig. 6, Vin (z)+Vint(z)z-1+(1+z-1) Q=Dout (z), wherein Vin (z) is input signal in the domain Z
The form of expression, Vint (z) be remaining difference signal Vres in the form of expression after transfer function H (z), Q is quantization error,
Dout (z) is the form of expression of the output signal in the domain Z；Vres (z)=Vin (z)-Dout (z), Vint (z)=Vres (z) H
(z),Wherein, H (z) is the form of expression of the transfer function on feedforward path in the domain z,
It is available according to above formula, as shown in Figure 7 and Figure 8,
Specifically, integrate and can obtain by the way that the voltage of node Vres and the Vint node of last moment to be mutually added in
To the opposite number of the error Q in this period, is performed corresponding processing by the quantization error Q that will be obtained and mentioned on the basis of original
Rise the order of noise transfer function NTF.By the way that the value of obtained quantization error is directly connected to comparator input terminal, realize
Single order noise shaping is increased on the original basis.
Specifically, as shown in figure 9, the transfer function that noise coupling loop is realized is H1(z)=1-z-1.With do not increase noise
The Bode diagram of coupling loop noise transfer function NTF compares, and increases ADC in the case where noise coupling loop noise transmission function
There can be the rejection ability of additional 20dB to low-frequency noise, improve the effect of single order noise shaping, therefore obtain noise biography
The expression formula of delivery function are as follows:
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (10)
1. a kind of gradual approaching A/D converter characterized by comprising the first signal input part, second signal input terminal,
First bootstrapped switch, the second bootstrapped switch, differential capacitance array, comparator, SAR logic module and register；
The input terminal of first bootstrapped switch is connect with first signal input part, the input terminal of second bootstrapped switch
It is connect with the second signal input terminal；
The differential capacitance array is set between first bootstrapped switch and second bootstrapped switch and the comparator,
The first input end of the differential capacitance array is connect with the output end of first bootstrapped switch, the differential capacitance array
Second input terminal is connect with the output end of second bootstrapped switch, the first output end of the differential capacitance array and the ratio
The first non-inverting input terminal compared with device connects, and the second output terminal of the differential capacitance array and the first reverse phase of the comparator are defeated
Enter end connection；
The signal output end of the comparator is connect with the signal input part of the SAR logic module, the ready of the comparator
Signal output end is connect with the ready signal input part of the SAR logic module, the signal output end of the SAR logic module
It is connect with the input terminal of the register；The control signal output of the SAR logic module and the differential capacitance array
Control signal input connection.
2. a kind of gradual approaching A/D converter according to claim 1, which is characterized in that further include feedthrough before first
The first of road module and the second feedforward path module, the input terminal of the first feedforward path module and the differential capacitance array
The connection of remaining difference signal output end, the first output end of the first feedforward path module, second output terminal are respectively compared with described
Second non-inverting input terminal of device, the connection of third non-inverting input terminal；The input terminal of the second feedforward path module and the difference
More than second difference signal output end of capacitor array connects, third output end, the 4th output end of the second feedforward path module
It is connect respectively with the second inverting input terminal of the comparator, third inverting input terminal.
3. a kind of gradual approaching A/D converter according to claim 1, which is characterized in that the differential capacitance array
Including first capacitor device array and the second array of capacitors；The input terminal and the first signal input part of the first capacitor device array
The output end of the first capacitor device array is connect with the first non-inverting input terminal of the comparator；Second array of capacitors
Input terminal connect with the second signal input terminal, the first of the output end of second array of capacitors and the comparator
Inverting input terminal connection；The control signal output of the SAR logic module includes first control signal output end and the second control
Signal output end processed, the first control signal output end and the second control signal output end respectively with the first capacitor
Device array is connected with second array of capacitors.
4. a kind of gradual approaching A/D converter according to claim 2, which is characterized in that first feedforward path
Module and the second feedforward path module include noise coupling loop, FIR filter circuit, iir filter circuit, described
Weighted capacitors group (the C of the input terminal of the FIR filter circuit of first feedforward path module and the first capacitor device array0、
C1...CN-2) top crown, second array of capacitors redundant capacitor (CR) top crown connection, feedthrough before described first
First output end of the FIR filter circuit of road module is connect with the first input end of noise coupling loop, first feedforward
The second output terminal of the FIR filter circuit of channel module is connect with the input terminal of the iir filter, the iir filter
The first output end connect with the second input terminal of the noise coupling loop, the output end of the noise coupling loop with it is described
The third non-inverting input terminal of comparator connects, and the second of the second output terminal of the FIR filter and the comparator is in the same direction defeated
Enter end connection；The input terminal of the FIR filter circuit of the second feedforward path module adds with second array of capacitors
Weigh capacitor group (C0、C1...CN-2) top crown, second array of capacitors redundant capacitor (CR) top crown connection,
The first input end of first output end of the FIR filter circuit of the second feedforward path module and the noise coupling loop
Connection, the second output terminal of the FIR filter circuit of the second feedforward path module and the input terminal of the iir filter connect
It connects, the first output end of the iir filter is connect with the second input terminal of the noise coupling loop, the noise coupling ring
The output end on road is connect with the third inverting input terminal of the comparator, the second output terminal of the FIR filter and the ratio
The second inverting input terminal compared with device connects.
5. a kind of gradual approaching A/D converter according to claim 2, which is characterized in that further include filtering extraction
Device, the input terminal of the decimation filter are connect with the output end of the register.
6. a kind of gradual approaching A/D converter according to claim 3, which is characterized in that the first capacitor device battle array
Column, second array of capacitors include: redundant capacitor (CR), several weighted capacitors group (C being successively connected in parallel0、
C1...CN-1), it is C that wherein redundant capacitor, which is capacitance, and the first weighted capacitors group includes the capacitor that a capacitance is C；The
Two weighted capacitors group C2The capacitor for being 2C including a capacitance；N-1 weighted capacitors group includes capacitor CN-1, capacitance
It is 2N-1C, N >=2.
7. a kind of gradual approaching A/D converter according to claim 6, which is characterized in that the first capacitor device battle array
Weighted capacitors group (the C of column0、C1...CN-2) top crown, the first capacitor device array redundant capacitor (CR) top crown
Meet the first signal input part, the weighted capacitors group (C of the first capacitor device array0、C1...CN-2) bottom crown connection first
Single pole multiple throw group (SN), the first single pole multiple throw group (SN) selective connection power end (Vref), reference power source end
(Vcm) or ground terminal (GND), the redundant capacitor (C of the first capacitor device arrayR) reference power source end (Vcm), the SAR is patrolled
The control signal output for collecting module is connect with the first single pole multiple throw group (SN).
8. a kind of gradual approaching A/D converter according to claim 6, which is characterized in that the second capacitor battle array
Weighted capacitors group (the C of column0、C1...CN-2) top crown, second array of capacitors redundant capacitor (CR) top crown
Meet second signal input terminal, the weighted capacitors group (C of second array of capacitors0、C1...CN-2) bottom crown connection second
Single pole multiple throw group (SP), the second single pole multiple throw group (SP) selective connection power end (Vref), reference power source end
(Vcm) or ground terminal (GND), the redundant capacitor (C of second array of capacitorsR) reference power source end (Vcm), the SAR is patrolled
The control signal output for collecting module is connect with the second single pole multiple throw group (SP).
9. a kind of gradual approaching A/D converter according to claim 7, which is characterized in that the first capacitor device battle array
Column further include the first signaling switch (Sin), the first single pole multiple throw group (SN) passes through the first signaling switch (Sin)
With the weighted capacitors group (C of the first capacitor device array0、C1...CN-2) bottom crown connection.
10. a kind of gradual approaching A/D converter according to claim 8, which is characterized in that second capacitor
Array further includes second signal switch (Sip), the second single pole multiple throw group (SP) is switched by the second signal
(Sip) with the weighted capacitors group (C of second array of capacitors0、C1...CN-2) bottom crown connection.
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