CN107491136B - A kind of difference type capacity regulator for digital calibration - Google Patents
A kind of difference type capacity regulator for digital calibration Download PDFInfo
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- CN107491136B CN107491136B CN201710546176.0A CN201710546176A CN107491136B CN 107491136 B CN107491136 B CN 107491136B CN 201710546176 A CN201710546176 A CN 201710546176A CN 107491136 B CN107491136 B CN 107491136B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
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Abstract
The invention belongs to the digital calibration techniques field of integrated circuit, specially a kind of difference type capacity regulator for digital calibration.Capacity regulator provided by the invention, including a pair of of capacitor array, a pair of input calibration code and a pair of output；It adjusts bulky capacitor subarray and small capacitances subarray in different capacitor arrays by input calibration code simultaneously, and the difference of capacitor in a pair of output is made to be equal to the integral multiple of large and small capacitor cell difference；The difference of large and small capacitor cell is less than the capacitor minimum value that can be manufactured under given process, thus the problem of adjusting granularity for alleviating calibration is limited to manufacturing process.The present invention effectively improves the precision of digital calibration.
Description
Technical field
The invention belongs to the data calibration technical fields of integrated circuit, and in particular to integrated circuit for digital calibration
Difference type capacity regulator.
Background technique
Digital calibration is widely used among the design of various high-precision integrated circuits, it be one by circuit to be calibrated,
Detect the degeneration factor that controller, calibration code generator, four, adjuster are partially constituted.Wherein, adjuster passes through input school
Quasi- code to needing matched one or more pairs of paths to be adjusted in circuit to be calibrated, and adjusts granularity and is decided by adjuster institute
The minimal difference for the physical quantity (such as: capacitance) being adjustable.
The well known capacity regulator for digital calibration, as shown in Figure 1, comprising: a pair of of capacitor array (100 and 200),
A pair of input calibration code (CALP<N:1>and CALN<N:1>) and a pair of output (OUTP and OUTN)；Each capacitor array
Including M equal-sized capacitor cells, each capacitor is connected by independent switch with the output end of the capacitor array；One
Switch in a pair of of capacitor array is controlled respectively to input calibration code.
Shown in Fig. 2, as M=7, input calibration code to the adjusting situation of the output capacitor of known capacity regulator,
In: the minimum capacity C that can be manufacturedminArea is 0.25um*0.25um, and each capacitor cell be minimum capacity (i.e.:
CP1=CP2=...=CPM=CN1=CN2=...=CNM=Cmin)；Horizontal axis positive direction indicates the increased direction calibration code CALP<N:1>, horizontal axis
Negative direction indicates the increased direction calibration code CALN<N:1>.When forward direction is adjusted, the capacitor on only output end OUTP is with school
The increase of quasi- code and increase, and the capacitor on output end OUTN remains unchanged；When negative regulation, on only output end OUTN
Capacitor increases with the increase of calibration code, and the capacitor on output end OUTP remains unchanged.So the adjusting grain calibrated at this time
Degree is decided by capacitor cell.
The well known capacity regulator for digital calibration, its shortcoming is that: it is decided by capacitor cell due to adjusting granularity
Value, and for specifying manufacturing process, the capacitor that can be manufactured is there are minimum value, therefore the adjusting granularity of well known capacity regulator
It is limited to the manufacturing process of capacitor.
Summary of the invention
There is adjusting granularity for the above-mentioned well known capacity regulator for digital calibration and is limited to capacitor cell manufacture
The problem of technique, provides a kind of difference type capacity regulator for digital calibration, it is adjusted simultaneously by inputting calibration code
Bulky capacitor subarray and small capacitances subarray in different capacitor arrays, are equal to the difference of capacitor in a pair of output
The integral multiple of large and small capacitor cell difference；The difference of large and small capacitor cell is less than the capacitor that can be manufactured under given process most
Small value, thus the problem of adjusting granularity for alleviating calibration is limited to manufacturing process.Therefore, the present invention effectively improves number
The precision of calibration.
Provided by the present invention for the difference type capacity regulator of digital calibration, as shown in Fig. 2, including a pair of of capacitor array
(100 and 200), a pair of input calibration code (CALP<N:1>and CALN<N:1>) and a pair of output (OUTP and OUTN)；It is described
A pair of of capacitor array structure having the same, including a bulky capacitor subarray (101 or 201) and a small capacitances subarray
(102 or 202)；Bulky capacitor subarray (101 or 201) includes M HI-C cell (CBk, k=1,2 ..., M), small capacitances submatrix
Arranging (102 or 202) includes M small capacitances unit (CSk, k=1,2 ..., M), each capacitor cell is connected by independent switch
It is connected to the output end (OUTP or OUTN) of respective capacitor array.
In above scheme, the 2M HI-C cell is equal in magnitude, and 2M small capacitances cell size is equal；Bulky capacitor
Difference between unit and small capacitances unit is a fixed value, and this fixed value is less than and can manufacture under given process
Capacitor minimum value.
In above scheme, a switch can only be controlled by a calibration code；A pair of input calibration code is as follows to electricity
The switch held in array is controlled:
(1) when a pair of of input calibration code is a pair of of thermometer-code, N=M, each calibration code controls two and opens
Close: n-th of the first calibration code (CALP<N:1>) controls in first capacitor array (100) in bulky capacitor subarray (101) simultaneously
N-th of HI-C cell switch and the second capacitor array (200) in n-th of small capacitances in small capacitances subarray (202)
The switch of unit；N-th of second calibration code (CALN<N:1>) controls small capacitances submatrix in first capacitor array (100) simultaneously
Arrange n-th in the switch and the second capacitor array (200) of n-th of small capacitances unit in (102) in bulky capacitor subarray (201)
The switch of a HI-C cell；
(2) when a pair of of input calibration code is a pair of of binary code, N=log2(M+1), each weight is W's
The switch number of calibration code control is that weight is the position of W while controlling first capacitor battle array in the 2W: the first calibration code (CALP<N:1>)
Arrange the W switch and the second capacitor array (200) medium and small electricity of W HI-C cell in (100) in bulky capacitor subarray (101)
Hold W switch of W small capacitances unit in subarray (202)；Weight is that the position of W is same in second calibration code (CALN<N:1>)
When control first capacitor array (100) in W switch of W small capacitances unit in small capacitances subarray (102) and second electric
Hold W switch of W HI-C cell in array (200) in bulky capacitor subarray (201).
In above scheme, a pair of of capacitor array (100 and 200) is same under the control of a pair of of input calibration code
Moment at least a pair of bulky capacitor subarray and small capacitances subarray (101 and 202 or 201 Hes being in different capacitor arrays
102) all switches in all disconnect.
The problem of being limited to manufacturing process the beneficial effects of the invention are as follows the adjusting granularity for alleviating calibration, effectively improves
The precision of digital calibration.
Detailed description of the invention
Fig. 1 is the well known capacity regulator for digital calibration.
Fig. 2 is the well known capacity regulator for digital calibration, and a pair of output capacitance is closed with the variation of calibration code
System.
Fig. 3 is the difference type capacity regulator for digital calibration of the invention.
Fig. 4 is the difference type capacity regulator for digital calibration of the invention, and a pair of output capacitance is with calibration code
Variation relation.
Fig. 5 is that well-known technique and the technology of the present invention is respectively adopted, output capacitor difference with calibration code variation relation ratio
Relatively result.
Specific embodiment
In order to make it easy to understand, the present invention is described in detail below with reference to specific drawings and embodiments.It needs
It is noted that Fig. 3, Fig. 4 and Fig. 5 are only implementation examples of the invention, the specific implementation in scope of the invention as claimed
Form and details are not limited to Fig. 3, Fig. 4 and Fig. 5.For the personnel of any known IC design technology, it is known that institute of the present invention
State each example of Fig. 3, Fig. 4 and Fig. 5 can make a variety of different amendments and variation according to illustrating herein within the scope of the present invention,
These amendments and variation are also included in the scope of the present invention.
Fig. 3 is a kind of embodiment of the difference type capacity regulator for digital calibration of the invention, including a pair of of electricity
Hold array (100 and 200), a pair of input calibration code (CALP<N:1>and CALN<N:1>) and a pair of output (OUTP with
OUTN)；A pair of of capacitor array structure having the same, including a bulky capacitor subarray (101 or 201) and one small
Capacitor subarray (102 or 202)；Bulky capacitor subarray (101 or 201) includes M HI-C cell (CBk, k=1,2 ..., M),
Small capacitances subarray (102 or 202) includes M small capacitances unit (CSk, k=1,2 ..., M), each capacitor cell passes through only
Vertical switch is connected to the output end (OUTP or OUTN) of respective capacitor array.
2M above-mentioned HI-C cell is equal in magnitude, and 2M small capacitances cell size is equal；HI-C cell and small electricity
Holding the difference between unit is a fixed value △ C, and this fixed value △ C is less than the capacitor that can be manufactured under given process
Minimum value (Cmin)；That is:
CB1=CB2=...=CBM=CB
CS1=CS2=...=CSM=CS
△C=CB-CS<Cmin
Since the size of capacitor is proportional to the area of capacitor, it is possible to which the minimum capacity of manufacture is usually with its minimum area
To indicate.In the present embodiment, the capacitor minimum area that can be manufactured is 0.25um*0.25um: small capacitances cellar area takes most
Small value, it may be assumed that 0.25um*0.25um；And HI-C cell area is taken as 0.30um*0.25um；The difference of capacity area large and small in this way
Value is 0.05um*0.25um, is the 20% of the capacity area minimum value that can be manufactured.
One switch of above scheme can only be controlled by a calibration code；A pair of input calibration code is as follows to capacitor
Switch in array is controlled, by taking M=7 as an example:
(1) when a pair of of input calibration code is a pair of of thermometer-code, N=M=7, each calibration code controls two
Switch: n-th of the first calibration code (CALP<7:1>) controls bulky capacitor subarray (101) in first capacitor array (100) simultaneously
In n-th of HI-C cell switch and the second capacitor array (200) in n-th small electricity in small capacitances subarray (202)
Hold the switch of unit；N-th of second calibration code (CALN<7:1>) controls small capacitances in first capacitor array (100) simultaneously
In the switch and the second capacitor array (200) of n-th of small capacitances unit in array (102) in bulky capacitor subarray (201)
The switch of n-th of HI-C cell；
(2) when a pair of of input calibration code is a pair of of binary code, N=log2(M+1)=3, each weight is W
Calibration code control switch number be in the 2W: the first calibration code (CALP<3:1>) weight be W position and meanwhile control first capacitor
W switch of W HI-C cell in array (100) in bulky capacitor subarray (101) and the second capacitor array (200) are medium and small
W switch of W small capacitances unit in capacitor subarray (202)；Weight is the position of W in second calibration code (CALN<3:1>)
The W switch and second of W small capacitances unit in first capacitor array (100) in small capacitances subarray (102) is controlled simultaneously
W switch of W HI-C cell in capacitor array (200) in bulky capacitor subarray (201).
Above-mentioned a pair of of capacitor array (100 and 200) is under the control of a pair of of input calibration code, synchronization at least one
To all in the bulky capacitor subarray and small capacitances subarray (101 and 202 or 201 and 102) being in different capacitor arrays
Switch all disconnects.Therefore, as follows for inputting the requirement of calibration code: when inputting calibration code is a pair of 7 thermometer-codes, at least
Having a calibration code is 0000000；When inputting calibration code is a pair of 3 binary codes, at least one calibration code is 000.
Fig. 4 is adjusting feelings of the input calibration code to difference type capacity regulator output capacitor of the invention as M=7
Condition, in which: horizontal axis positive direction indicates the increased direction calibration code CALP<3:1>, and horizontal axis negative direction indicates calibration code CALN<3:1>
Increased direction.No matter it is positive adjust or negative regulation, the capacitor on a pair of output OUTP and OUTN is always with calibration
Code increase and increase；The difference is that when forward direction adjust when, due to it is increased on output end OUTP be HI-C cell, and
Increased on output end OUTN is small capacitances unit, so the speed that the former increases is faster；When negative regulation, due to output end
OUTP it is upper it is increased be small capacitances unit, and increased on output end OUTN is HI-C cell, so the speed that the latter increases
Faster.
Fig. 5 is as M=7, and when comparing using the technology of the present invention and well-known technique, a pair of output capacitive differential is with school
The variation relation of quasi- code.It can be seen that the smallest capacitive differential is exactly the minimum capacity that can be manufactured when using well-known technique
Value；And in the embodiment using the technology of the present invention, minimum capacity difference about can manufacture the 23% of position of minimum capacitance, therefore
So that being decided by that the adjusting granularity of minimum capacity difference accordingly becomes smaller, alleviates and adjusts the problem of granularity is limited to manufacturing process,
To improve the precision of digital calibration.
Claims (3)
1. a kind of difference type capacity regulator for digital calibration, which is characterized in that including a pair of of capacitor array (100 Hes
200), a pair of of input calibration code and a pair of output (OUTP and OUTN)；The pair of input calibration code is the first calibration code
CALP<N:1>and the second calibration code CALN<N:1>；A pair of of capacitor array structure having the same, including one big electricity
Hold subarray (101 or 201) and a small capacitances subarray (102 or 202)；Bulky capacitor subarray (101 or 201) includes M
HI-C cell CBk, k=1,2 ..., M, small capacitances subarray (102 or 202) includes M small capacitances unit CSk, k=1,
2 ..., M, each capacitor cell are connected to the output end (OUTP or OUTN) of respective capacitor array by independent switch；
The 2M HI-C cell is equal in magnitude, and 2M small capacitances cell size is equal；HI-C cell and small capacitances list
Difference between member is a fixed value, and this fixed value is less than the capacitor minimum value that can be manufactured under given process.
2. the difference type capacity regulator according to claim 1 for digital calibration, which is characterized in that a switch is only
It can be controlled by a calibration code；A pair of input calibration code as follows controls the switch in capacitor array:
(1) when a pair of of input calibration code is a pair of of thermometer-code, N=M, two switches of each calibration code control: the
N-th of one calibration code CALP<N:1>controls n-th in first capacitor array (100) in bulky capacitor subarray (101) simultaneously
N-th of small capacitances unit in the switch of HI-C cell and the second capacitor array (200) in small capacitances subarray (202) is opened
It closes；N-th of second calibration code CALN<N:1>controls in first capacitor array (100) in small capacitances subarray (102) simultaneously
N-th of bulky capacitor list in the switch and the second capacitor array (200) of n-th of small capacitances unit in bulky capacitor subarray (201)
The switch of member；
(2) when a pair of of input calibration code is a pair of of binary code, N=log2(M+1), each weight is the calibration of W
The switch number of code control is that weight is the position of W while controlling first capacitor array in the 2W: the first calibration code CALP<N:1>
(100) small capacitances in W switch of W HI-C cell in bulky capacitor subarray (101) and the second capacitor array (200)
W switch of W small capacitances unit in subarray (202)；Weight is the same time control in position of W in second calibration code CALN<N:1>
The W switch and the second capacitor battle array of W small capacitances unit in first capacitor array (100) processed in small capacitances subarray (102)
Arrange W switch of W HI-C cell in (200) in bulky capacitor subarray (201).
3. the difference type capacity regulator according to claim 1 for digital calibration, which is characterized in that described a pair
For capacitor array (100 and 200) under the control of a pair of of input calibration code, synchronization at least a pair is in different capacitor arrays
In bulky capacitor subarray (101 or 201) and small capacitances subarray (201 and 102) in all switches all disconnect.
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| CN201710546176.0A CN107491136B (en) | 2017-07-06 | 2017-07-06 | A kind of difference type capacity regulator for digital calibration |
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| CN201710546176.0A CN107491136B (en) | 2017-07-06 | 2017-07-06 | A kind of difference type capacity regulator for digital calibration |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101820267A (en) * | 2009-02-26 | 2010-09-01 | 旺玖科技股份有限公司 | Automatic correction circuit and method of capacitor |
| CN102082572A (en) * | 2009-11-26 | 2011-06-01 | 联发科技股份有限公司 | Calibration method and related calibration apparatus for capacitor array |
| CN103281083A (en) * | 2013-05-20 | 2013-09-04 | 电子科技大学 | Successive approximation fully differential analog-digital converter with figure correction function and processing method thereof |
| CN105375925A (en) * | 2015-11-30 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | Pseudo-differential capacitive successive approximation register analog-digital converter |
| US9461665B1 (en) * | 2015-08-24 | 2016-10-04 | Korea University Research And Business Foundation | Successive approximated register analog-to-digital converter and conversion method thereof |
-
2017
- 2017-07-06 CN CN201710546176.0A patent/CN107491136B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101820267A (en) * | 2009-02-26 | 2010-09-01 | 旺玖科技股份有限公司 | Automatic correction circuit and method of capacitor |
| CN102082572A (en) * | 2009-11-26 | 2011-06-01 | 联发科技股份有限公司 | Calibration method and related calibration apparatus for capacitor array |
| CN103281083A (en) * | 2013-05-20 | 2013-09-04 | 电子科技大学 | Successive approximation fully differential analog-digital converter with figure correction function and processing method thereof |
| US9461665B1 (en) * | 2015-08-24 | 2016-10-04 | Korea University Research And Business Foundation | Successive approximated register analog-to-digital converter and conversion method thereof |
| CN105375925A (en) * | 2015-11-30 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | Pseudo-differential capacitive successive approximation register analog-digital converter |
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