CN101207384B - Analog-to-digital converting system - Google Patents
Analog-to-digital converting system Download PDFInfo
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- CN101207384B CN101207384B CN2007101283370A CN200710128337A CN101207384B CN 101207384 B CN101207384 B CN 101207384B CN 2007101283370 A CN2007101283370 A CN 2007101283370A CN 200710128337 A CN200710128337 A CN 200710128337A CN 101207384 B CN101207384 B CN 101207384B
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Abstract
A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.
Description
Technical field
The present invention relates to a kind of D conversion system, and particularly relate to a kind of underrange continuous approximation D conversion system.
Background technology
The structure of A/D converter (ADC) is of a great variety, as flash type (Flash) ADC, pipeline (Pipeline) ADC, continuous approximation formula (Successive Approximation, SA) ADC and two steps type (Two-Step) ADC.These ADC structures possess the range of application that is fit to separately.
Though flash type ADC is applicable to that in the application of high speed sampling rate, its power consumption is big.The sampling frequency of continuous approximation formula ADC is lower, but its power consumption is low and its circuit complexity is low.
The characteristic of pipeline ADC then is between flash type ADC and continuous approximation formula ADC, but pipeline ADC need use the multiplication D/A transducer (Multiplier Digital-to-AnalogConverter, MDAC).And MDAC inside comprises residue (Residue) operational amplifier, and it is a negative feedback structure.Therefore, the residue operational amplifier will become the bottleneck of pipeline ADC on the high speed sampling frequency is used.
Two steps type ADC is categorized as circulating (Bit-Cycling) ADC in position and underrange formula (Subranging) ADC again.The circulating ADC in position also needs to remain amplifier, so similar problem is also arranged.According to present document record, underrange formula ADC can break through the bottleneck of the pipeline ADC two steps type ADC circulating with adopting the position, reaches the high speed sampling frequency.
Under will introduce several existing ADC systems respectively.
First kind of existing ADC system can be with reference to U.S. Pat 6124818.It is a utilization pipeline technology, so its operational capability greatly increases.The structure of the two rank ADC of its utilization, inner thick (Coarse) ADC and thin (Fine) ADC utilize the SA-ADC structure.Therefore, reduce the demand of D/A (DAC) resolution, make the circuit area of DAC diminish and the data transaction speed height of ADC.But because thick ADC adopts the SA-ADC structure, so it is hidden (Latency) time long, and sampling frequency is understood slow.
Second kind of existing ADC system can be with reference to U.S. Pat 5973632.It is the technology of utilization two steps type ADC, and the thick ADC of its inside is to adopt the flash type structure to carry out data transaction with thin ADC.Therefore, promoted the data transaction speed of ADC.But because thin ADC adopts the flash type structure, the number of its comparator is (2
MSBs+ L
SBs-2), MSBs and LSBs represent most significant byte and least significant byte respectively, so the quantity of comparator is more.Therefore, the circuit complexity height, power consumption is higher with the area availability also lower.
The third existing ADC system can be with reference to U.S. Pat 5675340.It is the technology of utilization two steps type ADC, and the thick ADC of its inside adopts the thin ADC of flash type ADC structure then to adopt the SA-ADC structure.So the comparator number of ADC only is 2
MSBsIndividual, negligible amounts.Therefore, power consumption is lower, and chip area is also less.But, will cause the data transaction time of DAC long because of it uses adder (Adder), so be not suitable for the high-speed transitions structure.Owing to do not adopt the technology of underrange, so the MSBs that thick ADC produces must pass to the DAC of SA-ADC inside, so the area of DAC (because of comprising more specific capacitance) greatly.The input equivalent capacity of DAC is higher, so under equal resolution, the ADC sampling frequency is slower.
The 4th kind of existing ADC system can be with reference to U.S. Pat 5247301.Please refer to Fig. 1, it shows the representative graph (Fig. 1) of U.S. Pat 5247301.As shown in Figure 1, this two steps type ADC mainly comprises: high position group 1, high-order sampling/maintenance (Sample/Hold, S/H) circuit bank 2, high coding device 3, low level comparator bank 4, low level sampling/holding circuit group 5, low level encoder 6, reference voltage generator 7, control signal generator 8, analog switch Sm, and buffer 9.
Similarly, low level comparator bank 4 comprises a plurality of comparator 4-1-4-n.Low level comparator bank 4 comparison reference voltage VL-1-VL-n and input voltage vin.Low level sampling/holding circuit group 5 comprises many group S/H circuit 5-1-5-n, and each S/H comprises switch S 5, S51 and capacitor C i.5 pairs of input voltage vin of low level sampling/holding circuit group are taken a sample/are kept, and give low level comparator bank 4 with the result.Low level encoder 6 is encoded into low byte DoL with the comparative result of low level comparator bank 4.
Reference voltage generator 7 can produce high-order reference voltage VH-1-VH-m to high position group 1.In addition, reference voltage generator 7 can produce low level reference voltage VL-1-VL-n according to high byte DoH and give low level comparator bank 4.
Control signal generator 8 produces control signal φ m, φ s2 respectively and φ s5 gives analog switch Sm, high-order sampling/holding circuit group 2 and low level sampling/holding circuit group 5.
Whether conducting is to high-order sampling/holding circuit group 2 and low level sampling/holding circuit group 5 for analog switch Sm control input voltage vin.
The 4th kind of existing ADC structure merges utilization two steps type ADC and underrange ADC.Its data transaction speed is very fast.But its comparator number is more, and therefore, circuit complexity height, power consumption are higher, the rate that manufactures a finished product is low also lower with the area availability.
The 5th kind of existing ADC system can be with reference to U.S. Pat 4994806.It uses the high-speed transitions feature of flash type ADC, to promote the conversion speed of ADC.It uses SA-ADC, to promote the accuracy of ADC.It is not needing to promote the overall efficiency of ADC under the extra emphasizer circuit in conjunction with the advantage of flash type ADC and SA-ADC.But because need use the residue amplifier, when ADC operates under the high-speed transitions frequency, this amplifier will become the design bottleneck of whole ADC system.
Summary of the invention
The invention provides a kind of D conversion system, convert analog input signal to digital output signal.This D conversion system comprises: follow the tracks of and holding circuit this analog input signal of following the tracks of and keeping being traced into; Roughcast/number converter is changed this tracking according to first reference voltage and is become first digital code with the output signal of holding circuit, and this first digital code is relevant for the most significant byte of this digital output signal; Coding and deposit unit are stored this first digital code and second digital code, and this second digital code is relevant for the least significant byte of this digital output signal, and this coding and deposit unit are encoded into the 3rd digital code with this first digital code; Reference voltage generator produces this first reference voltage and gives this roughcast/number converter, and this reference voltage generator produces second reference voltage according to coded the 3rd digital code that goes out of this coding and deposit unit; Continuous approximation formula A/D converter receives the output signal of this tracking and holding circuit, and according to this second reference voltage, this continuous approximation formula A/D converter utilizes the continuous approximation algorithm to change this tracking to become this second digital code with the output signal of holding circuit; And timing control unit, be used to control this tracking and holding circuit, this roughcast/number converter, this coding and deposit unit, this reference voltage generator and this continuous approximation formula A/D converter.
When the analog input signal of this D conversion system was full differential wave, this continuous approximation formula A/D converter comprised: continuous approximation formula register is used to store this second digital code and the 4th digital code; 2 complement code generator produces 2 complement code of the 4th digital code; First possesses the D/A of sampling/maintenance function, according to output signal, this second reference voltage and four digital code of this tracking with holding circuit, changes out first aanalogvoltage; Second sampling/maintenance the D/A according to this tracking this complement code of 2 with output signal, this second reference voltage and the 4th digital code of holding circuit, is changed out second aanalogvoltage; And comparator, receive this first and second possess this first aanalogvoltage and second aanalogvoltage that the D/A of sampling/maintenance function is exported, output signal to this continuous approximation formula register and this complement code generator of 2 with generation, this output signal of this comparator is used to upgrade this complement code of 2 of this second digital code, the 4th digital code and the 4th digital code.This comparator comprises: preamplifier, receive this first and second possess this first aanalogvoltage and second aanalogvoltage that the D/A of sampling/maintenance function is exported; And latch lock unit, the output that receives this preamplifier is to produce this output signal of this comparator.
Perhaps, when this analog input signal of this D conversion system was full differential wave, this continuous approximation formula A/D converter comprised: continuous approximation formula register is used to store this second digital code and the 4th digital code; 2 complement code generator produces 2 complement code of the 4th digital code; First D/A according to this second reference voltage and the 4th bit code, is changed out first aanalogvoltage; Second D/A according to this complement code of 2 of this second reference voltage and the 4th digital code, is changed out second aanalogvoltage; And comparator, relatively this first aanalogvoltage and this are followed the tracks of the output signal with holding circuit, and relatively this second aanalogvoltage and this are followed the tracks of output signal with holding circuit, output signal to this continuous approximation formula register and this complement code generator of 2 with generation, this output signal of this comparator is used to upgrade this complement code of 2 of this second digital code, the 4th digital code and the 4th digital code.This comparator comprises: first preamplifier receives output signal and this first aanalogvoltage of this tracking and holding circuit; Second preamplifier receives output signal and this second aanalogvoltage of this tracking and holding circuit; First adder receives the negative sense output of this first and second preamplifier; Second adder receives the forward output of this first and second preamplifier; And latch lock unit, the output that receives this first and second adder is to produce this output signal of this comparator.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 shows the representative graph of U.S. Pat 5247301.
Fig. 2 shows the schematic diagram of traditional binary continuous approximation transfer algorithm and novel binary system continuous approximation algorithm.
Fig. 3 shows the circuit block diagram according to the ADC system of first embodiment of the invention.
Fig. 4 shows the circuit block diagram according to the ADC system of second embodiment of the invention.
How the reference voltage generator of Fig. 5 displayed map 4 pursues the common-mode voltage of the output signal of T/H circuit.
The schematic diagram of the D/A of Fig. 6 displayed map 4 (tool sampling/maintenance function).
The example of the structure of Fig. 7 displayed map 4 when decision LSBs.
Fig. 8 shows the circuit block diagram according to the ADC system of third embodiment of the invention.
The schematic diagram of the D/A of Fig. 9 displayed map 8 (not tool sampling/maintenance function).
The reference numeral explanation
1: the high position group
2: high-order sampling/holding circuit group
3: the high coding device
4: the low level comparator bank
5: low level sampling/holding circuit group
6: the low level encoder
7: reference voltage generator
8: the control signal generator
9: buffer
Sm: analog switch
1-1-1-m: comparator
2-1-2-m: sampling/holding circuit
S2, S21: switch
Ci: electric capacity
4-1-4-n: comparator
5-1-5-n: sampling/holding circuit
S5, S51: switch
The 30:ADC system
31: follow the tracks of and holding circuit
32: roughcast/number converter
33: coding and deposit unit
34: reference voltage generator
35: continuous approximation A/D converter (SA-ADC)
36: timing control unit
The 40:ADC system
41: follow the tracks of and holding circuit
42: roughcast/number converter
43: coding and deposit unit
44: reference voltage generator
45: continuous approximation A/D converter (SA-ADC)
46: timing control unit
The complement code generator of 451:2
452,453: tool sampling and the D/A that keeps function
454: comparator
455: preamplifier
456: latch lock unit
457: continuous approximation register (SAR)
R51-R52: resistance
51: amplifier
52 and 53: current source
54: resistance string
61-65: switch
66-69: electric capacity
The 80:ADC system
81: follow the tracks of and holding circuit
82: thick ADC
83: coding and deposit unit
84: reference voltage generator
85: continuous approximation A/D converter (SA-ADC)
86: timing control unit
The complement code generator of 851:2
852 and 853: D/A (DAC)
854: comparator
855a and 855b: preamplifier
856a and 856b: adder
857: continuous approximation register (SAR)
858: latch lock unit
91-94: switch
95-97: electric capacity.
Embodiment
In several embodiment of the present invention, be to serve as the technology of basis employing Subranging with the Two-Step structure, wherein, the structure of thick ADC is Flash ADC, thin ADC then adopts continuous approximation formula ADC.So those embodiment have the advantage of high speed sampling frequency and low power consumption.
These embodiment utilize binary system continuous approximation transfer algorithm.But the applied binary system continuous approximation of those embodiment transfer algorithm is different from traditional binary continuous approximation transfer algorithm.
Please refer to Fig. 2, it shows the schematic diagram of traditional binary continuous approximation transfer algorithm and the applied binary system continuous approximation of those embodiment algorithm.Carry out four data transaction in this hypothesis, and adopt the synchronous sequence control mode.
As shown in Figure 2, traditional binary continuous approximation algorithm needs 4 Δ T1 to finish the data transaction of 4 (MSB, MSB-1, MSB-2 and LSB).Δ T1 depends on the slowest data transaction situation, and it is relevant for the time of electric charge redistribution.
In comparison, in the applied binary system continuous approximation of embodiment of the invention algorithm, 4 data transaction is carried out the data transaction of most significant byte (MSBs) respectively by thick ADC, thin ADC then carries out the data transaction of least significant byte (being MSB-2 and LSB).Because thick ADC adopts flash type ADC structure, it has data transaction speed very at a high speed, can be less than 2* Δ T1 so determine the required time Δ T0 of MSBs.Because thin ADC only is responsible for the conversion of LSBs and adopts the underrange technology again, so redistributing the time, electric charge will reduce four times, i.e. Δ T1=4* Δ T2.So, the overall data conversion speed can be significantly improved.
[first embodiment]
Please refer to Fig. 3, it shows the circuit block diagram according to the ADC system of first embodiment of the invention.As shown in Figure 3, this ADC system 30 comprises: follow the tracks of and holding circuit (Track and Hold, T/H) 31, roughcast/number converter (Coarse ADC) 32, coding and deposit unit (decoding and bufferingunit) 33, reference voltage generator 34, SA-ADC 35, and timing control unit 36.
When tracing mode, follow the tracks of with holding circuit 31 and can follow the tracks of input signal.When keeping pattern, follow the tracks of input signal that is traced into holding circuit 31 meeting maintenances and the circuit (being roughcast/number converter 32, SA-ADC 35 and reference voltage generator 34) that sends the rear end to.
Roughcast/number converter 32 receives the output signal of following the tracks of with holding circuit 31, carries out high-order data transaction with generation digital code MSBs, and digital code MSBs is passed to coding and deposit unit 33.Digital code MSBs is relevant for final result D
OUT[N
RES-1:0] (N
RESBe resolution) most significant byte.The digital code MSBs that roughcast/number converter 32 produced is such as being Gray code (Gray Code).Roughcast/number converter 32 can utilize flash type ADC to implement, and it has the function of error correction.In the present embodiment, the structure chart of roughcast/number converter 32 does not limit especially, as long as can reach above-mentioned functions.
Coding and deposit unit 33 store M SBs and LSBs (it is produced by SA-ADC25).Coding can convert 2 to MSBs (it is a Gray code) with deposit unit 33
MSBs(it is n 1 yard (1-of-nCode)), and with 2
MSBsSend reference voltage generator 34 to, so that reference voltage generator 34 is in order to produce reference voltage VB (VB
RT, VB
RBWith VB
CM).N
RESByte equal the figure place summation of MSBs and LSBs.When sA-ADC 35 obtained final digital code LSBs, coding can produce final result D according to digital code MSBs and digital code LSBs with deposit unit 33
OUT[N
RES-1:0].At this, digital code MSBs is unnecessary identical with the figure place of LSBs.
SA-ADC 35 receives the output signal of following the tracks of with holding circuit 31, utilizes data transaction that continuous approximation (SA) algorithm carries out low level producing LSBs, and LSBs is passed to coding and deposit unit 33.
Please refer again to Fig. 2.The MSBs that thick ADC is produced is relevant for reference voltage VB
RTWith VB
RB(supplying with SA-ADC).The two relation is such as following table.
| MSB | (VB RT，VB RB) |
| 11 | (VA RT，V1) |
| 10 | (V1，V2) |
| 01 | (V2，V3) |
| 00 | (V3，VA RB) |
In addition, better be, no matter the value of MSBs is why, VB
RTWith VB
RBBetween difference for fixing.
Beneath operating principle with key diagram 3.Resolution of ADC at this hypothesis Fig. 3 is 4, and MSBs and LSBs are all 2.Please together with reference to figure 2 and Fig. 3.
In Δ T0, roughcast/number converter 32 can be changed out MSBs, supposes that it is 01.So reference voltage generator 34 can produce suitable reference voltage VB according to MSBs and give SA-ADC 35.Then, in first Δ T2, SA-ADC 35 can change out the high bit of LSBs.In second Δ T2, SA-ADC 35 can change out LSBs than low level.At last, coding can be combined into D with MSBs and LSBs with deposit unit 33
OUTSo far, finish the conversion operations of ADC.
[second embodiment]
Please refer to Fig. 4, it shows the circuit block diagram according to the ADC system of second embodiment of the invention.As shown in Figure 4, this ADC system 40 comprises: follow the tracks of and holding circuit 41, and roughcast/number converter 42, coding and deposit unit 43, reference voltage generator 44, SA-ADC 45, and timing control unit 46.Timing control unit 46 can asynchronous system be controlled those unit 41-45 and inner electronic circuit thereof, so timing control unit 46 can not need external timing signal.Fig. 4 is applicable to when input signal is complete differential input signal.
SA-ADC 45 comprises: 2 complement code generator 451 has the D/A (DAC) 452 and 453 that sampling keeps function, comparator 454, and continuous approximation register (SAR) 457.Comparator 454 comprises: preamplifier 455 and latch lock unit 456.Comparator 454 has the deviation adjusting function simultaneously.
Under the control of digital code Code_I and Code_II (Code_I I is 2 the complement code of Code_I), DAC 452 and 453 can be according to the output signal and the reference voltage VB of T/H circuit 41
RB, VB
RT, and change out analog voltage signal Vp and Vn.How changing as for DAC 452 and 453 can be with reference to beneath graphic and description.
The structure of continuous approximation register 457 does not need to limit especially it at this.Can be the combination of shift register and logical circuit such as it.
Please refer to Fig. 5, the some of the reference voltage generator 44 of its displayed map 4, it is used to pursue the common-mode voltage VCM_TH of the output signal of T/H circuit 41.The some of reference voltage generator 44 comprises: resistance R 51 and R52, amplifier 51, current source 52 and 53, and resistance string 54.Resistance string 54 comprises the resistance R of a plurality of series connection.
As shown in Figure 5, resistance R 51 can be used for taking out its common-mode voltage VCM_TH from the output signal of T/H circuit 41 with R52.Common-mode voltage VCM_TH inputs to amplifier 51, and the other end of amplifier 51 then is connected to another common-mode voltage VA
CMThe output signal of amplifier 51 can be used for Control current source 52.By the negative feedback mechanism that assembly 51-54 is set up, will make common-mode voltage VA
CMPursue common-mode voltage VCM_TH.
Please refer to Fig. 6, it shows the schematic diagram of D/A 452 (tool sampling/maintenance function).The structure of D/A 453 is same as D/A 452, and difference only is the handle difference of b0-b2.
As shown in Figure 6, D/A 452 comprises: switch 61-65, and electric capacity 66-69.In the present embodiment, the capacitance ratio of electric capacity 66-69 is 1: 1: 2: 4.
When being in when reseting pattern, switch 61 can conductings, and switch 62-65 can be connected to common-mode voltage VB
CM
When being in sample phase, switch 61 meeting conductings, switch 62-65 can switch to VO_TH, and VO_TH is the output voltage of T/H circuit 41.
When being in maintenance during the stage, switch 61 can be obstructed, and switch 62 switches to VB
RBSwitch 63-65 can determine to switch to VB according to position b0, b1 and b2 respectively
RBOr VB
RTSuch as, when position b0 was 0, switch 63 can switch to VB
RBOtherwise, then switch to VB
RTPosition b0-b2 is LSBs.
Voltage Vp can be expressed as follows:
Vp＝VB
CM-VO_TH+ΔV_MSBs*(1/2*b2+1/4*B1+1/8*B0)+VB
RB
…(1)
In following formula (1), Δ V_MSBs represents VB
RTWith VB
RBDifference.
Please refer to Fig. 7, the example of the structure of its displayed map 4 when decision LSBs.According to the continuous approximation algorithm, the default value of Code_I and Code_II is all 100.
During T1, can determine a b2.At the position b2 that this hypothesis is determined is 0.The position b2 that is determined can be stored to the complement code generator 451 of SAR 457 and 2 respectively, to upgrade Code_I and Code_II, makes it become 010 and 110 respectively.
During T2, can determine a b1.During T3, can determine a b0.Similarly, the position b1 and the b0 that are determined can upgrade Code_I and Code_II, as shown in Figure 7.After T3, can determine the end value of LSBs.
The structure of Fig. 4 is such as applicable to super wideband (Ultra-Wide Band; UWB) radio communication.
[the 3rd embodiment]
Please refer to Fig. 8, it shows the circuit block diagram according to the ADC system of third embodiment of the invention.As shown in Figure 8, this ADC system 80 comprises: follow the tracks of and holding circuit 81, and thick ADC 82, coding and deposit unit 83, reference voltage generator 84, SA-ADC 85, and timing control unit 86.Timing control unit 86 can the method for synchronization be controlled those unit 81-85 and inner electronic circuit thereof, so timing control unit 86 needs external timing signal and sampled signal.Unit 81,82,83,84 is identical with 86 or similar in the assembly of the foregoing description, so no longer repeat in this.
SA-ADC 85 comprises: 2 complement code generator 851, and DAC (not tool sampling/maintenance function) 852 and 853, comparator 854 is with continuous approximation register 857.Comparator 854 comprises: preamplifier 855a and 855b, adder 856a and 856b, and latch lock unit 858.Comparator 854 has the deviation adjusting function simultaneously.The annexation of the intraware of SA-ADC 85 can get with reference to figure 8, no longer repeats at this.
Please refer to Fig. 9, it shows the schematic diagram of D/A 852.The similar of D/A 853 or be same as D/A 852.
As shown in Figure 9, D/A 852 comprises: switch 91-94, and electric capacity 95-97.In the present embodiment, the capacitance ratio of electric capacity 95-97 is 1: 2: 4.
When being in when reseting pattern, switch 91 can conductings, and switch 92-94 can be connected to common-mode voltage VB
CM
When carrying out data transaction, switch 91 can open circuit, and switch 92,93 and 94 can determine to switch to VB according to position b0, b1 and b2
RBOr VB
RTSuch as, when position b0 was 0, switch 83 can switch to VB
RBOtherwise, then switch to VB
RTPosition b0-b2 is LSBs.
Structure by Fig. 9 can find out that voltage Vp can be expressed as follows:
Vp＝ΔV_MSBs*(1/2*b2+1/4*b1+1/8*b0)+VB
RB …(2)
In the above-described embodiments, can obtain to reduce by two characteristics such as adc circuit consumed power and lifting data transaction speed.Its reason is, is example with traditional double stepwise ADC structure, and the demand of thick ADC comparator is (2
MSBs-1); And the demand of thin ADC comparator is (2
LSBs-1).But in the present embodiment, ADC internal comparator demand only is 2
MSBs, so reach the purpose that reduces circuit complexity and power consumption.In addition, because the minimizing of the demand of comparator, so the load capacitance amount of tracking and holding circuit can be reduced.And the technology of Subranging makes the resolution of DAC of SA-ADC inside reduce, thus shorten the electric charge redistribution time, and then lifting adc data conversion speed.
Hold as above-mentioned, because the reduction of input equivalent capacitance value is reached layout coupling and preferable electric charge yardstick formula (Charge Scaling) the DAC structure (as Fig. 6 and Fig. 9) of accuracy easily so can adopt.
In sum, present embodiment can reach high speed sampling frequency, low power consumption and reduce circuit complexity as can be known, promotes chip manufacturing rate of finished products and area availability to reach.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the present patent application claim person of defining.
Claims (8)
1. a D conversion system converts analog input signal to digital output signal, and this D conversion system comprises:
Follow the tracks of and holding circuit, when tracing mode, this tracking and holding circuit are followed the tracks of this analog input signal, when keeping pattern, and this analog input signal that this tracking and holding circuit maintenance are traced into;
Roughcast/number converter is changed this tracking according to first reference voltage and is become first digital code with the output signal of holding circuit, and this first digital code is relevant for the most significant byte of this digital output signal;
Coding and deposit unit are stored this first digital code and second digital code, and this second digital code is relevant for the least significant byte of this digital output signal, and this coding and deposit unit are encoded into the 3rd digital code with this first digital code;
Reference voltage generator produces this first reference voltage and gives this roughcast/number converter, and this reference voltage generator more produces second reference voltage according to coded the 3rd digital code that goes out of this coding and deposit unit;
Continuous approximation formula A/D converter receives the output signal of this tracking and holding circuit, and according to this second reference voltage, this continuous approximation formula A/D converter utilizes the continuous approximation algorithm to change this tracking to become this second digital code with the output signal of holding circuit; And
Timing control unit is used to control this tracking and holding circuit, this roughcast/number converter, this coding and deposit unit, this reference voltage generator and this continuous approximation formula A/D converter.
2. D conversion system as claimed in claim 1, wherein, this first digital code is a Gray code, and this roughcast/number converter is the flash type A/D converter.
3. D conversion system as claimed in claim 1, wherein, when this analog input signal was full differential wave, this reference voltage generator was more pursued the common-mode voltage of the output signal of this tracking and holding circuit.
4. D conversion system as claimed in claim 2, wherein, the 3rd digital code is 1 yard of n.
5. D conversion system as claimed in claim 1, wherein, when this analog input signal was full differential wave, this continuous approximation formula A/D converter comprised:
Continuous approximation formula register is used to store this second digital code and the 4th digital code;
2 complement code generator produces 2 complement code of the 4th digital code;
First possesses the D/A of sampling/maintenance function, according to output signal, this second reference voltage and four digital code of this tracking with holding circuit, changes out first aanalogvoltage;
Second possesses the D/A of sampling/maintenance function, according to this tracking this complement code of 2 with output signal, this second reference voltage and the 4th digital code of holding circuit, changes out second aanalogvoltage; And
Comparator, receive this first and second possess this first aanalogvoltage and this second aanalogvoltage that the D/A of sampling/maintenance function exports and output signal to this continuous approximation formula register and this complement code generator of 2 with generation, this output signal of this comparator is used to upgrade this complement code of 2 of this second digital code, the 4th digital code and the 4th digital code.
6. D conversion system as claimed in claim 5, wherein, this comparator comprises:
Preamplifier, receive this first and second possess this first aanalogvoltage and this second aanalogvoltage that the D/A of sampling/maintenance function is exported; And
Latch lock unit, the output that receives this preamplifier is to produce this output signal of this comparator.
7. D conversion system as claimed in claim 1, wherein, when this analog input signal was full differential wave, this continuous approximation formula A/D converter comprised:
Continuous approximation formula register is used to store this second digital code and the 4th digital code;
2 complement code generator produces 2 complement code of the 4th digital code;
First D/A according to this second reference voltage and the 4th digital code, is changed out first aanalogvoltage;
Second D/A according to this complement code of 2 of this second reference voltage and the 4th digital code, is changed out second aanalogvoltage; And
Comparator, relatively this first aanalogvoltage and this are followed the tracks of the output signal with holding circuit, and relatively this second aanalogvoltage and this are followed the tracks of output signal with holding circuit, output signal to this continuous approximation formula register and this complement code generator of 2 with generation, this output signal of this comparator is used to upgrade this complement code of 2 of this second digital code, the 4th digital code and the 4th digital code.
8. D conversion system as claimed in claim 7, wherein, this comparator comprises:
First preamplifier receives output signal and this first aanalogvoltage of this tracking and holding circuit;
Second preamplifier receives output signal and this second aanalogvoltage of this tracking and holding circuit;
First adder receives the negative sense output of this first and second preamplifier;
Second adder receives the forward output of this first and second preamplifier; And
Latch lock unit, the output that receives this first and second adder is to produce this output signal of this comparator.
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|---|---|---|---|
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200828817A (en) | 2008-07-01 |
| CN101207384A (en) | 2008-06-25 |
| TWI333335B (en) | 2010-11-11 |
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