CN113078906B - Successive approximation type analog-to-digital converter and conversion method thereof - Google Patents
Successive approximation type analog-to-digital converter and conversion method thereof Download PDFInfo
- Publication number
- CN113078906B CN113078906B CN202110628624.8A CN202110628624A CN113078906B CN 113078906 B CN113078906 B CN 113078906B CN 202110628624 A CN202110628624 A CN 202110628624A CN 113078906 B CN113078906 B CN 113078906B
- Authority
- CN
- China
- Prior art keywords
- sampling
- output voltage
- input signal
- conversion
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The invention provides a successive approximation type analog-to-digital converter and a conversion method thereof, wherein the converter comprises: the sampling circuit is used for obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the current input signal when sampling for the first time; when sampling is not carried out for the first time, obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the difference value of the current input signal and the previous input signal; the conversion circuit is connected to the output end of the sampling circuit and is used for carrying out analog-to-digital conversion on the difference value of the output voltage of the in-phase end and the output voltage of the anti-phase end to obtain a digital signal corresponding to each sampling; and the digital control circuit is connected with the output end of the conversion circuit and used for defining the next sampling as the first sampling if the weight bit corresponding to the current digital signal is in the set low weight bit range and the difference between the weight bit and the set low weight bit range is less than a set value when the sampling is not performed for the first time. The successive approximation type analog-to-digital converter and the conversion method thereof provided by the invention solve the problem of slow conversion rate of the existing SAR ADC.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a successive approximation type analog-to-digital converter and a conversion method thereof.
Background
An analog-to-digital converter (ADC) is a bridge for communicating the natural world with the machine world, and is also an essential component in a measurement control system, wherein a successive approximation analog-to-digital converter (SAR ADC) is widely applied due to its characteristics of high speed, high precision, low delay and the like.
The conversion period of the SAR ADC can be divided into two stages according to the time sequence of actual work: the first stage is sampling, accurately sampling the analog signal to be converted to a capacitor and holding the analog signal, and the second stage is conversion, quantizing the analog signal obtained by the sampling in the first stage, converting the analog signal into a digital signal and outputting the digital signal; therefore, if the SAR ADC output is to meet the high speed and high accuracy requirement, the time required to compress the two stages must be considered without sacrificing accuracy.
Many of the analog signals in the natural world are continuous and low-frequency signals, such as temperature, humidity, sound waves and the like, which require relatively high precision when being processed, and the processing speed may also require relatively high requirements due to the requirement of control feedback, which puts requirements on the SAR ADC; some other signals are not absolute precision, but the difference between the current signal and another signal, or the relative difference between the current time of the current signal and the previous time of the current signal, but the difference also requires fast and precise conversion.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a successive approximation type analog-to-digital converter and a conversion method thereof, which are used to solve the problem of slow conversion rate of the existing SAR ADC.
To achieve the above and other related objects, the present invention provides a successive approximation type analog-to-digital converter, including:
the sampling circuit is used for obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the current input signal when sampling for the first time; when sampling is not carried out for the first time, obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the difference value of the current input signal and the previous input signal;
the conversion circuit is connected to the output end of the sampling circuit and is used for carrying out analog-to-digital conversion on the difference value of the output voltage of the in-phase end and the output voltage of the anti-phase end to obtain a digital signal corresponding to each sampling;
and the digital control circuit is connected with the output end of the conversion circuit and used for defining the next sampling of the sampling circuit as the first sampling if the weight bit corresponding to the current digital signal is in the set low weight bit range and the difference between the set low weight bit and the weight bit corresponding to the current digital signal is less than a set value when the sampling is not performed for the first time.
Optionally, the sampling circuit comprises: the sampling module comprises a same-phase end sampling module and an opposite-phase end sampling module which have the same circuit structure, wherein both the two sampling modules comprise two sampling units with the same circuit structure;
during first sampling, two sampling units of two sampling modules sample current input signals, and then charge transfer is carried out on one sampling unit so as to obtain output voltage of a non-inverting terminal and output voltage of an inverting terminal based on the current input signals;
when sampling is not performed for the first time, the two sampling units of the two sampling modules sample the current input signal, and simultaneously, charge transfer is performed on the sampling unit which is not subjected to charge transfer for the previous time, so that the output voltage of the in-phase end and the output voltage of the inversion end are obtained based on the difference value of the current input signal and the previous input signal.
Optionally, the sampling unit includes: the sampling circuit comprises a sampling capacitor and four switches, wherein two switches of the four switches are connected in series between corresponding input voltage and common mode voltage to form a series node, the other two switches of the four switches are connected in series between the common mode voltage and corresponding output voltage to form another series node, and the sampling capacitor is connected between the two series nodes.
Optionally, the digital control circuit is further configured to obtain a conversion output corresponding to the current input signal based on the current digital signal when sampling for the first time; and when the sampling is not carried out for the first time, obtaining the conversion output corresponding to the current input signal based on the current digital signal and all the previous digital signals.
Optionally, the digital control circuit is further configured to generate a sampling control signal.
Optionally, the input signal is a low frequency continuously slowly varying signal.
The invention also provides a conversion method of the successive approximation type analog-to-digital converter, which comprises the following steps:
when sampling for the first time, obtaining the output voltage of a non-inverting terminal and the output voltage of an inverting terminal based on the current input signal; when sampling is not carried out for the first time, obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the difference value of the current input signal and the previous input signal;
performing analog-to-digital conversion on the difference value of the output voltage of the in-phase end and the output voltage of the inversion end to obtain a digital signal corresponding to each sampling;
when the sampling is not the first sampling, if the weight bit corresponding to the current digital signal is in the set low weight bit range and the difference between the set low weight bit and the weight bit corresponding to the current digital signal is less than the set value, the next sampling is defined as the first sampling.
Optionally, the method for obtaining the output voltage of the in-phase terminal and the output voltage of the inverting terminal includes:
during first sampling, the in-phase end and the inverting end use two sampling capacitors to sample a current input signal, and then charge transfer is carried out on one of the sampling capacitors, so that the in-phase end output voltage and the inverting end output voltage are obtained based on the current input signal;
when sampling is not performed for the first time, the in-phase end and the inverting end use the two sampling capacitors to sample the current input signal, and simultaneously perform charge transfer on the sampling capacitor which has not performed charge transfer for the previous time, so that the in-phase end output voltage and the inverting end output voltage can be obtained based on the difference value of the current input signal and the previous input signal.
Optionally, the conversion method further comprises: obtaining a conversion output corresponding to the current input signal; the method specifically comprises the following steps: when sampling for the first time, obtaining conversion output corresponding to the current input signal based on the current digital signal; and when the sampling is not carried out for the first time, obtaining the conversion output corresponding to the current input signal based on the current digital signal and all the previous digital signals.
Optionally, the input signal is a low frequency continuously slowly varying signal.
As described above, according to the successive approximation type analog-to-digital converter and the conversion method thereof of the present invention, the conversion result of the first input signal and the conversion result of the difference value of every two subsequent adjacent input signals are used to derive the complete result of each conversion, so as to increase the conversion speed of the ADC, reduce the dynamic power consumption consumed during the conversion, and suppress the low-frequency noise and the common-mode deviation.
Drawings
FIG. 1 is a circuit diagram of a successive approximation analog-to-digital converter according to the present invention.
Fig. 2 is a schematic diagram showing a waveform of the input signal according to the present invention.
Fig. 3 is a schematic diagram showing the closing of each switch of the successive approximation type analog-to-digital converter during the first sampling.
Fig. 4 is a schematic diagram showing the closing of each switch in the successive approximation type analog-to-digital converter according to the present invention during the first charge transfer.
FIG. 5 is a schematic diagram showing the closing of the switches of the successive approximation register analog-to-digital converter during the second sampling and charge transfer.
FIG. 6 is a schematic diagram showing the closing of the switches of the successive approximation register analog-to-digital converter during the third sampling and charge transfer.
Element number description: the device comprises a 10 sampling circuit, an 11 in-phase end sampling module, a 111 in-phase end sampling unit, a 12 inverting end sampling module, a 112 inverting end sampling unit, a 20 conversion circuit and a 30 digital control circuit.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a successive approximation type analog-to-digital converter, which includes: the sampling circuit 10, the conversion circuit 20 and the digital control circuit 30, the conversion circuit 20 is connected to the output end of the sampling circuit 10, and the digital control circuit 30 is connected to the output end of the conversion circuit 20.
The sampling circuit 10 is configured to obtain an in-phase end output voltage VXP and an inverting end output voltage VXN based on a current input signal when sampling for the first time; and when the sampling is not performed for the first time, obtaining the output voltage VXP of the in-phase end and the output voltage VXN of the inverting end based on the difference value of the current input signal and the previous input signal.
Specifically, as shown in fig. 1, the sampling circuit 10 includes: the sampling module comprises a same-phase end sampling module 11 and an opposite-phase end sampling module 12 which have the same circuit structure, wherein both the two sampling modules comprise two sampling units with the same circuit structure;
during first sampling, two sampling units of two sampling modules sample current input signals, and then charge transfer is carried out on one sampling unit so as to obtain output voltage VXP of a non-inverting terminal and output voltage VXN of an inverting terminal based on the current input signals;
when sampling is not performed for the first time, the two sampling units of the two sampling modules sample the current input signal, and simultaneously perform charge transfer on the sampling unit which has not performed charge transfer for the previous time, so that the output voltage VXP of the in-phase end and the output voltage VXN of the anti-phase end can be obtained based on the difference value of the current input signal and the previous input signal.
More specifically, the sampling unit includes: the sampling circuit comprises a sampling capacitor and four switches, wherein two switches of the four switches are connected in series between the corresponding input voltage and the common-mode voltage VCM to form a series node, the other two switches of the four switches are connected in series between the common-mode voltage VCM and the corresponding output voltage to form another series node, and the sampling capacitor is connected between the two series nodes. Further, the in-phase end sampling module 11 includes: two in-phase end sampling capacitors and eight in-phase end switches, namely a first in-phase end sampling capacitor CSP1, a second in-phase end sampling capacitor CSP2, a first in-phase end switch SWP1, a second in-phase end switch SWP2, a third in-phase end switch SWP3, a fourth in-phase end switch SWP4, a fifth in-phase end switch SWP5, a sixth in-phase end switch SWP6, a seventh in-phase end switch SWP7 and an eighth in-phase end switch SWP 8; the first non-inverting terminal sampling capacitor CSP1, the first non-inverting terminal switch SWP1, the second non-inverting terminal switch SWP2, the third non-inverting terminal switch SWP3, and the fourth non-inverting terminal switch SWP4 constitute a non-inverting terminal sampling unit 111 in the non-inverting terminal sampling module 11, and the second non-inverting terminal sampling capacitor CSP2, the fifth non-inverting terminal switch SWP5, the sixth non-inverting terminal switch SWP6, the seventh non-inverting terminal switch SWP7, and the eighth non-inverting terminal switch SWP8 constitute another non-inverting terminal sampling unit 111 in the non-inverting terminal sampling module 11 (specifically, as shown in fig. 1). The inverting terminal sampling module 12 includes: two inverting terminal sampling capacitors and eight inverting terminal switches, namely a first inverting terminal sampling capacitor CSN1, a second inverting terminal sampling capacitor CSN2, a first inverting terminal switch SWN1, a second inverting terminal switch SWN2, a third inverting terminal switch SWN3, a fourth inverting terminal switch SWN4, a fifth inverting terminal switch SWN5, a sixth inverting terminal switch SWN6, a seventh inverting terminal switch SWN7 and an eighth inverting terminal switch SWN 8; the first inverting terminal sampling capacitor CSN1, the first inverting terminal switch SWN1, the second inverting terminal switch SWN2, the third inverting terminal switch SWN3, and the fourth inverting terminal switch SWN4 constitute an inverting terminal sampling unit 112 in the inverting terminal sampling module 12, and the second inverting terminal sampling capacitor CSN2, the fifth inverting terminal switch SWN5, the sixth inverting terminal switch SWN6, the seventh inverting terminal switch SWN7, and the eighth inverting terminal switch SWN8 constitute another inverting terminal sampling unit 112 in the inverting terminal sampling module 12 (specifically, as shown in fig. 1).
Specifically, the input signal is a low-frequency continuously-slowly-varying signal (specifically, as shown in fig. 2). For low-frequency continuous slowly-varying signals, because the distance between two adjacent continuous conversion times is short and the change of two adjacent input signals is small, the high-weight bits of digital outputs corresponding to the two input signals are basically consistent, as long as the high-weight bit result is obtained by the first conversion, the high-weight bit comparison can be skipped for the next conversion, and the low-weight bit comparison can be directly carried out, so that the time and the power consumption required by the high-weight bit conversion are saved for the next conversion; thus, only the first time of input signal needs to be subjected to all weight bit conversion, the second time of input signal can be subjected to low weight bit conversion only on the basis of the first time, the third time of input signal is subjected to low weight bit conversion on the basis of the second time, and the like, the Nth time of input signal is subjected to low weight bit conversion on the basis of the (N-1) th time, namely, the first complete input signal is converted for the first time, the difference value between the second input signal and the first input signal is converted for the second time, the difference value between the third input signal and the second input signal is converted for the third time, and the like, and the difference value between the Nth input signal and the (N-1) th input signal is converted for the Nth time. The conversion mode is characterized in that the conversion of each input signal is not participated by the ownership resetting bit, and most signals are actually converted only by the low-weight resetting bit, so that the conversion time at each time can be greatly shortened, an accurate result can be obtained more quickly, the conversion rate is improved, meanwhile, the high-weight resetting bit is not participated in most conversions, the dynamic power consumption of the whole ADC in normal work can be greatly reduced, in addition, the low-frequency noise and the common-mode offset can be suppressed by difference processing, and the anti-noise performance of the ADC is improved.
The conversion circuit 20 is configured to perform analog-to-digital conversion on a difference between the output voltage VXP at the non-inverting terminal and the output voltage VXN at the inverting terminal, so as to obtain a digital signal corresponding to each sampling.
Specifically, the conversion circuit 20 is any one of the existing circuit structures that can perform analog-to-digital conversion on the difference between the output voltage VXP at the non-inverting terminal and the output voltage VXN at the inverting terminal, and this example does not limit the specific structure thereof.
When the digital control circuit 30 is used for non-initial sampling, if the weight bit corresponding to the current digital signal is within the range of the set low weight bit and the difference between the set low weight bit and the weight bit corresponding to the current digital signal is smaller than the set value, the next sampling of the sampling circuit 10 is defined as the initial sampling. When sampling is not performed for the first time, the output voltage VXP of the in-phase end and the output voltage VXN of the anti-phase end are obtained based on the difference value of the current input signal and the previous input signal, and the difference value is much smaller than the input signal, so that only low-weight bit conversion can be performed; all the weight bits are marked as DA bits, the range of the low weight bits is 0-DL bits, the range of the high weight bits is DA to (DL + 1) bits, if the current digital signal is corresponding to the range of the low weight bits and is far smaller than DL, the conversion is considered to be effective, and once the current digital signal is corresponding to the range of the low weight bits and approaches DL, the next sampling is redefined as the first sampling to perform the conversion of all the weight bits and is used as the reference of the next conversion, so that the situation that the difference value approaches or exceeds the range of the low weight bits and cannot accurately reflect the size of the sampling signal can be avoided; if the current digital signal is assumed to have 8 bits of low weight and 2 bits of set value, the next sampling is defined as the first sampling if the current digital signal corresponds to 7 bits of weight, i.e., the current digital signal corresponds to a weight within the range of the set low weight and the difference between the set low weight and the current digital signal is less than the set value. It should be noted that the weight bits in this example refer to output codes of SAR ADC conversion from high to low in order, the codes of different bits have different total weights, the highest bit weight is the largest, and the lowest bit weight is the smallest, such as binary code 101, and corresponds to three weight bits, and the corresponding value is 4+0+1= 5; the "weight bit corresponding to the current digital signal" refers to the number of bits of the current digital signal, and the "set low weight bit" is a preset value and can be set according to actual requirements.
Specifically, the digital control circuit 30 is further configured to obtain a conversion output corresponding to the current input signal based on the current digital signal when sampling for the first time; and when the sampling is not carried out for the first time, obtaining the conversion output corresponding to the current input signal based on the current digital signal and all the previous digital signals.
More specifically, the digital control circuit is further configured to generate a sampling control signal (i.e., a non-inverting sampling control signal C)SWPAnd an inverting terminal sampling control signal CSWN) For controlling the switches in the sampling circuit 10 to realize sampling and charge transfer.
Correspondingly, the present embodiment further provides a conversion method of a successive approximation type analog-to-digital converter, where the conversion method includes:
1) when sampling for the first time, obtaining the output voltage of a non-inverting terminal and the output voltage of an inverting terminal based on the current input signal; when sampling is not carried out for the first time, obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the difference value of the current input signal and the previous input signal;
2) performing analog-to-digital conversion on the difference value of the output voltage of the in-phase end and the output voltage of the inversion end to obtain a digital signal corresponding to each sampling;
3) when the sampling is not the first sampling, if the weight bit corresponding to the current digital signal is in the set low weight bit range and the difference between the set low weight bit and the weight bit corresponding to the current digital signal is less than the set value, the next sampling is defined as the first sampling.
Specifically, the conversion method further includes: 4) obtaining a conversion output corresponding to the current input signal; the method specifically comprises the following steps: when sampling for the first time, obtaining conversion output corresponding to the current input signal based on the current digital signal; and when the sampling is not carried out for the first time, obtaining the conversion output corresponding to the current input signal based on the current digital signal and all the previous digital signals.
Specifically, the method for obtaining the output voltage of the in-phase terminal and the output voltage of the inverting terminal in 1) includes:
during first sampling, the in-phase end and the inverting end use two sampling capacitors to sample a current input signal, and then charge transfer is carried out on one of the sampling capacitors, so that the in-phase end output voltage and the inverting end output voltage are obtained based on the current input signal;
when sampling is not performed for the first time, the in-phase end and the inverting end use the two sampling capacitors to sample the current input signal, and simultaneously perform charge transfer on the sampling capacitor which has not performed charge transfer for the previous time, so that the in-phase end output voltage and the inverting end output voltage can be obtained based on the difference value of the current input signal and the previous input signal.
Specifically, the input signal is a low-frequency continuous slowly varying signal.
Referring to fig. 2-6, a conversion process of the successive approximation type analog-to-digital converter of the present embodiment is described; in order to simplify the analysis, the figure only shows the working condition of each switch in the sampling and charge conversion process of the inverting terminal sampling module.
The successive approximation type analog-to-digital converter of the present embodiment is used to perform a/D conversion on an input signal as shown in fig. 2, and the specific process is as follows:
for the first sampling and charge transfer, as shown in fig. 3, the input signal VIN1 at the inverting terminal is sampled to two sampling capacitors CSN1 and CSN2, respectively, and the lower plates of the two sampling capacitors CSN1 and CSN2 are both connected to the common-mode voltage VCM; then, as shown in fig. 4, the upper plate of the sampling capacitor CSN1 is connected to the common-mode voltage VCM, the lower plate thereof is connected to VXN1, the input signal VIN1 on the sampling capacitor CSN1 is mapped to VXN1 due to charge sharing, the upper and lower plates of the sampling capacitor CSN2 are both disconnected, and the charge (VIN 1-VCM) CSN2 is temporarily stored on the sampling capacitor CSN2 for the next input signal to be used for difference; from the conservation of charge on the sampling capacitor CSN 1: (VCM-VIN 1) × CSN1= (VXN 1-VCM) × CSN1, i.e., VXN1=2 × VCM-VIN 1; similarly, VXP1=2 × VCM-VIP 1; thus, the signal Vin _ core1= VXP1-VXN1= Vin1-VIP1 actually performing a/D conversion, and its output corresponding to a/D conversion is Dout 1.
The second sampling and charge transfer, as shown in fig. 5, since the first sampling already preserves the charge (VIN 1-VCM) × CSN2 on the sampling capacitor CSN2, the conservation of charge by the sampling capacitor CSN2 can be: (VIN 1-VCM) × CSN2= (VIN 2-VXN 2) × CSN2, i.e. VXN2= VCM + VIN2-VIN 1; similarly, VXP2= VCM + VIP2-VIP 1; thus, the signal Vin _ core2= VXP2-VXN2= (VIP 2-VIN 2) - (VIP 1-VIN 1) = V1 for actually performing A/D conversion, and the corresponding output of the signal Vin _ core2 after A/D conversion is Δ Dout 1; meanwhile, the input signal of the second time is sampled to the upper plate of the sampling capacitor CSN1, and the charge (VIN 2-VCM) CSN1 is temporarily stored on the sampling capacitor CSN 1;
for the third sampling and charge transfer, as shown in fig. 6, since the second sampling already preserves the charge (VIN 2-VCM) × CSN1 on the sampling capacitor CSN1, the conservation of charge by the sampling capacitor CSN1 can be: (VIN 2-VCM) × CSN1= (VIN 3-VXN 3) × CSN1, i.e. VXN3= VCM + VIN3-VIN 2; similarly, VXP3= VCM + VIP3-VIP 2; thus, the signal Vin _ core3= VXP3-VXN3= (VIP 3-VIN 3) - (VIP 2-VIN 2) = V2 for actually performing A/D conversion, and the corresponding output of the signal Vin _ core3 after A/D conversion is Δ Dout 2;
so that the following is finally obtained:
the digital output of the first input signal VIP1-VIN1 corresponds to: -Dout 1;
the digital outputs of the second input signal VIP2-VIN2 correspond to: -Dout1 Δ Dout 1;
the digital output of the third input signal VIP3-VIN3 corresponds to: -Dout1 Δ Dout1 Δ Dout 2;
by analogy, the digital output corresponding to the nth input signal VIPn-VINn is:
according to the above analysis, as long as the digital quantization result corresponding to the first input signal is obtained, the subsequent signals can be obtained each time of complete quantization results by accumulating the difference quantization results according to the first digital quantization result. Especially, for some applications, only the difference value between the previous signal and the next signal is concerned, but the absolute value of the difference value is not concerned, and the difference value can be directly used. Most of difference signals are converted by low-weight bits, and high-weight bit conversion is skipped, so that the overall conversion speed is much higher than that of conventional conversion, dynamic power consumption required by high-weight inversion is saved, low-frequency noise and common-mode deviation can be inhibited due to two times of difference operation of adjacent signals, and the design of a high-speed, high-precision and low-power-consumption SAR ADC is easier to realize.
In summary, the successive approximation type analog-to-digital converter and the conversion method thereof of the present invention utilize the conversion result of the first input signal and the conversion result of the difference between every two subsequent adjacent input signals to derive the complete result of each conversion, so as to increase the conversion speed of the ADC, reduce the dynamic power consumption consumed during conversion, and suppress the low-frequency noise and the common-mode deviation. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A successive approximation analog-to-digital converter, comprising:
the sampling circuit is used for obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the current input signal when sampling for the first time; when sampling is not carried out for the first time, obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the difference value of the current input signal and the previous input signal;
the conversion circuit is connected to the output end of the sampling circuit and is used for carrying out analog-to-digital conversion on the difference value of the output voltage of the in-phase end and the output voltage of the anti-phase end to obtain a digital signal corresponding to each sampling;
the digital control circuit is connected with the output end of the conversion circuit and is used for defining the next sampling of the sampling circuit as the first sampling if the weight bit corresponding to the current digital signal is in the set low weight bit range and the difference between the set low weight bit and the weight bit corresponding to the current digital signal is less than a set value when the sampling is not performed for the first time;
the sampling circuit includes: the sampling module comprises a same-phase end sampling module and an opposite-phase end sampling module which have the same circuit structure, wherein both the two sampling modules comprise two sampling units with the same circuit structure;
during first sampling, two sampling units of two sampling modules sample current input signals, and then charge transfer is carried out on one sampling unit so as to obtain output voltage of a non-inverting terminal and output voltage of an inverting terminal based on the current input signals;
when sampling is not performed for the first time, the two sampling units of the two sampling modules sample the current input signal, and simultaneously, charge transfer is performed on the sampling unit which is not subjected to charge transfer for the previous time, so that the output voltage of the in-phase end and the output voltage of the inversion end are obtained based on the difference value of the current input signal and the previous input signal.
2. The successive approximation analog-to-digital converter according to claim 1, wherein the sampling unit comprises: the sampling circuit comprises a sampling capacitor and four switches, wherein two switches of the four switches are connected in series between corresponding input voltage and common mode voltage to form a series node, the other two switches of the four switches are connected in series between the common mode voltage and corresponding output voltage to form another series node, and the sampling capacitor is connected between the two series nodes.
3. The successive approximation analog-to-digital converter according to claim 1 or 2, wherein the digital control circuit is further configured to obtain a conversion output corresponding to the current input signal based on the current digital signal at the time of first sampling; and when the sampling is not carried out for the first time, obtaining the conversion output corresponding to the current input signal based on the current digital signal and all the previous digital signals.
4. The successive approximation analog-to-digital converter according to claim 3, wherein the digital control circuit is further configured to generate a sampling control signal.
5. The successive approximation analog-to-digital converter according to claim 1, wherein the input signal is a low frequency continuously-varying signal.
6. A conversion method of a successive approximation type analog-to-digital converter, the conversion method comprising:
when sampling for the first time, obtaining the output voltage of a non-inverting terminal and the output voltage of an inverting terminal based on the current input signal; when sampling is not carried out for the first time, obtaining the output voltage of the in-phase end and the output voltage of the inversion end based on the difference value of the current input signal and the previous input signal;
performing analog-to-digital conversion on the difference value of the output voltage of the in-phase end and the output voltage of the inversion end to obtain a digital signal corresponding to each sampling;
when the sampling is not the first sampling, if the weight bit corresponding to the current digital signal is in the set low weight bit range and the difference between the set low weight bit and the weight bit corresponding to the current digital signal is less than a set value, defining the next sampling as the first sampling;
the method for obtaining the output voltage of the in-phase end and the output voltage of the inverting end comprises the following steps:
during first sampling, the in-phase end and the inverting end use two sampling capacitors to sample a current input signal, and then charge transfer is carried out on one of the sampling capacitors, so that the in-phase end output voltage and the inverting end output voltage are obtained based on the current input signal;
when sampling is not performed for the first time, the in-phase end and the inverting end use the two sampling capacitors to sample the current input signal, and simultaneously perform charge transfer on the sampling capacitor which has not performed charge transfer for the previous time, so that the in-phase end output voltage and the inverting end output voltage can be obtained based on the difference value of the current input signal and the previous input signal.
7. The conversion method of a successive approximation type analog-to-digital converter according to claim 6, characterized in that the conversion method further comprises: obtaining a conversion output corresponding to the current input signal; the method specifically comprises the following steps: when sampling for the first time, obtaining conversion output corresponding to the current input signal based on the current digital signal; and when the sampling is not carried out for the first time, obtaining the conversion output corresponding to the current input signal based on the current digital signal and all the previous digital signals.
8. The method of claim 6, wherein the input signal is a low frequency continuous slow varying signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110628624.8A CN113078906B (en) | 2021-06-07 | 2021-06-07 | Successive approximation type analog-to-digital converter and conversion method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110628624.8A CN113078906B (en) | 2021-06-07 | 2021-06-07 | Successive approximation type analog-to-digital converter and conversion method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113078906A CN113078906A (en) | 2021-07-06 |
| CN113078906B true CN113078906B (en) | 2021-08-27 |
Family
ID=76617071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110628624.8A Active CN113078906B (en) | 2021-06-07 | 2021-06-07 | Successive approximation type analog-to-digital converter and conversion method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113078906B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166644A (en) * | 2013-04-11 | 2013-06-19 | 东南大学 | Low power consumption successive approximation type analog-digital converter and converting method of low power consumption successive approximation type analog-digital converter |
| CN105007079A (en) * | 2015-07-01 | 2015-10-28 | 西安交通大学 | Fully differential increment sampling method of successive approximation type analog-digital converter |
| CN106301364A (en) * | 2016-08-25 | 2017-01-04 | 东南大学 | A kind of gradual approaching A/D converter structure and low power consumption switch method thereof |
| CN108631778A (en) * | 2018-05-10 | 2018-10-09 | 上海华虹宏力半导体制造有限公司 | Gradually-appoximant analog-digital converter and conversion method |
| CN111786675A (en) * | 2020-07-22 | 2020-10-16 | 电子科技大学 | Charge sharing type analog-to-digital converter quantization method based on dynamic tracking |
| CN112187281A (en) * | 2020-10-03 | 2021-01-05 | 天津理工大学 | Switched capacitor oversampling delta-sigma modulator circuit |
| CN112367084A (en) * | 2020-11-23 | 2021-02-12 | 电子科技大学 | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9673832B2 (en) * | 2015-05-15 | 2017-06-06 | Mediatek Inc. | Successive approximation analog-to-digital converter and accuracy improving method thereof |
-
2021
- 2021-06-07 CN CN202110628624.8A patent/CN113078906B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166644A (en) * | 2013-04-11 | 2013-06-19 | 东南大学 | Low power consumption successive approximation type analog-digital converter and converting method of low power consumption successive approximation type analog-digital converter |
| CN105007079A (en) * | 2015-07-01 | 2015-10-28 | 西安交通大学 | Fully differential increment sampling method of successive approximation type analog-digital converter |
| CN106301364A (en) * | 2016-08-25 | 2017-01-04 | 东南大学 | A kind of gradual approaching A/D converter structure and low power consumption switch method thereof |
| CN108631778A (en) * | 2018-05-10 | 2018-10-09 | 上海华虹宏力半导体制造有限公司 | Gradually-appoximant analog-digital converter and conversion method |
| CN111786675A (en) * | 2020-07-22 | 2020-10-16 | 电子科技大学 | Charge sharing type analog-to-digital converter quantization method based on dynamic tracking |
| CN112187281A (en) * | 2020-10-03 | 2021-01-05 | 天津理工大学 | Switched capacitor oversampling delta-sigma modulator circuit |
| CN112367084A (en) * | 2020-11-23 | 2021-02-12 | 电子科技大学 | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113078906A (en) | 2021-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101783684B (en) | Pipelined analog-to-digital converter | |
| US5936566A (en) | Auto-reference pseudo-flash analog to digital converter | |
| KR101020672B1 (en) | Analog-to-digital conversion using asynchronous current-mode cyclic comparison | |
| CN106230439B (en) | A method of improving the pipeline-type gradually-appoximant analog-digital converter linearity | |
| CN111711453B (en) | Successive approximation type analog-to-digital converter | |
| Bashir et al. | Analog-to-digital converters: A comparative study and performance analysis | |
| CN102545901A (en) | Second-order feedforward Sigma-Delta modulator based on successive comparison quantizer | |
| CN100546195C (en) | A kind of improved voltage marking D/A converter | |
| CN114499520A (en) | ADC circuit and control method thereof | |
| CN110690901A (en) | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit | |
| Aytar et al. | Employing threshold inverter quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC) | |
| Kar et al. | Design of ultra low power flash ADC using TMCC & bit referenced encoder in 180nm technology | |
| CN113078906B (en) | Successive approximation type analog-to-digital converter and conversion method thereof | |
| CN111034052A (en) | Method and apparatus for enabling wide input common mode range in a SAR ADC without additional active circuitry | |
| EP2629426A1 (en) | Device, system and method for analogue-to-digital conversion with noise shaping function | |
| CN102857226A (en) | Successive approximation type analog-to-digital converter | |
| CN112187265A (en) | Mixed type analog-digital converter and signal transceiver for electric power special communication network | |
| CN113612480B (en) | Successive approximation type analog-to-digital converter based on segmented differential capacitor array | |
| CN102281069B (en) | Analog-to-digital conversion circuit | |
| CN1169217A (en) | A/D conversion with folding and interpolation | |
| Zhu et al. | An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC | |
| CN112994699B (en) | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method | |
| CN201138796Y (en) | Improved voltage scaling digital to analog converter | |
| Hwang et al. | A range-scaled 13b 100MS/s 0.13 μm CMOS SHA-free ADC based on a single reference | |
| JP2001053612A (en) | Sequential comparison type ad converter and microcomputer having same built in |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |