CN114499520A

CN114499520A - ADC circuit and control method thereof

Info

Publication number: CN114499520A
Application number: CN202210124222.9A
Authority: CN
Inventors: 刘维辉; 陈敏
Original assignee: Chipsea Technologies Shenzhen Co Ltd
Current assignee: Chipsea Technologies Shenzhen Co Ltd
Priority date: 2022-02-10
Filing date: 2022-02-10
Publication date: 2022-05-13
Also published as: WO2023151632A1

Abstract

The invention provides an ADC circuit and a control method thereof, belonging to the technical field of electronics. The ADC circuit at least comprises: the analog-to-digital conversion module and the calibration module; the analog-to-digital conversion module is configured to output a corresponding first digital signal based on the sampled first signal when a first control signal is at a first level and output a corresponding second digital signal based on the sampled second signal when the first control signal is at a second level during conversion; the calibration module is connected with the analog-to-digital conversion module and configured to determine a calibration code based on a mismatch code obtained during calibration and perform calibration code compensation on the analog-to-digital conversion module; wherein the first control signal switches levels during sampling. By adopting the invention, the continuous calibration of the differential mode and the single-ended mode of the analog-digital conversion module can be realized.

Description

ADC circuit and control method thereof

Technical Field

The invention relates to the technical field of electronics, in particular to an ADC circuit and a control method thereof.

Background

In the field of electronics, Analog-to-Digital Converter (ADC) circuits may be used for signal measurement to convert Analog signals into Digital signals.

In some application scenarios, it is necessary to support continuous measurement of differential signals and single-ended signals of different input channels. At present, it is a conventional practice to process differential signals and single-ended signals respectively by switching the ADC operation mode and using the differential mode and the single-ended mode.

However, the conventional ADC cannot continuously operate two working modes, for example, after differential signals are processed, the ADC is reconfigured and single-ended signals are processed, and redundant mode switching time exists in the middle, so that the ADC cannot continuously operate. And when the requirement on the ADC precision is higher, the ADC needs to be calibrated, and the traditional method cannot continuously calibrate the ADC differential mode and the single-ended mode.

Disclosure of Invention

In order to solve the problems in the prior art, embodiments of the present invention provide an ADC circuit and a control method thereof. The technical scheme is as follows:

according to an aspect of the present invention, there is provided an ADC circuit including at least: the analog-to-digital conversion module and the calibration module;

the analog-to-digital conversion module is configured to output a corresponding first digital signal based on the sampled first signal when a first control signal is at a first level and output a corresponding second digital signal based on the sampled second signal when the first control signal is at a second level during conversion;

the calibration module is connected with the analog-to-digital conversion module and configured to determine a calibration code based on a mismatch code obtained during calibration and perform calibration code compensation on the analog-to-digital conversion module;

wherein the first control signal switches levels during sampling.

Optionally, the calibration module includes a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module;

the calibration algorithm module has an input end connected to the analog-to-digital conversion module and an output end connected to the calibration control module, and is configured to determine a first calibration code corresponding to the first signal based on the mismatch code when the first control signal is at the first level; when the first control signal is at the second level, determining a second calibration code corresponding to the second signal based on the mismatch code;

the calibration control module is configured to transmit the calibration code currently output by the calibration algorithm module to the calibration digital-to-analog conversion module during the conversion period;

the calibration digital-to-analog conversion module is configured to perform voltage compensation on the digital-to-analog conversion module based on a currently received calibration code during the conversion.

Optionally, the calibration algorithm module is further configured to store the mismatch code.

Optionally, the calibration control module is further configured to set a calibration code as a preset intermediate calibration code during the sampling period, and transmit the intermediate calibration code to the calibration digital-to-analog conversion module.

Optionally, the ADC circuit further includes an input preprocessing module, and an output end of the input preprocessing module is connected to an input end of the analog-to-digital conversion module;

the input preprocessing module is used for receiving an input signal and is configured to output the first signal based on the input signal when a second control signal is at a third level matched with the first level; outputting the second signal based on the input signal when the second control signal is a fourth level matching the second level;

wherein the second control signal switches level during the transition.

Optionally, the input preprocessing module at least comprises a first switch;

the first switch is configured to switch the signal output by the input preprocessing module based on the second control signal.

Optionally, when the second control signal is at the third level, one end of the first switch is used for connecting a negative-end input voltage to the negative end of the input preprocessing module, and the other end of the first switch is connected to the analog-to-digital conversion module;

when the second control signal is at the fourth level, one end of the first switch is used for connecting a first preset voltage to the negative end of the input preprocessing module, and the other end of the first switch is connected with the analog-to-digital conversion module.

Optionally, the analog-to-digital conversion module includes a digital-to-analog conversion module, a comparison module and a logic module, and the digital-to-analog conversion module is used for sample holding and quantization;

the digital-to-analog conversion module is connected with the input preprocessing module and is configured to execute a first working mode corresponding to the first signal when the first control signal is at the first level during the conversion; when the first control signal is at the second level, executing a second working mode corresponding to the second signal;

the input end of the comparison module is connected with the digital-to-analog conversion module, and the output end of the comparison module is connected with the logic module;

the logic module is configured to output a digital signal corresponding to the input signal.

Optionally, the digital-to-analog conversion module includes a positive-end digital-to-analog conversion module and a negative-end digital-to-analog conversion module, the positive-end digital-to-analog conversion module is adapted to the second switch, and the negative-end digital-to-analog conversion module is adapted to the third switch;

during the course of the said transition period, the said switching period,

when the first control signal is at the first level, the second switch and the third switch are adapted to the first operating mode;

when the first control signal is at the second level, the second switch is adapted to the second working mode, and the third switch is used for connecting a second preset voltage to the negative terminal digital-to-analog conversion module.

Optionally, a difference between the second preset voltage and the first preset voltage accessed to the input preprocessing module is not greater than a difference threshold.

Optionally, the logic module is further configured to quantize the error voltage of the digital-to-analog conversion module during calibration to obtain the mismatch code.

According to another aspect of the present invention, there is provided a control method of an ADC circuit including at least: the method comprises an analog-to-digital conversion module and a calibration module, and comprises the following steps:

during the conversion, when a first control signal is at a first level, outputting a corresponding first digital signal based on the sampled first signal, and when the first control signal is at a second level, outputting a corresponding second digital signal based on the sampled second signal;

during the conversion period, determining a calibration code based on a mismatch code obtained during the calibration period through the calibration module, and performing calibration code compensation on the analog-to-digital conversion module;

wherein the first control signal switches levels during sampling.

the determining, by the calibration module, a calibration code based on a mismatch code obtained during calibration, and performing calibration code compensation on the analog-to-digital conversion module includes:

when the first control signal is at the first level, determining, by the calibration algorithm module, a first calibration code corresponding to the first signal based on the mismatch code; when the first control signal is at the second level, determining, by the calibration algorithm module, a second calibration code corresponding to the second signal based on the mismatch code;

transmitting the calibration code currently output by the calibration algorithm module to the calibration digital-to-analog conversion module;

and on the basis of the calibration digital-to-analog conversion module, performing voltage compensation on the analog-to-digital conversion module according to the currently received calibration code.

Optionally, the method further includes:

the mismatch code is stored based on the calibration algorithm module.

Optionally, the method further includes:

and during the sampling period, setting the voltage of the calibration digital-to-analog conversion module as a preset intermediate calibration code.

Optionally, the ADC circuit further includes an input preprocessing module, and the method further includes:

receiving an input signal;

when the second control signal is a third level matched with the first level, acquiring a first signal based on the input signal through the input preprocessing module;

when the second control signal is a fourth level matched with the second level, acquiring a second signal based on the input signal through the input preprocessing module;

wherein the second control signal switches level during the transition.

Optionally, the input preprocessing module at least comprises a first switch;

the method further comprises the following steps: and controlling the first switch based on the second control signal to switch the signal output by the input preprocessing module.

Optionally, the controlling the first switch based on the second control signal to switch the signal output by the input preprocessing module includes:

when the second control signal is at the third level, controlling the first switch to connect a negative terminal input voltage from the negative terminal of the input preprocessing module to the analog-to-digital conversion module; connecting a positive end input voltage to the analog-to-digital conversion module from the positive end of the input preprocessing module;

when the second control signal is at the fourth level, controlling the first switch to connect a first preset voltage to the analog-to-digital conversion module from the negative end of the input preprocessing module; and connecting a positive end input voltage into the analog-to-digital conversion module from the positive end of the input preprocessing module.

the sampling-based first signal outputs a corresponding first digital signal, comprising: controlling the digital-to-analog conversion module to execute a first working mode corresponding to the first signal; outputting a first digital signal corresponding to the first signal based on the logic module;

the sampling-based second signal outputs a corresponding second digital signal, comprising: controlling the digital-to-analog conversion module to execute a second working mode corresponding to the second signal; and outputting a second digital signal corresponding to the second signal based on the logic module.

the method further comprises the following steps:

when the first control signal is at the first level, controlling the second switch and the third switch to adapt to the first working mode;

and when the first control signal is at the second level, controlling the second switch to adapt to the second working mode, and controlling the third switch to access a second preset voltage to the negative terminal digital-to-analog conversion module.

Optionally, the method further includes:

and during the calibration period, the error voltage of the digital-to-analog conversion module is quantized by multiplexing the logic module to obtain the mismatch code.

According to another aspect of the invention, a chip is provided, which comprises the ADC circuit described above.

According to another aspect of the present invention, there is provided an electronic apparatus including:

the ADC circuit described above;

a processor; and

a memory for storing a program, wherein the program is stored in the memory,

wherein the program includes instructions that, when executed by the processor, cause the processor to execute the control method of the ADC circuit described above.

According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the control method of the ADC circuit described above.

In the embodiment of the invention, through the first control signal, the ADC circuit can realize continuous calibration of two different working modes, and the ADC circuit does not need to be restarted to configure the different working modes.

Drawings

Further details, features and advantages of the invention are disclosed in the following description of exemplary embodiments with reference to the accompanying drawings, in which:

fig. 1 is a schematic diagram illustrating an ADC circuit structure provided in accordance with an exemplary embodiment of the present invention;

fig. 2 is a schematic diagram illustrating an ADC circuit structure provided in accordance with an exemplary embodiment of the present invention;

FIG. 3 illustrates a timing control diagram provided in accordance with an exemplary embodiment of the present invention;

fig. 4 shows a schematic diagram of a SAR ADC circuit structure provided according to an exemplary embodiment of the present invention;

FIG. 5 illustrates a schematic diagram of an ADC circuit provided in accordance with an exemplary embodiment of the present invention;

FIG. 6 illustrates a timing control diagram provided in accordance with an exemplary embodiment of the present invention;

FIG. 7 illustrates a schematic diagram of an input pre-processing module provided in accordance with an exemplary embodiment of the present invention;

fig. 8 is a schematic diagram illustrating an ADC circuit structure provided in accordance with an exemplary embodiment of the present invention;

fig. 9 shows a schematic diagram of a SAR ADC circuit structure provided according to an exemplary embodiment of the present invention;

fig. 10 is a flowchart illustrating a control method of an ADC circuit provided according to an exemplary embodiment of the present invention;

fig. 11 is a flowchart illustrating a calibration control method of an ADC circuit according to an exemplary embodiment of the present invention;

fig. 12 is a flowchart illustrating a control method of an ADC circuit provided according to an exemplary embodiment of the present invention;

FIG. 13 illustrates a schematic diagram of switch states during sampling provided in accordance with an exemplary embodiment of the present invention;

FIG. 14 illustrates a schematic diagram of switch states during sampling provided in accordance with an exemplary embodiment of the present invention;

FIG. 15 illustrates a schematic diagram of switch states during transitions provided in accordance with an exemplary embodiment of the present invention;

FIG. 16 illustrates a schematic diagram of switch states during transitions provided in accordance with an exemplary embodiment of the present invention;

FIG. 17 illustrates a block diagram of an exemplary electronic device that can be used to implement an embodiment of the invention.

Detailed Description

Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and the embodiments of the present invention are illustrative only and are not intended to limit the scope of the present invention.

It should be understood that the various steps recited in the method embodiments of the present invention may be performed in a different order and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the invention is not limited in this respect.

The term "including" and variations thereof as used herein is intended to be open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present invention are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.

It is noted that references to "a", "an", and "the" modifications in the present invention are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.

The names of messages or information exchanged between devices in the embodiments of the present invention are for illustrative purposes only, and are not intended to limit the scope of the messages or information.

An embodiment of the present invention provides an ADC circuit, as shown in fig. 1, the ADC circuit at least includes: the device comprises an analog-to-digital conversion module and a calibration module.

An analog-to-digital conversion module configured to output a corresponding first digital signal based on the sampled first signal when the first control signal is at a first level and output a corresponding second digital signal based on the sampled second signal when the first control signal is at a second level during conversion;

the calibration module is connected with the analog-to-digital conversion module and configured to determine a calibration code based on the mismatch code obtained during calibration and perform calibration code compensation on the analog-to-digital conversion module;

wherein the first control signal switches levels during sampling.

In a possible implementation, the input signal of the first signal may be a differential signal, and the first signal may be a corresponding differential signal; the input signal of the second signal may be a single-ended signal, and the second signal may be a corresponding pseudo-differential signal.

Optionally, as shown in fig. 2, the ADC circuit, wherein the calibration module may include a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module. The ADC circuit may be controlled by the timing sequence shown in fig. 3, where sar _ clk refers to a clock control signal, sar _ sample refers to a sampling control signal, DIFF _ EN1 refers to a first control signal, CALCODE _ I < M:1> refers to a calibration code output by the calibration algorithm module, CALCODE _ P/N < M:1> refers to a calibration code output by the calibration control module, and the number of M bits is determined by the number of bits of the calibration dac module.

The input end of the calibration algorithm module is connected with the analog-to-digital conversion module, the output end of the calibration algorithm module is connected with the calibration control module, and the calibration algorithm module is configured to determine a first calibration code corresponding to the first signal based on the mismatch code when the first control signal is at a first level; when the first control signal is at a second level, determining a second calibration code corresponding to the second signal based on the mismatch code;

the calibration control module is configured to transmit the calibration code currently output by the calibration algorithm module to the calibration digital-to-analog conversion module during conversion;

and the calibration digital-to-analog conversion module is configured to perform voltage compensation on the digital-to-analog conversion module based on the currently received calibration code during conversion.

In one possible implementation, when the ADC circuit is a SAR ADC circuit, the corresponding circuit after adding the calibration module is shown in fig. 4. The input end of the calibration algorithm module is connected with the successive approximation search logic module. The calibration digital-to-analog conversion module, which may be a calibration differential capacitor array (CALDACP/CALDACN), is coupled to the input of the comparator and may be configured to complement the voltage at the input of the comparator during conversion based on a currently received calibration code.

In addition to the calibration differential capacitor array shown in fig. 4, the calibration digital-to-analog conversion module may also adopt other circuit structures, such as a capacitor resistor array, and the specific circuit structure of the calibration digital-to-analog conversion module is not limited in this embodiment.

Optionally, the calibration control module is further configured to set the calibration code as a preset intermediate calibration code during the sampling period, and transmit the intermediate calibration code to the calibration digital-to-analog conversion module.

Optionally, as shown in the schematic structural diagram of the ADC circuit shown in fig. 5, the ADC circuit further includes an input preprocessing module, and an output end of the input preprocessing module is connected to an input end of the analog-to-digital conversion module. The ADC circuit may be controlled by the timing shown in fig. 6, where DIFF _ EN2 refers to the second control signal.

The input preprocessing module is used for receiving an input signal and is configured to output a first signal based on the input signal when the second control signal is at a third level matched with the first level; outputting the second signal based on the input signal when the second control signal is a fourth level matching the second level;

wherein the second control signal switches levels during the transition.

Optionally, the input preprocessing module may include at least a first switch;

and the first switch is configured to switch the signal output by the input preprocessing module based on the second control signal.

As shown in the schematic diagram of the input pre-processing module of FIG. 7, the first switch may be disposed at the negative terminal of the input pre-processing module.

In a possible implementation manner, the positive end of the input preprocessing module can also be provided with a switch which is the same as the first switch, so as to reduce the output voltage offset between the positive end and the negative end of the input preprocessing module and improve the accuracy of analog-to-digital conversion.

In another possible embodiment, the switch may not be provided at the positive terminal of the input preprocessing module, and the positive terminal input voltage is connected to the analog-to-digital conversion module. The present embodiment is not limited to whether the switch is provided at the positive terminal of the input preprocessing module.

Optionally, when the second control signal is at a third level, one end of the first switch is used for connecting a negative terminal input voltage to the negative terminal of the input preprocessing module, and the other end of the first switch is connected to the analog-to-digital conversion module;

when the second control signal is at a fourth level, one end of the first switch is used for connecting a first preset voltage to the negative end of the input preprocessing module, and the other end of the first switch is connected with the analog-to-digital conversion module.

Optionally, as shown in fig. 8, the ADC circuit, wherein the analog-to-digital conversion module may include a digital-to-analog conversion module, a comparison module and a logic module, and the digital-to-analog conversion module may be used for sample holding and quantization. The quantization may be performed in a successive approximation manner, or may be performed in other manners, which is not limited in this embodiment.

The digital-to-analog conversion module is connected with the input preprocessing module and is configured to execute a first working mode corresponding to a first signal when a first control signal is at a first level during conversion; when the first control signal is at a second level, executing a second working mode corresponding to the second signal;

and the logic module is configured to output a digital signal corresponding to the input signal.

In one possible implementation, as shown in fig. 9, in a SAR ADC (Successive Approximation Analog-to-Digital Converter) circuit, the Digital-to-Analog conversion module may be a Digital-to-Analog conversion differential capacitor array (DAC), the comparison module may be a Comparator (COMP), and the logic module may be a SAR logic module.

during the course of the transition period, the switching operation,

when the first control signal is at a first level, the second switch and the third switch are adapted to a first working mode;

when the first control signal is at a second level, the second switch is adapted to the second working mode, and the third switch is used for connecting a second preset voltage to the negative terminal digital-to-analog conversion module.

During sampling, the second switch is used for connecting the positive end output voltage of the input preprocessing module to the positive end digital-to-analog conversion module, and the third switch is used for connecting the negative end output voltage of the input preprocessing module to the negative end digital-to-analog conversion module.

The ADC circuit described above can realize continuous conversion of a differential signal and a single-ended signal under the control of the first control signal and the second control signal.

Optionally, the logic module is further configured to quantize an error voltage of the digital-to-analog conversion module during calibration to obtain a mismatch code. That is to say, during calibration, the existing logic modules in the analog-to-digital conversion module can be multiplexed to calculate the mismatch code, and no logic module needs to be additionally added in the subsequent calibration module, so that the logic complexity of the calibration module is optimized, and the area of the ADC circuit is reduced.

The ADC circuit can also realize continuous conversion of the differential signal and the single-ended signal on the basis of realizing continuous calibration of the differential signal and the single-ended signal. Due to the fact that the logic module is multiplexed, another logic module does not need to be additionally added, logic complexity of the calibration module is optimized, and the area of the ADC circuit is reduced.

The embodiment of the invention provides a control method of an ADC (analog to digital converter) circuit, which can be used for controlling the ADC circuit. The control method will be described with reference to a flowchart of the control method of the ADC circuit shown in fig. 10.

First, the timing control relationship shown in fig. 3 and 6 will be described.

The clock control signal sar _ clk, the sampling control signal sar _ sample, the first control signal DIFF _ EN1, and the second control signal DIFF _ EN2 may be set in advance in the electronic apparatus to the ADC circuit.

When the sampling control signal is at a high level, the ADC circuit is in a sampling period and executes sampling related processing; when the sampling control signal is at a low level, the ADC circuit is in a conversion period, and conversion-related processing is performed. As shown in fig. 3 and 6, the sar _ sample may be initially at a low level, switched from the low level to the high level at the 2 nd rising edge of sar _ clk, and switched from the high level to the low level at the 4 th rising edge, and the sampling period is 2 clock cycles; the 4 th rising edge of sar _ clk switches from high to low, and the 16 th rising edge switches from low to high, with a transition period of 12 clock cycles. In this embodiment, the initial level of the sampling control signal, the position of the specific switching level, the sampling period, and the conversion period are not limited.

In this embodiment, the first control signal may be used to control an operation mode of the ADC circuit during the conversion, and specifically, may be used to control an operation mode of a digital-to-analog conversion module (DAC) in the analog-to-digital conversion module during the conversion, and when the ADC circuit includes the calibration module, control an operation mode of the calibration module. In order to ensure that the ADC circuit can be configured with the corresponding operating mode in advance before conversion, the first control signal may be switched before the sampling control signal is switched to the low level, that is, the first control signal may be switched in level during sampling, and the switching of the first control signal does not affect the sampling function of the digital-to-analog conversion module.

In a preferred embodiment, the first control signal may switch levels before the sampling control signal, avoiding an impact on the switching. As shown in fig. 3 and 6, DIFF _ EN1 may switch earlier than sar _ sample during sampling, such as DIFF _ EN1 switching from low to high on the 3 rd rising edge of sar _ clk, or from low to high on the 2 nd or 3 rd falling edge. The present embodiment does not limit the specific switching level position of the first control signal.

In this embodiment, the second control signal may be used to control an output voltage mode of the input preprocessing module, and in order to ensure that the external input signal can be processed in advance before sampling by the ADC circuit, the second control signal may be switched before the sampling control signal is switched to a high level, that is, the second control signal may be switched to a level during the conversion.

In a preferred embodiment, the second control signal may switch levels 1 clock cycle or more before the sampling control signal, so as to avoid affecting the sampling. As shown in fig. 6, DIFF _ EN2 may switch 1 clock cycle or more ahead of sar _ sample during the transition, such as DIFF _ EN2 switching from low to high on the 1 st rising edge of sar _ clk; during the conversion of the ADC circuit, DIFF _ EN2 may switch from high to low on the 5 th rising edge of sar _ clk, or from high to low on the 15 th rising edge. The present embodiment does not limit the position of the specific switching level of the second control signal.

Next, a control method of the ADC circuit shown in fig. 10 will be described.

In step 1001, during the conversion, when the first control signal is at the first level, the corresponding first digital signal is output based on the sampled first signal, and when the first control signal is at the second level, the corresponding second digital signal is output based on the sampled second signal.

The first control signal may control a working mode of the ADC circuit, so that the ADC circuit may execute a first working mode corresponding to the differential signal or a second working mode corresponding to the single-ended signal, and output a digital signal corresponding to the differential signal or the single-ended signal. The first level may be a high level or a low level, which is not limited in this embodiment. The second level is opposite to the first level, and when the first level is a high level, the second level is a low level; when the first level is a low level, the second level is a high level.

In one possible implementation, the ADC circuit may collect signals of a plurality of channels outside the circuit, where the collected signals may include at least a differential signal and a single-ended signal. For differential signals, there may be two channel inputs, for example, channel X and channel X-1, where the signal of channel X may be the positive input signal VINP of the digital-to-analog conversion module, and the signal of channel X-1 is the negative input signal VINN of the digital-to-analog conversion module. For single-ended signals, there may be one channel input, e.g., channel X-2, and the signal of channel X-2 may be the positive side input signal VINP of the digital-to-analog conversion module.

During sampling, the acquired signal may be sampled based on a digital-to-analog conversion module. During different sampling periods, the differential signal and the single-ended signal can be alternately sampled based on the digital-to-analog conversion module, that is, if the differential signal is sampled during the current sampling period, the single-ended signal is sampled during the next sampling period; if the single-ended signal is sampled during the current sampling period, the differential signal is sampled during the next sampling period.

During the conversion, if the differential signal (i.e. the first signal) is sampled during the corresponding sampling period, the sampled differential signal can be converted to output a corresponding first digital signal; if the single-ended signal (i.e., the second signal) is sampled during the corresponding sampling period, the sampled single-ended signal may be converted to output a corresponding second digital signal.

In the conversion period, a calibration code is determined by the calibration module based on the mismatch code obtained in the calibration period, and the analog-to-digital conversion module is compensated by the calibration code.

In one possible implementation, during calibration, the error voltage of the digital-to-analog conversion module may be quantized to obtain a mismatch code. Furthermore, during the conversion period, the calibration code can be input into the analog-to-digital conversion module through the calibration module, and the error voltage of the digital-to-analog conversion module is compensated back, so that the calibration of the digital signal output by the analog-to-digital conversion module is realized, and the precision of the ADC circuit is improved.

Optionally, the calibration module includes a calibration digital-to-analog conversion module, a calibration algorithm module, and a calibration control module. On the basis, as shown in the flowchart of the calibration control method of the ADC circuit shown in fig. 11, the step 1002 can be as the following steps 1101-1103.

Step 1101, when the first control signal is at a first level, determining a first calibration code corresponding to the first signal based on the mismatch code through a calibration algorithm module; and when the first control signal is at the second level, determining a second calibration code corresponding to the second signal based on the mismatch code through the calibration algorithm module.

In a possible implementation manner, the first control signal may control an operation mode of the calibration algorithm module, so that the calibration algorithm module calculates and outputs a first calibration code corresponding to the differential signal or a second calibration code corresponding to the single-ended signal. The operating mode of the calibration algorithm module corresponds to the operating mode of the ADC circuit during the conversion described above.

When the first control signal is at the first level, the operating mode is a first operating mode corresponding to the differential signal, and during the conversion, the calibration algorithm module may calculate a first calibration code of the differential signal based on an offset of the digital-to-analog conversion module and an error voltage of capacitance mismatch, and store the first calibration code in the calibration algorithm module.

When the first control signal is at the second level, the working mode is a second working mode corresponding to the single-ended signal, and during the conversion period, the calibration algorithm module may calculate a second calibration code of the single-ended signal based on the offset of the digital-to-analog conversion module and the error voltage of the capacitance mismatch, and store the second calibration code in the calibration algorithm module.

Step 1102, the calibration code currently output by the calibration algorithm module is transmitted to the calibration digital-to-analog conversion module.

In one possible embodiment, the SAR logic control signal may control the calibration differential capacitance array by controlling a calibration control module, an output of which is determined by an output of the calibration algorithm module. As shown in the SAR ADC circuit of fig. 9, during the conversion, when the first control signal is at the first level, the calibration code CALCODE _ I < M:1> output by the calibration algorithm module is a differential calibration code (i.e. the first calibration code), and at this time, the calibration control module may respectively output a positive side calibration code CALCODE _ P < M:1> and a negative side calibration code CALCODE _ N < M:1> to be transmitted to the calibration differential capacitor array. The positive side calibration code CALCODE _ P < M:1> can be input into the positive side capacitor array of the calibration differential capacitor array, and the negative side calibration code CALCODE _ N < M:1> can be input into the negative side capacitor array of the calibration differential capacitor array.

When the first control signal is at the second level, the calibration code CALCODE _ I < M:1> output by the calibration algorithm module is a single-ended calibration code (i.e., the second calibration code), and the subsequent processing of the calibration control module is similar to the above-mentioned processing, which is not described herein again.

Step 1103, performing voltage compensation on the analog-to-digital conversion module according to the currently received calibration code based on the calibration digital-to-analog conversion module.

In one possible embodiment, as shown in the SAR ADC circuit of fig. 4, during the conversion, when the first control signal is at the first level, the positive side capacitor array of the calibration differential capacitor array may receive the differential calibration code CALCODE _ P < M:1>, and the calibration code value CALCODE _ P < M:1> is compensated back to the voltage at the positive input terminal of the comparator; the negative side capacitor array of the calibration differential capacitor array may receive a differential calibration code CALCODE _ N < M:1>, and may complement the calibration code value CALCODE _ N < M:1> back to the voltage at the negative input of the comparator.

When the first control signal is at the second level, the calibration differential capacitor array may receive the single-ended calibration code, and perform a compensation on the voltage at the input end of the comparator.

During the sampling period before the above step 1103, a compensation reset may also be performed, and the voltage of the calibration digital-to-analog conversion module is set to a preset intermediate calibration code. As shown in the CALCODE _ P/N < M:1> of fig. 3, during the sampling period, the calibration control module outputs a preset intermediate calibration code according to the sampling control signal, transmits the intermediate calibration code to the calibration differential capacitor array, and sets the calibration differential capacitor array to an intermediate calibration code value, so as to prepare for compensating the error voltage which can be positive or negative during the normal conversion period.

The control method described above can realize continuous calibration of differential signals and single-ended signals, and further, can realize continuous conversion of differential signals and single-ended signals through the control method flowchart of the ADC circuit shown in fig. 12. At this time, the ADC circuit further includes an input preprocessing module, and the control method is as follows in steps 1201-1203.

Step 1201, receiving an input signal;

step 1202, when the second control signal is a third level matched with the first level, acquiring a first signal based on the input signal through the input preprocessing module;

in step 1203, when the second control signal is at a fourth level matched with the second level, a second signal is obtained based on the input signal through the input preprocessing module.

The third level may be a high level or a low level, which is not limited in this embodiment. The fourth level is opposite to the third level, and when the third level is the high level, the fourth level is the low level; when the third level is a low level, the fourth level is a high level.

In one possible embodiment, as described above with reference to step 1001, there may be two inputs for the differential signal, such as channel X and channel X-1, where the signal of channel X may be used as the positive input signal VINP of the input pre-processing module and the signal of channel X-1 is the negative input signal VINN of the input pre-processing module. For single-ended signals, there may be one channel input, e.g., channel X-2, and the signal of channel X-2 may be the positive side input signal VINP to the input pre-processing block.

The second control signal may control an output voltage mode of the input preprocessing module, so that the input preprocessing module may output a first signal corresponding to a differential signal or a second signal corresponding to a single-ended signal.

When the second control signal is at the third level, the output voltage mode of the input pre-processing module may be a differential mode, and at this time, the positive-side output signal VIN + of the input pre-processing module may be the signal VINP of the channel X, and the negative-side output signal VIN-may be the signal VINN of the channel X-1.

When the second control signal is at the fourth level, the output voltage mode of the input pre-processing module may be a single-ended mode, and at this time, the positive-side output signal VIN + of the input pre-processing module may be the signal VINP of the channel X-2, and the negative-side output signal VIN-may be the first preset voltage. The first preset voltage may be a built-in positive-side reference voltage VREFN, a built-in negative-side reference voltage VREFP, or other fixed voltage values, and the later second preset voltage is the same or different, and this embodiment does not limit this.

Optionally, the input preprocessing module at least includes a first switch, and switching of outputting the first signal or the second signal may be implemented by the first switch, specifically, the signal output by the input preprocessing module may be switched by controlling the first switch based on the second control signal.

The control method of the first switch may be as follows:

when the second control signal is at a third level, controlling the first switch to enable the negative terminal input voltage to be connected to the analog-to-digital conversion module from the negative terminal of the input preprocessing module; the input voltage of the positive end is connected to the analog-to-digital conversion module from the positive end of the input preprocessing module;

when the second control signal is at a fourth level, controlling the first switch to connect the first preset voltage to the analog-to-digital conversion module from the negative end of the input preprocessing module; and connecting the positive end input voltage into the analog-to-digital conversion module from the positive end of the input preprocessing module.

Specifically, as shown in fig. 13 and 14, in the switching state during sampling, for example, the positive and negative terminals of the input preprocessing module include switches, where the switch at the positive terminal is used to connect the input voltage at the positive terminal to the analog-to-digital conversion module; the switch of the negative terminal is used for connecting the input voltage of the negative terminal or a first preset voltage to the analog-digital conversion module. The switch at the negative terminal corresponds to the first switch.

One specific implementation of the first control signal controlling the output voltage mode of the input pre-processing module is as follows:

when the second control signal is at the third level, one end of the switch at the positive terminal can be used for receiving the input voltage at the positive terminal, and the other end of the switch at the positive terminal is connected with the analog-to-digital conversion module; one end of the switch of the negative end is used for receiving the input voltage of the negative end, and the other end of the switch of the negative end is connected with the analog-to-digital conversion module. At this time, the output voltage mode is a differential mode, VIN + ═ VINP, VIN- ═ VINN, the input preprocessing module outputs a first signal corresponding to the differential signal, VINP is input to the positive terminal of the digital-to-analog conversion module, and VINN is input to the negative terminal of the digital-to-analog conversion module.

When the second control signal is at the fourth level, one end of the switch at the positive terminal can be used for receiving the input voltage at the positive terminal, and the other end of the switch at the positive terminal is connected with the analog-to-digital conversion module; one end of the switch at the negative end is used for receiving a first preset voltage, and the other end of the switch at the negative end is connected with the analog-to-digital conversion module. At this time, the output voltage mode is a single-ended mode, VIN + ═ VINP, VIN- ═ first preset voltage, the input preprocessing module outputs a second signal corresponding to the single-ended signal, and inputs VINP to the positive terminal of the digital-to-analog conversion module, and inputs the first preset voltage to the negative terminal of the digital-to-analog conversion module.

Optionally, the analog-to-digital conversion module may include a digital-to-analog conversion module, a comparison module, and a logic module, where the digital-to-analog conversion module is used for sample holding and quantization. The analog-to-digital conversion module may sample and convert an input analog signal to output a corresponding digital signal.

During the sampling period, no matter in a differential mode or a single-ended mode, the digital-to-analog conversion module can sample the signal output by the input preprocessing module without modifying the circuit structure of the digital-to-analog conversion module.

During the conversion, for the above step 1001, when the first control signal is at the first level, the control method for the analog-to-digital conversion module may be as follows: controlling the digital-to-analog conversion module to execute a first working mode corresponding to the first signal; and outputting a first digital signal corresponding to the first signal based on the logic module. When the first control signal is at the second level, the control method for the analog-to-digital conversion module may be as follows: controlling the digital-to-analog conversion module to execute a second working mode corresponding to the second signal; and outputting a second digital signal corresponding to the second signal based on the logic module.

Optionally, the digital-to-analog conversion module may include a positive-side digital-to-analog conversion module and a negative-side digital-to-analog conversion module, the positive-side digital-to-analog conversion module is adapted to the second switch, and the negative-side digital-to-analog conversion module is adapted to the third switch. The second switch and the third switch can realize the switching of the working mode of the digital-to-analog conversion module.

The control method comprises the following steps: when the first control signal is at a first level, controlling the second switch and the third switch to adapt to a first working mode; and when the first control signal is at a second level, the second switch is controlled to adapt to a second working mode, and the third switch is controlled to connect a second preset voltage to the negative terminal digital-to-analog conversion module.

In one possible embodiment, when the first control signal is at the first level, each switch of the digital-to-analog conversion differential capacitor array may be controlled individually based on the successive approximation search logic, as shown in fig. 15 and 16 for the switch state during conversion. At the moment, the capacitor arrays at the positive end and the negative end of the digital-to-analog conversion differential capacitor array are simultaneously controlled by the successive approximation search logic module.

When the first control signal is at a second level, each switch of the positive end capacitor array of the digital-to-analog conversion differential capacitor array is controlled based on the successive approximation search logic module; and one end of each switch of the negative end capacitor array of the digital-analog conversion differential capacitor array receives a second preset voltage, and the other end of each switch is connected with the negative end capacitor. At this time, only the positive side capacitor array of the digital-to-analog conversion differential capacitor array is controlled by the successive approximation search logic module, and the negative side capacitor array is fixedly connected to the second preset voltage, that is, the positive side reference voltage VREFN, the negative side reference voltage VREFP or other fixed voltage values.

Optionally, the difference between the second preset voltage and the first preset voltage connected to the input preprocessing module is not greater than the difference threshold. Wherein the difference threshold may be equal to (VREFN + VREFP)/2. In a preferred embodiment, the second predetermined voltage is equal to the first predetermined voltage.

In another possible implementation, when the second preset voltage is not equal to the first preset voltage, the digital signal output by the ADC circuit may be processed based on the voltage difference value. Specifically, the second preset voltage may be subtracted from the first preset voltage to obtain a voltage difference; converting the voltage difference value into a difference code value based on the analog-to-digital conversion principle in the ADC circuit; and subtracting the difference code value from the digital signal code value output by the ADC circuit to obtain a final digital signal code value.

For example, when the ADC circuit processes a single-ended signal, if the first preset voltage is 0V and the second preset voltage is 1/2 × VREFP, the voltage difference may be obtained by using the following formula: the voltage difference is the second predetermined voltage — the first predetermined voltage is 1/2 × VREFP. The voltage difference value is converted into a difference code value by the following formula: the difference code value is voltage difference/VREFP 2N 2 (N-1). Calculating a final digital signal code value by using the following formula for the digital signal code value: the final digital signal code value-difference code value.

When the ADC circuit processes the differential signal, if the first preset voltage is 0V and the second preset voltage is 1/2 × VREFP, the voltage difference can be obtained by using the following formula: the voltage difference is the second predetermined voltage — the first predetermined voltage is 1/2 × VREFP. Converting the voltage difference value into a difference code value by adopting the following formula: the difference code value is voltage difference value/VREFP 2^ (N-1) ^ 2^ (N-2). Calculating a final digital signal code value by using the following formula for the digital signal code value: the final digital signal code value-difference code value.

Where N is the number of bits of the ADC circuit, the difference code value may be positive or negative. In addition, the processing of converting the difference code value may be processed in a circuit, or may be processed by software in the using process, which is not limited in this embodiment.

In a preferred embodiment, the mismatch code of step 1002 may be calculated by a logic module in the analog-to-digital conversion module, and the specific process is as follows: during calibration, the multiplexing logic module quantizes the error voltage of the digital-to-analog conversion module to obtain a mismatch code. As shown in fig. 9, in the stage of calibration error, the SAR ADC circuit may multiplex a successive approximation search logic module existing in the analog-to-digital conversion module, and the SAR logic control signal controls the calibration control module to calibrate the differential capacitor array, quantizes the offset of the digital-to-analog conversion differential capacitor array and the error voltage of capacitor mismatch, transmits the obtained mismatch code to the calibration algorithm module, and stores the mismatch code in the calibration algorithm module.

Optionally, the ADC circuit may further include a reset switch, and the reset switch may be configured to switch the bias voltage into the digital-to-analog conversion module.

In one possible implementation, as shown in fig. 13, 14, during sampling, reset switch SWCM1/2 may be closed, causing one plate of a capacitor in the digital-to-analog conversion differential capacitor array to be reset to bias voltage VCM. Further, as shown in fig. 15, 16, during the transition, the reset switch SWCM1/2 may be turned off.

The embodiment of the invention can obtain the following beneficial effects:

(1) through the first control signal, the ADC circuit can realize continuous calibration of two different working modes, and the ADC circuit does not need to be restarted to configure the different working modes.

(2) By the ADC circuit and the corresponding time sequence control, continuous switching can be realized on the basis of realizing continuous calibration of a differential mode and a single-ended mode.

(3) In the calibration error stage, the quantization error voltage is realized by multiplexing the logic module without additionally adding another logic module, so that the logic complexity of the calibration module is optimized, and the area of an ADC (analog-to-digital converter) circuit can be reduced.

The invention further provides a chip comprising the ADC circuit provided by the embodiment of the invention.

An exemplary embodiment of the present invention also provides an electronic device including: the ADC circuit provided by the embodiment of the invention; at least one processor; and a memory communicatively coupled to the at least one processor. The memory stores a computer program executable by the at least one processor, the computer program, when executed by the at least one processor, is for causing the electronic device to perform a method according to an embodiment of the invention.

Exemplary embodiments of the present invention also provide a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is operable to cause the computer to perform a method according to an embodiment of the present invention.

Referring to fig. 17, a block diagram of a structure of an electronic device 1700 that can be the present invention, which is an example of a hardware device that can be applied to aspects of the present invention, will now be described. Electronic devices are intended to represent various forms of digital electronic computer devices, such as data center servers, notebook computers, thin clients, laptop computers, desktop computers, workstations, personal digital assistants, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 17, the electronic apparatus 1700 includes a computing unit 1701 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM)1702 or a computer program loaded from a storage unit 1708 into a Random Access Memory (RAM) 1703. In the RAM 1703, various programs and data required for the operation of the device 1700 can also be stored. The computing unit 1701, the ROM 1702, and the RAM 1703 are connected to each other through a bus 1704. An input/output (I/O) interface 1705 is also connected to bus 1704.

Various components in the electronic device 1700 are connected to the I/O interface 1705, including: an input unit 1706, an output unit 1707, a storage unit 1708, and a communication unit 1709. The input unit 1706 may be any type of device capable of inputting information to the electronic device 1700, and the input unit 1706 may receive input numeric or character information and generate key signal inputs related to user settings and/or function control of the electronic device. Output unit 1707 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, a video/audio output terminal, a vibrator, and/or a printer. Storage unit 1704 may include, but is not limited to, a magnetic disk or optical disk. The communication unit 1709 allows the electronic device 1700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and/or a chipset, such as a bluetooth device, a WiFi device, a WiMax device, a cellular communication device, and/or the like.

The computing unit 1701 may be a variety of general purpose and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 1701 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and the like. The computing unit 1701 executes the various methods and processes described above. For example, in some embodiments, the control method of the ADC circuit may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the memory unit 1708. In some embodiments, part or all of the computer program may be loaded and/or installed onto electronic device 1700 via ROM 1702 and/or communications unit 1709. In some embodiments, the computational unit 1701 may be configured in any other suitable manner (e.g., by way of firmware) to perform a control method for the ADC circuit.

Program code for implementing the methods of the present invention may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

Claims

1. An analog-to-digital converter (ADC) circuit, the ADC circuit comprising at least: the analog-to-digital conversion module and the calibration module;

wherein the first control signal switches levels during sampling.

2. The ADC circuit of claim 1, wherein said calibration module comprises a calibration digital-to-analog conversion module, a calibration algorithm module, a calibration control module;

3. The ADC circuit of claim 2, wherein the calibration algorithm module is further configured to store the mismatch code.

4. The ADC circuit of claim 2, wherein the calibration control module is further configured to set a calibration code to a preset intermediate calibration code during the sampling, and to transmit the intermediate calibration code to the calibration DAC module.

5. The ADC circuit of claim 1 further comprising an input pre-processing module, an output of said input pre-processing module being connected to an input of said analog-to-digital conversion module;

wherein the second control signal switches level during the transition.

6. The ADC circuit of claim 5, wherein the analog-to-digital conversion module comprises a digital-to-analog conversion module, a comparison module and a logic module, wherein the digital-to-analog conversion module is used for sample holding and quantization;

7. The ADC circuit of claim 6, wherein the logic module is further configured to quantize an error voltage of the DAC module during calibration to obtain the mismatch code.

8. A method for controlling an ADC circuit, the ADC circuit comprising at least: the analog-to-digital conversion module and the calibration module, wherein the method comprises the following steps:

wherein the first control signal switches levels during sampling.

9. The ADC circuit control method according to claim 8, wherein said calibration module comprises a calibration digital-to-analog conversion module, a calibration algorithm module, a calibration control module;

10. The method of controlling an ADC circuit according to claim 8, the method further comprising:

the mismatch code is stored based on the calibration algorithm module.

11. The method of controlling an ADC circuit according to claim 8, the method further comprising:

12. The ADC circuit of claim 8, further comprising an input pre-processing module, the method further comprising:

receiving an input signal;

wherein the second control signal switches level during the transition.

13. The control method of the ADC circuit of claim 12, wherein the analog-to-digital conversion module comprises a digital-to-analog conversion module, a comparison module and a logic module, wherein the digital-to-analog conversion module is used for sample holding and quantization;

14. The method of controlling an ADC circuit according to claim 13, the method further comprising:

15. A chip comprising an ADC circuit as claimed in any one of claims 1 to 7.

16. An electronic device, comprising:

the ADC circuit of any one of claims 1-7;

a processor; and

a memory for storing a program, wherein the program is stored in the memory,

wherein the program comprises instructions which, when executed by the processor, cause the processor to carry out the method according to any one of claims 8-14.

17. A non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 8-14.