CN115833835A - Successive approximation type analog-to-digital converter, oversampling method and device - Google Patents

Abstract

The embodiment of the disclosure provides a successive approximation type analog-to-digital converter, an oversampling method and a device. By the processing scheme of the disclosure, the same analog signal is utilized during oversampling, the change is not large, and the sampling error is not more than 2 ^M Based on the conventional SAR ADC converter, an oversampling error range signal, an oversampling enabling signal, a last group of result registers and a control logic circuit supporting oversampling are added. When the oversampling enable is effective, the high-order result of the last result register is adopted as much as possible, and the residual result bits are determined by successive approximation from a certain middle bit to a low bit. Under the condition of not increasing hardware resources remarkably, the conversion efficiency of the SAR ADC to continuous and repeated sampling conversion of the analog signal can be effectively improved, and the over-sampling time of the analog signal is shortened.

Description

Successive approximation type analog-to-digital converter, oversampling method and device

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a successive approximation type analog-to-digital converter, an oversampling method and an oversampling device.

Background

A successive approximation Analog-to-digital converter (SAR ADC) is a common Analog-to-digital converter used to sample an Analog signal and convert it into a digital signal.

The SAR ADC mainly comprises five parts, namely a control circuit, a sample-and-hold circuit, an analog comparator, a SAR successive approximation register and a Digital-to-analog converter (DAC). After receiving a sampling enabling signal input from the outside, the control circuit samples and holds an analog signal as an input voltage Vin in a sampling stage, and then gradually changes a digital signal of the DAC from a high position to a low position to enable the DAC to output an analog output voltage Vo; the analog comparator compares Vin and Vo successively to enable Vo to approach Vin finally to obtain a final digital signal of the DAC, and the final digital signal is used as a final digital result after analog-to-digital conversion of the SAR ADC. When in conversion, default input digital signals of the DAC are all zero; firstly, setting the highest bit of the input digital signal of the DAC as '1', comparing Vin with Vo, and if Vin is not higher than Vo, changing the bit of the input digital signal of the DAC to '0'; and then, determining a bit of input digital signal of the DAC from high bit to low bit in each period by adopting a similar method until all the bit of the digital signal is judged, and finishing conversion, wherein the final input digital signal of the DAC is the digital signal conversion result of the SAR ADC.

In order to reduce the sampling error of the analog signal, the analog signal needs to be oversampled many times, that is, the analog signal is subjected to continuous sampling conversion for many times, and the sampling conversion results for many times are filtered to obtain a final sampling result. The existing SAR ADC needs to pass through a sampling stage and a conversion stage every time sampling conversion is carried out; in the conversion stage, the conversion of the digital result is completed by taking N clock cycles from high bit to low bit; if X oversampling are continued, the cumulative transition time of oversampling will take X N clock cycles. This results in a low conversion efficiency of the oversampling. In order to improve the sampling conversion efficiency of the SAR ADC, the SAR ADC generally adopts a pipeline manner. But the hardware resources required for a pipelined SAR ADC will increase as the number of pipeline stages increases.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a successive approximation type analog-to-digital converter, an oversampling method and an apparatus, which at least partially solve the problems in the prior art.

In a first aspect, an embodiment of the present disclosure provides a successive approximation type analog-to-digital converter oversampling method, including:

if an oversampling enabling signal is received, acquiring an oversampling error index M;

obtaining the conversion data P stored in the last result register _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data as D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 Convert data for the most significant bit, D ₀ Representing the least significant bit converted data;

from said conversion data P in order from lower to higher order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0;

let the approximation bit parameter K = L;

set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

From D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ ；

Will D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:

if from the conversion data P _N-1 P _N-2 P _N-3 …P ₁ P ₀ In-search distance error index bit data P _M Most recent bit data P _L Bit when =0;

enabling the approximation bit parameter K = N-1;

from D _K At the beginning, D is determined by adopting a successive approximation method according to the sequence from high order to low order _K D _K-1 D _K-2 …D ₁ D ₀ 。

According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:

if L = N-1, making the approximation bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ 。

According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:

if the input voltage V is _in Greater than the output voltage V _o If so, the approximation bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ 。

According to a specific implementation of the embodiments of the present disclosure, the slave D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ The method comprises the following steps:

let D _K ＝1；

If the input voltage V is _in Not greater than output voltage V _o Then order D _K ＝0；

Let K = K-1, continue to judge the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V is _in Greater than the output voltage V _o If K = K-1, the determination of the input voltage V is continued _in And an output voltage V _o Until K = 0.

In a second aspect, an embodiment of the present disclosure provides a successive approximation type analog-to-digital converter oversampling apparatus, including:

the enabling module is used for acquiring an oversampling error index M if an oversampling enabling signal is received;

an obtaining module for obtaining the conversion data P stored in the last group of result registers _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit converted data; setting the conversion data to D _N-1 D _{N- 2} D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

a search module for converting the data P from the lower order to the upper order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0;

a first setting module, configured to enable an approximation bit parameter K = L;

a second setting module for setting D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

Approximation module for deriving D from _K Initially, D is determined by successive approximation in order from high to low _K D _{K- 1} D _K-2 …D ₁ D ₀ ；

A memory module for storing D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

According to a specific implementation manner of the embodiment of the present disclosure, the approximation module is specifically configured to:

let D _K ＝1；

If the input voltage V is _in Not greater than output voltage V _o Then order D _K ＝0；

Let K = K-1, continue to judge the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V is _in Greater than the output voltage V _o If K = K-1, the determination of the input voltage V is continued _in And an output voltage V _o Until K = 0.

In a third aspect, an embodiment of the present disclosure further provides a successive approximation type analog-to-digital converter, including:

a sample-and-hold unit for receiving an input voltage V _in ；

DAC digital-to-analog converter for converting a reference voltage V _ref Is converted into an output voltage V _o ；

A comparator for comparing the input voltage V _in And an output voltage V _o Sending the comparison result to a successive approximation type analog-to-digital converter oversampling device;

the successive approximation type analog-to-digital converter oversampling device is used for realizing the successive approximation type analog-to-digital converter oversampling method.

According to a specific implementation manner of the embodiment of the present disclosure, the successive approximation type analog-to-digital converter oversampling device includes:

a last set of result registers for storing last conversion data P _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

a control logic circuit for converting the data P in order from lower bits to higher bits _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0; let the approximation bit parameter K = L; set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

SAR successive approximation register for slave D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ ；

The last set of result registers is also used for storing D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data as output is stored.

In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, where the electronic device includes:

at least one processor; and the number of the first and second groups,

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of successive approximation analog to digital converter oversampling in any of the implementations of the first aspect or the first aspect.

In a fourth aspect, the disclosed embodiments also provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a successive approximation type analog-to-digital converter oversampling method in the foregoing first aspect or any implementation manner of the first aspect.

In a fifth aspect, the disclosed embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform a successive approximation type analog-to-digital converter oversampling method in the foregoing first aspect or any implementation manner of the first aspect.

The oversampling scheme of the successive approximation type analog-to-digital converter in the embodiment of the disclosure includes acquiring an oversampling error index M if an oversampling enable signal is received; obtaining the conversion data P stored in the last result register _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data; from said conversion data P in order from lower to higher order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the distance error exponent digital data P _M-1 Most recent bit data P _L Bit parameter L when =0; let the approximation bit parameter K = L; set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _{N- 1} P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ =0; from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ (ii) a Will D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register. By the scheme, under the condition that hardware resources are not remarkably increased, the conversion efficiency of the SAR ADC to continuous and repeated sampling conversion of the analog signal can be effectively improved, and the over-sampling time of the analog signal is shortened.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a successive approximation type analog-to-digital converter according to an embodiment of the disclosure;

fig. 2 is a schematic flowchart of a first successive approximation type analog-to-digital converter oversampling method according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a second successive approximation type analog-to-digital converter oversampling method according to the embodiment of the present disclosure;

fig. 4 is a schematic flowchart of a third successive approximation type analog-to-digital converter oversampling method according to the embodiment of the present disclosure;

fig. 5 is a schematic flowchart of a fourth successive approximation type analog-to-digital converter oversampling method according to the embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an oversampling device of a successive approximation type analog-to-digital converter according to an embodiment of the disclosure.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

Fig. 1 is a schematic structural diagram of a successive approximation type analog-to-digital converter according to an embodiment of the disclosure, as shown in fig. 1, the SAR ADC includes: a sample holder 110, a comparator 120, a DAC digital-to-analog converter 130, and a successive approximation analog-to-digital converter oversampling unit 140.

The sample-and-hold device 110 receives an input voltage V _in Wherein V is _in For analog voltage, DAC 130 converts the reference voltage V _ref Is converted into an output voltage V _o Wherein the reference voltage V _ref Is a digital voltage, outputting a voltage V _o For analog voltages, the comparator 120 compares the input voltage V _in And an output voltage V _o And sends the comparison result to successive approximation type analog-to-digital converter oversampling unit 140, successive approximation type analog-to-digital converter oversampling unit 140 includes: a last set of result registers 141, a control logic circuit 142, and a SAR successive approximation register 143. The function of the successive approximation type adc oversampling unit 140 is described in detail below.

Fig. 2 is a schematic flow chart of a first successive approximation type analog-to-digital converter oversampling method provided in the embodiment of the present disclosure, which is applied to the successive approximation type analog-to-digital converter oversampling device 140, as shown in fig. 2, the method includes:

step S21, if an oversampling enabling signal is received, acquiring an oversampling error index M;

in particular, in a successive approximation analog-to-digital converter oversampling system, an oversampling error range signal 2 is included ^M An oversampling enable signal 3a, a last group of result registers 141, and a control logic circuit 142 and SAR successive approximation register 143 supporting oversampling. Over-sampling error range signal definition sampling error not exceeding 2 ^M . The oversampling enable signal 3a is an input digital signal, and the oversampling enable signal 3a maintains an inactive level or an active level during one sampling conversion of the analog signal: when the over-sampling enable signal 3a is valid, the analog signal of the current sampling conversion and the analog signal of the previous sampling conversion are the same signal source and are one sampling conversion in multiple continuous sampling of the analog signal together with the previous sampling conversion; when the oversampling enable signal 3a is inactive, it indicates that the analog signal of the current sampling conversion and the analog signal of the previous sampling conversion are not the same signal source, or that the current sampling conversion is not the oversampling of the previous sampling conversion, and is a new sampling conversion. The last set of result registers 141 is used to record the register of the last converted digital result. When the oversampling enable signal 3a received by the control logic circuit 142 is asserted, the control logic circuit 142 outputs the oversampling error range signal 2 ^M To determine an oversampling error index M.

Step S22, obtaining the conversion data P stored in the last group of result registers _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data as D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

specifically, the control logic circuit 142 obtains the conversion data P after the last system conversion from the last result register 141 _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Indicates the least significant bit of the conversion data, and the last result register 141 sets the current conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

fig. 3 is a schematic flow chart of a second successive approximation type adc oversampling method according to the embodiment of the present disclosure, as shown in fig. 3, 12-bit conversion data P is stored in the upper set of result registers 141 _N-1 P _N-2 P _N-3 …P ₁ P ₀ =101110111100, and oversampling error index M =2.

Step S23, converting the data P in the order from the lower order to the upper order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0;

specifically, control logic 142 converts data P from _N-1 P _N-2 P _N-3 …P ₁ P ₀ In the order from low order to high order, find out the distance P _M-1 The most recent bit having a one-bit value of "0" is P _L And finds the bit parameter L. As shown in FIG. 3, P _M-1 I.e. P ₁ =0, from lower to upper order, from P ₁ Bit of the nearest 0 of =0 is P _L ＝P ₆ At this time, L =6.

Step S24, enabling an approximation bit parameter K = L;

step S25, setting D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

Step S26, slave D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ ；

Step S27, adding D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

Specifically, let approach bit parameter K = L, set D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ =0, from D _K Initially, D of the digital signal input to the DAC is estimated by successive approximation in order from high to low bits _L To D ₀ . As shown in fig. 3, K =6, set D _N-1 D _N-2 D _N-3 …D _K+1 =10111 from D ₆ At the beginning, D of the digital signal input of the DAC is deduced by adopting a successive approximation method according to the sequence from high order to low order ₆ To D ₀ 。

Specifically, fig. 4 is a schematic flow chart of a third successive approximation type analog-to-digital converter oversampling method provided in the embodiment of the present disclosure, as shown in fig. 4:

first order D _K ＝1；

Determine the input voltage V _in Whether or not it is not greater than the output voltage V _o If yes, let D _K =0, otherwise D _K ＝1；

Judging whether K is 0, if not, making K = K-1, and continuously judging the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V is _in Greater than the output voltage V _o If K = K-1, the determination of the input voltage V is continued _in And an output voltage V _o Until K = 0.

Finally, data D will be converted _K-1 D _K-2 D _K-3 …D ₁ D ₀ As output analog-to-digital converted data.

Completion D _N-1 D _N-2 D _N-3 …D ₁ D ₀ After all bits are inferred, the final digital signal input to the DAC is output as the converted digital result of the SAR ADC, and the result is recorded in the last set of result registers 141.

In practical application, if the data P is converted _N-1 P _N-2 P _N-3 …P ₁ P ₀ In-search distance error index bit data P _M Most recent bit data P _L Bit when =0;

let the approximation bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ 。

I.e. if the data P is converted _N-1 P _N-2 P _N-3 …P ₁ P ₀ In-search of the distance error index bit data P _M-1 Most recent bit data P _L The bits when =0, the high order continuous turnover may be caused by errors, the high order result of the last group of result registers cannot be used as the initial value of the successive comparison, the DAC needs to determine D from the high order to the low order by using the successive approximation method _N-1 D _N-2 …D ₁ D ₀ 。

In practical application, if L = N-1, let approach bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ . That is, if L = N-1, the error may cause a highThe bits are continuously turned over, the high-order result of the last group of result registers cannot be used as the initial value of successive comparison, the DAC needs to determine D from the high-order to the low-order by adopting a successive approximation method _N-1 D _N-2 …D ₁ D ₀ 。

In practical application, if the input voltage V is _in Greater than the output voltage V _o If so, the approximation bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ 。

I.e. if V _in Greater than V _o It may mean that the analog signal suddenly becomes larger, P _N-1 P _N-2 P _N-3 …P _K+1 If the D can not be used as the high-order initial value of successive comparison, D needs to be determined by adopting a successive approximation method from the high order to the low order _N-1 D _N-2 …D ₁ D ₀ 。

In addition, if the oversampling enable signal 3a is invalid, indicating that the sampling conversion does not satisfy the oversampling condition, the DAC needs to select the highest bit D _N-1 And deducing from high to low by adopting a successive approximation method.

The method can be used for solving the problems that in the prior art, the sampling rate of the SAR ADC analog signal is low, and the sampling rate of the SAR ADC analog signal is high.

The successive approximation type analog-to-digital converter oversampling method provided by the embodiment of the disclosure utilizes that the same analog signal generally has small change and the sampling error does not exceed 2 during the oversampling period ^M Based on the conventional SAR ADC converter, an oversampling error range signal, an oversampling enabling signal, a last group of result registers and a control logic circuit supporting oversampling are added. When the over-sampling is effective, the high order of the last result register is used as much as possibleAs a result, the remaining result bits are determined by successive approximation starting from the middle bit toward the lower bits. During the oversampling conversion, because successive approximation is not performed from the highest position to the lower position every time, the times of successive approximation are reduced, the conversion efficiency is improved, and the conversion efficiency of the SAR ADC for oversampling the analog signal can be improved.

Fig. 5 is a schematic flowchart of a fourth successive approximation type analog-to-digital converter oversampling method according to an embodiment of the present disclosure, as shown in fig. 5, the method includes:

1) Inputting a valid oversampling enable signal, proving that the sampled signal and the last sampled signal come from the same signal source and are one sampling conversion of multiple continuous samples of the analog signal together with the previous sampling conversion, and taking out the result P stored in the last group of result registers _N-1 P _N-2 P _N-3 …P ₁ P ₀ ；

2) The flow (1) in FIG. 5 is executed to query the upper level for the distance P _M-1 Most recent P _L =0 bits, then L =6;

3) The flow of (2) in FIG. 5 is executed, P in the last set of result registers _N-1 P _N-2 P _N-3 …P _L+1 The value of the bit being assigned to D _{N- 1} D _N-2 D _N-3 …D _L+1 ,D _L ＝1，D _L-1 …D ₀ The assignment is 0,k = l: if V _in Not more than V _o Then D is _L K =0, k = k-1, the procedure of (3) is performed; if V _in Greater than V _o It may mean that the analog signal suddenly becomes larger, P _N-1 P _N-2 P _N-3 …P _L+1 If the value cannot be used as the initial high-order value for successive comparison, the procedure of (3) needs to be executed, and successive comparison is started from the highest-order bit.

4) The flow of (3) in FIG. 5 is executed to determine D by successive comparisons _N-1 D _N-2 D _N-3 …D ₀ All of the bits of (a).

5)D _N-1 D _N-2 D _N-3 …D ₀ After all the bits of (1) are successively compared, D _N-1 D _N-2 D _N-3 …D ₀ As SAR ADCsIs output and the result is recorded in the last result register (update P) _N-1 P _N-2 P _N-3 …P ₀ )。

The flow of (3) in fig. 5, i.e. K = N-1, infers the input of all bits of the DAC from the high order to the low order successive approximation, and is applicable to the following cases:

1) The over-sampling enabling signal is invalid, which indicates that the sampling conversion does not meet the over-sampling condition, and the DAC needs to go from the highest bit D _N-1 Starting from high to low, adopting a successive approximation method to deduce;

2) At P _N-1 P _N-2 P _N-3 …P _M-1 In the middle, P cannot be found _L Equal to 0, or L = N-1, the adoption of an error may cause the high order bits to flip consecutively, the high order result of the last result register cannot be adopted as the initial value for successive comparisons, and the DAC needs to start from the highest order bit D _N-1 Starting from high to low, adopting a successive approximation method to deduce;

3) Execute the flow of (2) in FIG. 5, P in the last result register _N-1 P _N-2 P _N-3 …P _L+1 The value of a bit being given to D _{N- 1} D _N-2 D _N-3 …D _L+1 ,D _L ＝1，D _L-1 …D ₀ Assigned a value of 0 if V _in Greater than V _o It may mean that the analog signal suddenly becomes larger, P _N-1 P _N-2 P _N-3 …P _L+1 If the value cannot be used as the initial high-order value for successive comparison, the procedure of (3) needs to be executed, and successive comparison is started from the highest-order bit.

The flow in (3) in fig. 5 includes:

let K = N-1,D _K ＝1，D _N-1 D _N-2 D _N-3 …D ₀ ＝0；

Determining the input voltage V _in Whether or not it is not greater than the output voltage V _o If yes, let D _K =0, otherwise D _K ＝1；

Judging whether K is 0, if not, making K = K-1, and continuously judging the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V is _in Greater than the output voltage V _o If K = K-1, the determination of the input voltage V is continued _in And an output voltage V _o Until K = 0.

Finally, data D will be converted _N-1 D _N-2 D _N-3 …D ₁ D ₀ As output analog-to-digital converted data.

The successive approximation type analog-to-digital converter (SAR ADC) oversampling method provided by the embodiment of the disclosure can effectively improve the conversion efficiency of the SAR ADC to the continuous and multiple sampling conversion of the analog signal without increasing hardware resources remarkably, and shorten the oversampling time of the analog signal.

Based on the same inventive concept, an embodiment of the present disclosure further provides an successive approximation type adc oversampling device, and fig. 6 is a schematic structural diagram of the successive approximation type adc oversampling device provided in the embodiment of the present disclosure, and as shown in fig. 6, the device includes: an enabling module 61, an obtaining module 62, a searching module 63, a first setting module 64, a second setting module 65, an approximating module 66 and a storing module 67, wherein:

the enabling module 61 is configured to obtain an oversampling error index M if an oversampling enabling signal is received; the obtaining module 62 is used for obtaining the conversion data P stored in the last group of result registers _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit converted data; the lookup module 63 is used for converting the data P from the lower bits to the upper bits in sequence _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the distance error exponent digital data P _M-1 Most recent bit data P _L Bit parameter L when =0; the first setting module 64 is configured to make the approximation bit parameter K = L; the second setting module 65 is for setting D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ =0; approximation module 66 is used to derive D from _K At the beginning, D is determined by adopting a successive approximation method according to the sequence from high order to low order _K D _K-1 D _K-2 …D ₁ D ₀ (ii) a Memory module 67 for storing D _{N- 1} D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

As in the successive approximation type analog-to-digital converter oversampling apparatus described above, optionally, the approximation module 66 is specifically configured to:

let D _K ＝1；

If the input voltage V is _in Not greater than output voltage V _o Then order D _K ＝0；

Let K = K-1, continue to judge the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V is _in Greater than the output voltage V _o If K = K-1, the determination of the input voltage V is continued _in And an output voltage V _o Until K = 0.

The successive approximation type analog-to-digital converter oversampling device provided in the embodiment of the present disclosure is used to implement the successive approximation type analog-to-digital converter oversampling method, which is described in detail in the embodiment of the method above, and is not described here again.

An embodiment of the present disclosure discloses an electronic device, the device including: a processor (processor), a memory (memory), and a bus;

the processor and the memory complete mutual communication through the bus;

the processor is used for calling the program instructions in the memory to execute the method provided by the above method embodiments, for example, the method includes: if an oversampling enabling signal is received, acquiring an oversampling error index M; obtaining the conversion data P stored in the last result register _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit converted data; from said conversion data P in order from lower to higher order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0; let the approximation bit parameter K = L; set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ =0; from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ (ii) a Will D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

The disclosed embodiments disclose a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions that, when executed by a computer, enable the computer to perform the methods provided by the above-described method embodiments, for example, comprising: if an oversampling enabling signal is received, acquiring an oversampling error index M; obtaining the conversion data P stored in the last result register _N-1 P _{N- 2} P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data(ii) a From said conversion data P in order from lower to higher order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0; let the approximation bit parameter K = L; set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ =0; from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ (ii) a Will D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

Embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer instructions that cause a computer to perform the methods provided by the above method embodiments, for example, including: if an oversampling enabling signal is received, acquiring an oversampling error index M; obtaining the conversion data P stored in the last result register _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data; from said conversion data P in order from low to high order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0; let the approximation bit parameter K = L; set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ =0; from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ (ii) a Will D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. An oversampling method for a successive approximation type analog-to-digital converter, comprising:

if an oversampling enabling signal is received, acquiring an oversampling error index M;

obtaining the conversion data P stored in the last result register _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data;

setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

from said conversion data P in order from lower to higher order _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0;

let the approximation bit parameter K = L;

set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

From D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ ；

Will D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

2. The successive approximation analog-to-digital converter oversampling method of claim 1, further comprising:

if from the conversion data P _N-1 P _N-2 P _N-3 …P ₁ P ₀ In-search distance error index bit data P _M Most recent bit data P _L Bit when =0;

let the approximation bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ 。

3. The successive approximation analog-to-digital converter oversampling method of claim 1, further comprising:

if L = N-1, let approach bit parameter K = N-1;

from D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ 。

4. The successive approximation analog-to-digital converter oversampling method of claim 1, further comprising:

if the input voltage V is _in Greater than the output voltage V _o If so, the approximation bit parameter K = N-1;

from D _K At the beginning, D is determined by adopting a successive approximation method according to the sequence from high order to low order _K D _K-1 D _K-2 …D ₁ D ₀ 。

5. The successive approximation analog-to-digital converter oversampling method according to any one of claims 1-4, wherein said slave D is _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ The method comprises the following steps:

let D _K ＝1；

If the input voltage V is _in Not greater than output voltage V _o Then order D _K ＝0；

Let K = K-1, continue to judge the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V _in Greater than the output voltage V _o If K = K-1, the determination of the input voltage V is continued _in And an output voltage V _o Until K = 0.

6. An oversampling apparatus for a successive approximation analog-to-digital converter, comprising:

the enabling module is used for acquiring an oversampling error index M if an oversampling enabling signal is received;

an obtaining module for obtaining the conversion data P stored in the last group of result registers _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

a search module for converting the data P in the order from the lower bits to the upper bits _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 More recentBit data P _L Bit parameter L when =0;

a first setting module, configured to enable an approximation bit parameter K = L;

a second setting module for setting D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

Approximation module for deriving D from _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ ；

A memory module for storing D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data is output and stored in a result register.

7. The successive approximation analog-to-digital converter oversampling apparatus of claim 6, wherein the approximation module is specifically configured to:

let D _K ＝1；

If the input voltage V is _in Not greater than output voltage V _o Then order D _K ＝0；

Let K = K-1, continue to judge the input voltage V _in And an output voltage V _o Until K =0;

if the input voltage V is _in Greater than the output voltage V _o If K = K-1, the judgment of the input voltage V is continued _in And an output voltage V _o Until K = 0.

8. A successive approximation analog-to-digital converter, comprising:

a sample-and-hold unit for receiving an input voltage V _in ；

DAC digital-to-analog converter for converting a reference voltage V _ref Is converted into an output voltage V _o ；

A comparator for comparing the inputVoltage V _in And an output voltage V _o Sending the comparison result to a successive approximation type analog-to-digital converter oversampling device;

the successive approximation type analog-to-digital converter oversampling device is used for realizing the successive approximation type analog-to-digital converter oversampling method according to any one of claims 1 to 5.

9. A successive approximation analog-to-digital converter, wherein the oversampling unit comprises:

a last set of result registers for storing last conversion data P _N-1 P _N-2 P _N-3 …P ₁ P ₀ Where N is the number of sampling bits, P _N-1 For conversion of the most significant bits, P ₀ Representing the least significant bit of the converted data; setting the conversion data to D _N-1 D _N-2 D _N-3 …D ₁ D ₀ Where N is the number of sampling bits, D _N-1 For conversion of the most significant bits, D ₀ Representing the least significant bit of the converted data;

a control logic circuit for converting the data P in order from lower bits to higher bits _N-1 P _N-2 P _N-3 …P ₁ P ₀ Finding the range error exponent data P _M-1 Most recent bit data P _L Bit parameter L when =0; let the approximation bit parameter K = L; set up D _N-1 D _N-2 D _N-3 …D _K+1 ＝P _N-1 P _N-2 P _N-3 …P _K+1 ，D _K ＝1,D _K-1 …D ₁ D ₀ ＝0；

SAR successive approximation register for slave D _K Initially, D is determined by successive approximation in order from high to low _K D _K-1 D _K-2 …D ₁ D ₀ ；

The last set of result registers is also used for storing D _N-1 D _N-2 D _N-3 …D ₁ D ₀ The analog-to-digital converted data as output is stored.

10. A non-transitory computer-readable storage medium storing computer instructions which, when executed by one or more processors, cause the one or more processors to perform the successive approximation analog to digital converter oversampling method of any of claims 1-5.

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