CN112187265A - Mixed type analog-digital converter and signal transceiver for electric power special communication network - Google Patents
Mixed type analog-digital converter and signal transceiver for electric power special communication network Download PDFInfo
- Publication number
- CN112187265A CN112187265A CN202011024305.8A CN202011024305A CN112187265A CN 112187265 A CN112187265 A CN 112187265A CN 202011024305 A CN202011024305 A CN 202011024305A CN 112187265 A CN112187265 A CN 112187265A
- Authority
- CN
- China
- Prior art keywords
- analog
- digital converter
- capacitor array
- stage
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 title claims abstract description 35
- 239000003990 capacitor Substances 0.000 claims abstract description 134
- 238000006243 chemical reaction Methods 0.000 claims abstract description 54
- 238000013139 quantization Methods 0.000 claims abstract description 23
- 238000005070 sampling Methods 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 9
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 3
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention relates to the field of integrated circuits, and provides a hybrid analog-to-digital converter for a power private communication network, which comprises: the system comprises a first-stage full parallel analog-to-digital converter, a second-stage successive approximation analog-to-digital converter and a decoder; the first-stage fully-parallel analog-to-digital converter comprises a 4-bit fully-parallel analog-to-digital converter, a first capacitor array and a digital coding circuit, and is used for carrying out quantization conversion on high bits of an analog input signal to obtain a 4-bit digital output code; the second-stage successive approximation analog-to-digital converter comprises a second capacitor array, a comparator and an 8-bit successive approximation analog-to-digital conversion logic circuit, and is used for carrying out quantization conversion on the low bits of the analog input signals to obtain 8-bit digital output codes; the decoder is used for translating the converted 4-bit digital output code and 8-bit digital output code into a 12-bit digital signal. The invention adopts a two-stage mixed structure to realize the 12-bit analog-to-digital conversion function with low power consumption and high speed, and can meet the requirements of the electric power wireless private network.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a hybrid analog-to-digital converter for a power private communication network and a signal transceiving device for the power private communication network.
Background
At present, a domestic power private communication network (TD-LTE power wireless private network) mainly adopts two frequency bands of 230MHz and 1.8GHz for networking. The total bandwidth of the power dedicated spectrum resource of the 230MHz frequency band is 1MHz, and is dispersed at 40 frequency points, and the bandwidth of each discrete frequency point is 25 kHz. Because the bandwidth of the 230MHz frequency band is narrow, the signal transceiver of the electric power private communication network needs to have a linear modulation function, and the signal transceiver needs to use a 12-bit Analog-to-Digital Converter (ADC), and the ADC needs to have low power consumption and high speed.
The existing analog-to-digital converters are of various types, for example: sigma-delta ADC, Pipeline ADC, Flash ADC (full parallel analog-to-digital converter, Flash analog-to-digital converter), SAR ADC (Successive Approximation ADC). Wherein, the precision of the sigma-delta ADC is high, but the speed is low; the static power consumption of the Pipeline ADC is high; the Flash ADC has high resolution, but high power consumption; the SAR ADC is widely applied to wireless communication, has a simple structure, a small area and low power consumption, but has a conversion rate in direct proportion to the power consumption, and has high power consumption at the same time of high rate. The existing various analog-to-digital converters cannot meet the requirements of a signal transceiver of a 230MHz frequency band of a power wireless private network on high speed and low power consumption of data conversion.
Disclosure of Invention
The invention aims to provide a hybrid analog-to-digital converter for a power private communication network, so as to meet the requirements of a 230MHz frequency band of a power wireless private network on high speed and low power consumption of data conversion.
In order to achieve the above object, an aspect of the present invention provides a hybrid analog-to-digital converter for a power private communication network, including: the system comprises a first-stage full parallel analog-to-digital converter, a second-stage successive approximation analog-to-digital converter and a decoder; the first-stage fully-parallel analog-to-digital converter comprises a 4-bit fully-parallel analog-to-digital converter, a first capacitor array and a digital coding circuit, and is used for carrying out quantization conversion on high bits of an analog input signal to obtain a 4-bit digital output code; the second-stage successive approximation analog-to-digital converter comprises a second capacitor array, a comparator and an 8-bit successive approximation analog-to-digital conversion logic circuit, and is used for carrying out quantization conversion on the low bits of the analog input signal to obtain an 8-bit digital output code; the decoder is used for translating the 4-bit digital output code quantized and converted by the full parallel analog-to-digital converter and the 8-bit digital output code quantized and converted by the successive approximation analog-to-digital converter into a 12-bit digital signal and outputting the digital signal.
Further, the second capacitive array includes: the capacitor array of the second top plate is connected with the differential normal-phase analog input voltage, and the capacitor array of the second bottom plate is connected with the differential reverse-phase analog input voltage; the second top plate capacitor array and the second bottom plate capacitor array both comprise two second capacitors connected in parallel and having the same capacity and four third capacitors connected in parallel and having the same capacity, and the capacity of the second capacitors is twice that of the third capacitors.
Furthermore, one of the two second capacitors is connected with a reference voltage, and the other second capacitor is connected with a ground signal; two third capacitors of the four third capacitors are connected with reference voltage, and the other two third capacitors are connected with a grounding signal.
Further, the first capacitive array includes: the capacitor array comprises a first top plate capacitor array and a first bottom plate capacitor array, wherein the first top plate capacitor array and the first bottom plate capacitor array both comprise a plurality of first capacitors connected in parallel.
Further, still include: a third capacitor array in signal connection with the decoder; the third capacitor array comprises a third top plate capacitor array and a third bottom plate capacitor array, and the third top plate capacitor array and the third bottom plate capacitor array are both connected with the reference voltage and the grounding signal.
Further, the comparator of the second-stage successive approximation analog-to-digital converter is a dynamic comparator; the dynamic comparator comprises a first-stage amplifier and a second-stage latch, wherein the first-stage amplifier is used for pre-amplifying an input signal, and the second-stage latch is used for comparing and latching a pre-amplified result of the first-stage amplifier.
Further, the second-stage successive approximation analog-to-digital converter adopts a gated ring oscillator circuit to generate a clock frequency for triggering the dynamic comparator.
Further, when a sampling clock signal of the hybrid analog-to-digital converter is set to a high level, the first-stage fully parallel analog-to-digital converter and the second-stage successive approximation analog-to-digital converter synchronously sample an analog input signal, and the sampled signal is stored in the first top plate capacitor array and the second top plate capacitor array in the form of electric charge;
when the first-stage sampling is finished, the sampling clock signal is changed into low level, the clock signal of the full-parallel analog-to-digital converter is set to high level, and at the moment, the full-parallel analog-to-digital converter performs coarse quantization processing on the voltage stored on the first top plate capacitor array;
after the coarse quantization processing of the first-stage fully parallel analog-to-digital converter is completed, the clock signal of the fully parallel analog-to-digital converter is set at a low level, the clock signal of the second-stage successive approximation analog-to-digital converter is set at a high level, and at the moment, the second-stage successive approximation analog-to-digital converter performs fine quantization processing on the voltage stored on the second top plate capacitor array.
Further, the fully parallel analog-to-digital converter is connected to the analog input signal through a bootstrap switch.
In another aspect, the present invention provides a signal transceiver for a power private communication network, including the hybrid analog-to-digital converter for a power private communication network.
The embodiment of the invention adopts a mode of combining a full parallel analog-to-digital converter and a successive approximation analog-to-digital converter to form a hybrid analog-to-digital converter for a power special communication network. The mixed analog-digital converter adopts a first-stage fully-parallel analog-digital converter 4-bit Flash ADC to realize coarse conversion (coarse quantization processing) on an input signal, then utilizes a second-stage successive approximation analog-digital converter 8-bit SAR ADC to realize fine conversion (fine quantization processing) on the input signal, combines the advantages of the Flash ADC (high resolution and conversion rate) and the SAR ADC (small area and low power consumption), and realizes the analog-digital conversion function with low power consumption and high rate. The hybrid analog-digital converter adopts a two-stage hybrid structure to realize the 12-bit analog-digital conversion function, is applied to a wireless signal transceiver, and can meet the requirements of 230MHz frequency band of a power wireless private network on high speed and low power consumption of data conversion.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a block diagram of a hybrid analog-to-digital converter for a power private communication network according to an embodiment of the present invention;
FIG. 2 is a diagram of connections of a capacitor array before comparison in a second-stage successive approximation analog-to-digital converter SAR ADC according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a dynamic comparator according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a gated ring oscillator circuit of a hybrid analog-to-digital converter for a power private communication network according to an embodiment of the present invention;
fig. 5 is a conversion timing diagram of a hybrid analog-to-digital converter for a power private communication network according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a block diagram of a hybrid analog-to-digital converter for a power private communication network according to an embodiment of the present invention. As shown in fig. 1, the present embodiment provides a hybrid analog-to-digital converter for a power private communication network, including: the system comprises a first-stage full parallel analog-to-digital converter, a second-stage successive approximation analog-to-digital converter SAR ADC and a decoder. The first-stage fully parallel analog-to-digital converter comprises a 4-bit fully parallel analog-to-digital converter 4-bit Flash ADC, a first capacitor array and a digital coding circuit, and is used for carrying out quantization conversion on high bits of an analog input signal to obtain a 4-bit digital output code. The second-stage successive approximation analog-to-digital converter SAR ADC comprises a second capacitor array, a comparator and an 8-bit successive approximation analog-to-digital conversion logic circuit (8-bit SAR logic circuit), and is used for carrying out quantization conversion on the low bits of the analog input signal to obtain an 8-bit digital output code. The decoder is used for translating the 4-bit digital output code quantized and converted by the full parallel analog-to-digital converter and the 8-bit digital output code quantized and converted by the successive approximation analog-to-digital converter into a 12-bit digital signal and outputting the digital signal.
The Flash ADC has the advantages that one-time signal conversion can be completed in one clock cycle, the conversion speed is high, but the precision index is achieved by sacrificing the area occupied by the circuit (the Flash ADC with N bits needs 2)N1 comparator), the accuracy of the Flash ADC is not high. However, an N-bit SAR ADC requires N clock cycles to complete one signal conversion, and has a slow conversion speed but a high accuracy. Therefore, by combining the advantages of the Flash ADC and the SAR ADC, the first stage adopts the 4-bit Flash ADC, and the second stage adopts the 8-bit SAR ADC (the occupied area of the circuit is balanced with the saved clock period number), so that the effects of high conversion speed and high precision and reducing the whole power consumption are achieved.
The embodiment of the invention adopts a mode of combining a full parallel analog-to-digital converter and a successive approximation analog-to-digital converter to form a hybrid analog-to-digital converter for a power special communication network. The mixed analog-digital converter adopts a first-stage fully-parallel analog-digital converter 4-bit Flash ADC to realize coarse conversion (coarse quantization processing) on an input signal, then utilizes a second-stage successive approximation analog-digital converter 8-bit SAR ADC to realize fine conversion (fine quantization processing) on the input signal, combines the advantages of the Flash ADC (high resolution and conversion rate) and the SAR ADC (small area and low power consumption), and realizes the analog-digital conversion function with low power consumption and high rate. The hybrid analog-digital converter of the embodiment adopts a two-stage hybrid structure to realize the 12-bit analog-digital conversion function, and can meet the requirements of 230MHz frequency band of the electric wireless private network on high speed and low power consumption of data conversion by applying the hybrid analog-digital converter to a wireless signal transceiver.
In FIG. 1, VIP is the differential positive-phase analog input voltage, VIN is the differential negative-phase analog input voltage, VRP is the reference voltage, and VRN/GND represents the ground signal. CLKS is the sampling clock signal, CLK1 is the clock signal of the full parallel analog-to-digital converter, and CLK2 is the clock signal of the successive approximation analog-to-digital converter. At the end of the sampling phase, the input signal is sampled onto the first capacitor array and the Flash ADC performs a coarse quantization conversion on the input signal. The Flash ADC generates a 14-bit temperature code, so that the first step of 4-bit conversion is completed; and further, the Flash logic controls 14 x 2 high-level section capacitors to be connected into the VRP/VRN, and an analog residual error signal required by next conversion is generated. In the conversion phase, the SAR ADC converts the residual voltage into an 8-bit binary code (fine quantization conversion). Finally, the decoder converts the 14-bit temperature code and the 8-bit binary code into a 12-bit digital signal.
In FIG. 1, VIP is the differential positive-phase analog input voltage, VIN is the differential negative-phase analog input voltage, VRP is the reference voltage, and VRN/GND represents the ground signal. The first capacitor array of the first stage fully parallel analog-to-digital converter comprises: the capacitor comprises a first top plate capacitor array and a first bottom plate capacitor array, wherein the first top plate capacitor array and the first bottom plate capacitor array both comprise a plurality of first capacitors 4C connected in parallel. The second capacitor array of the second-stage successive approximation analog-to-digital converter SAR ADC includes: the capacitor array comprises a second top plate capacitor array and a second bottom plate capacitor array, wherein the second top plate capacitor array is connected with a differential positive phase analog input voltage VIP, and the second bottom plate capacitor array is connected with a differential inverse phase analog input voltage VIN. The second top plate capacitor array and the second bottom plate capacitor array both comprise two second capacitors 2C which are connected in parallel and have the same capacity and four third capacitors C which are connected in parallel and have the same capacity, and the capacity of the second capacitors 2C is twice that of the third capacitors C. One second capacitor 2C of the two second capacitors is connected to the reference voltage VRP, and the other second capacitor 2C is connected to the ground signal VRN/GND. Two third capacitors C of the four third capacitors C are connected with the reference voltage VRP, and the other two third capacitors C are connected with the ground signal VRN/GND. The embodiment provides a hybrid analog-to-digital converter for a power private communication network, which further comprises a third capacitor array in signal connection with the decoder. The third capacitor array comprises a third top plate capacitor array and a third bottom plate capacitor array, the third top plate capacitor array and the third bottom plate capacitor array respectively comprise four capacitors (8C, 4C and 2C, C) connected in parallel, the capacities of the four capacitors are sequentially arranged in a multiple decreasing mode, and each capacitor is connected to a reference voltage VRP and a ground signal VRN/GND. Note that C in the capacitor array of fig. 1 represents a unit capacitance value, 2C represents twice the unit capacitance value, 4C represents four times the unit capacitance value, and 8C represents eight times the unit capacitance value.
The second capacitor array of the second-stage successive approximation analog-to-digital converter SAR ADC adopts a segmented capacitor design, and the capacitor array of the traditional structure is divided into two parts with the same size, namely two second capacitors, two third capacitors and two fourth capacitors. In the sampling phase, one second capacitor, one third capacitor and one fourth capacitor are connected to VRP, and the other second capacitor, the other third capacitor and the other fourth capacitor are connected to VRN. Only half of the discrete second capacitor array is required to change the voltage from VRP to VRN or from VRN to VRP after the comparator produces a result. Due to the design of the segmented capacitor, the direct access of a switch of the capacitor to a Voice Coil Motor (VCM) is avoided, the on-resistance is reduced, and the establishment speed of the capacitor array is increased. On the other hand, because the switch of the capacitor array consumes large power consumption when being switched, the total capacitance is reduced by the design of the segmented capacitor, and the power consumption (power consumption and fCV) consumed by the capacitor array is reduced2Proportional).
In the hybrid analog-to-digital converter provided by the embodiment, the residual error of the 8-bit SAR ADC conversion is smaller than the input signal of the 4-bit flash ADC conversion. This may avoid unnecessary charging and discharging on the reference voltage, i.e. consume less power, compared to conventional SAR. Fig. 2 is a connection diagram of a capacitor array before comparison in a second-stage successive approximation analog-to-digital converter SAR ADC according to an embodiment of the present invention. As can be seen from fig. 2, the hybrid analog-to-digital converter provided in this embodiment can realize a resolution of 12-bit by only 9-step conversion (the 4-bit Flash ADC performs one-step conversion, and the 8-bit SAR ADC performs 8-step conversion) in one analog-to-digital conversion. Whereas a conventional SAR ADC requires 12-step conversion to achieve a 12-bit resolution. It can be seen that the hybrid analog-to-digital converter of the present embodiment improves the conversion rate.
In this embodiment, dynamic comparators are used for the comparators of the first-stage full-parallel analog-to-digital converter 4-bit Flash ADC and the second-stage successive approximation analog-to-digital converter 8-bit SAR ADC. The dynamic comparator does not consume static power consumption, and is beneficial to realizing low power consumption. As shown in fig. 3, the dynamic comparator has a two-stage structure including a first-stage amplifier and a second-stage latch. The first-stage amplifier realizes pre-amplification of input signals, and the second-stage latch performs comparative latching on pre-amplification results. Since the noise equivalent of the second stage of the comparator to the input is the noise of the second stage divided by the gain of the first stage, the noise of the comparator depends mainly on the first stage, which is inversely proportional to the parasitic capacitance of the P-terminal or the N-terminal. In order to optimize the noise performance, it is not possible to add a load capacitance to the P terminal or the N terminal, because increasing the capacitance also reduces the operating speed of the comparator. To optimize noise while maintaining high speed operation of the comparator, the MOS transistor size of the SAR ADC comparator may be increased proportionally. Because the dynamic power consumption is increased by increasing the size of the MOS tube, the folded value of the size of the MOS tube can be selected under the condition of ensuring noise and power consumption.
For an 8-bit SAR ADC, the clock frequency that triggers the internal comparator is 8 times the external sampling clock. The speed of the working clock in the 8-bit SAR ADC is very high, the comparator completes comparison work in each bit conversion period, and the SAR logic circuit generates control signals and the operation established by the DAC. Because the minimum clock period of the synchronous SAR is limited by the maximum DAC setup time, the maximum comparison time and the maximum logic delay, the synchronous clock cannot be fully utilized, so that the conversion speed of the synchronous SAR ADC is limited. In contrast, the clock period of the asynchronous SAR is not fixed and can be automatically adjusted according to the comparison time of the comparator and the amplitude of the input signal, so that the conversion speed is increased. Therefore, the asynchronous clock is more suitable for a high-speed SAR ADC.
In this embodiment, the second-stage successive approximation analog-to-digital converter uses a gated ring oscillator circuit to generate an internal high-speed conversion clock, that is, a clock frequency for triggering the dynamic comparator is generated by the gated ring oscillator circuit. Fig. 4 is a schematic diagram of a gated ring oscillator circuit of a hybrid analog-to-digital converter for a power private communication network according to an embodiment of the present invention. As shown in fig. 4. When GT is 0, GCRO does not work. When GT is 1, GCRO starts to work. The conversion of CKC depends on the output results Q and QB of the comparators. The period of GCRO depends on the time the comparator produces a result and the time of reset, as well as the delay of the nand gate and the inverter. At the same time, the SAR ADC will complete the comparator comparison, the SAR logic circuit generates the control signal and the DAC set up at each clock. In the circuit design, the time per clock cycle can be achieved by sizing the nand gates and inverters to ensure that the DAC is fully established before the next comparison begins. In addition, the sum of the delay of the SAR logic and the settling time of the DAC can fluctuate for different process corners. As shown in fig. 3, the programmable resistor may be implemented by parallel gated switches, and further may control the delay of the nand gate, so that the ADC can adapt to the switches S1, S2, and S3 of the control signals of different process corners, and the programming may be implemented by the SPI interface of the SOC.
Fig. 5 is a conversion timing diagram of a hybrid analog-to-digital converter for a power private communication network according to an embodiment of the present invention. As shown in fig. 5, CLKS is the sampling clock signal of the hybrid analog-to-digital converter, CLK1 is the clock signal of the fully parallel analog-to-digital converter, and CLK2 is the clock signal of the successive approximation analog-to-digital converter. When the sampling clock signal CLKS is set at a high level, the first-stage full parallel analog-to-digital converter 4-bit Flash ADC and the second-stage successive approximation analog-to-digital converter 8-bit SAR ADC synchronously sample analog input signals (VIP and VIN), and the sampled signals are stored in the first top plate capacitor array and the second top plate capacitor array in the form of electric charge. When the first stage sampling is finished, the sampling clock signal CLKS is changed into low level, the clock signal CLK1 of the full parallel analog-to-digital converter is set to high level, at the moment, the full parallel analog-to-digital converter 4-bit Flash ADC performs coarse quantization processing on the voltage stored on the first top plate capacitor array, and then the high-order capacitor skipping and multiplexing (HCSR) algorithm is used for controlling the level switching of the bottom plate of the next top plate capacitor array. After the coarse quantization processing of the first-stage fully parallel analog-to-digital converter is finished, a clock signal CLK1 of the fully parallel analog-to-digital converter is set at a low level, a clock signal CLK2 of the second-stage successive approximation analog-to-digital converter is set at a high level, at the moment, the second-stage successive approximation analog-to-digital converter 8-bit SAR ADC performs fine quantization processing on the voltage stored on the second top plate capacitor array, and then the level switching of the bottom plate of the next capacitor array is controlled through an HCSR algorithm according to the obtained digital code. In this embodiment, the first stage of the fully parallel analog-to-digital converter 4-bit Flash ADC and the second stage of the successive approximation analog-to-digital converter 4-bit Flash ADC are connected to analog input signals (VIP, VIN) through bootstrap switches. The second capacitor arrays of the 4-bit Flash ADC and the 4-bit Flash ADC are connected to the analog input signal through a grid voltage bootstrap switch (not shown in the attached drawing), so that the analog input signal can be tracked, extra power consumption and thermal noise introduced by a sample-and-hold amplifier (SHA) are avoided, and the influence of sampling kickback noise is effectively reduced. In addition, the on-resistance of the bootstrap switch is stable and does not change along with the change of the input signal, and the linearity of the input signal can be ensured.
The embodiment of the invention also provides a signal transceiver for the power private communication network, which comprises the hybrid analog-to-digital converter for the power private communication network, and the signal transceiver can meet the requirements of the 230MHz frequency band of the power wireless private network on high speed and low power consumption of data conversion.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention.
Claims (10)
1. A hybrid analog-to-digital converter for a power private communication network, comprising: the system comprises a first-stage full parallel analog-to-digital converter, a second-stage successive approximation analog-to-digital converter and a decoder;
the first-stage fully-parallel analog-to-digital converter comprises a 4-bit fully-parallel analog-to-digital converter, a first capacitor array and a digital coding circuit, and is used for carrying out quantization conversion on high bits of an analog input signal to obtain a 4-bit digital output code;
the second-stage successive approximation analog-to-digital converter comprises a second capacitor array, a comparator and an 8-bit successive approximation analog-to-digital conversion logic circuit, and is used for carrying out quantization conversion on the low bits of the analog input signal to obtain an 8-bit digital output code;
the decoder is used for translating the 4-bit digital output code quantized and converted by the full parallel analog-to-digital converter and the 8-bit digital output code quantized and converted by the successive approximation analog-to-digital converter into a 12-bit digital signal and outputting the digital signal.
2. The hybrid analog-to-digital converter for power private communication network of claim 1, wherein the second capacitor array comprises: the capacitor array of the second top plate is connected with the differential normal-phase analog input voltage, and the capacitor array of the second bottom plate is connected with the differential reverse-phase analog input voltage;
the second top plate capacitor array and the second bottom plate capacitor array both comprise two second capacitors connected in parallel and having the same capacity and four third capacitors connected in parallel and having the same capacity, and the capacity of the second capacitors is twice that of the third capacitors.
3. The hybrid analog-to-digital converter for power private communication network of claim 2, wherein one of the two second capacitors is connected with a reference voltage, and the other second capacitor is connected with a ground signal; two third capacitors of the four third capacitors are connected with reference voltage, and the other two third capacitors are connected with a grounding signal.
4. The hybrid analog-to-digital converter for power private communication network of claim 3, wherein the first capacitor array comprises: the capacitor array comprises a first top plate capacitor array and a first bottom plate capacitor array, wherein the first top plate capacitor array and the first bottom plate capacitor array both comprise a plurality of first capacitors connected in parallel.
5. The hybrid analog-to-digital converter for power private communication network of claim 3, further comprising: a third capacitor array in signal connection with the decoder;
the third capacitor array comprises a third top plate capacitor array and a third bottom plate capacitor array, and the third top plate capacitor array and the third bottom plate capacitor array are both connected with the reference voltage and the grounding signal.
6. The hybrid analog-to-digital converter for power private communication network according to claim 1, wherein the comparator of the second-stage successive approximation analog-to-digital converter is a dynamic comparator;
the dynamic comparator comprises a first-stage amplifier and a second-stage latch, wherein the first-stage amplifier is used for pre-amplifying an input signal, and the second-stage latch is used for comparing and latching a pre-amplified result of the first-stage amplifier.
7. The hybrid analog-to-digital converter for power private communication network of claim 6, wherein the second stage successive approximation analog-to-digital converter employs a gated ring oscillator circuit to generate a clock frequency that triggers the dynamic comparator.
8. The hybrid analog-to-digital converter for power private communication network according to claim 4, wherein when the sampling clock signal of the hybrid analog-to-digital converter is set to high level, the first stage full parallel analog-to-digital converter and the second stage successive approximation analog-to-digital converter synchronously sample the analog input signal, and store the sampled signal in the form of charge amount in the first top plate capacitor array and the second top plate capacitor array;
when the first-stage sampling is finished, the sampling clock signal is changed into low level, the clock signal of the full-parallel analog-to-digital converter is set to high level, and at the moment, the full-parallel analog-to-digital converter performs coarse quantization processing on the voltage stored on the first top plate capacitor array;
after the coarse quantization processing of the first-stage fully parallel analog-to-digital converter is completed, the clock signal of the fully parallel analog-to-digital converter is set at a low level, the clock signal of the second-stage successive approximation analog-to-digital converter is set at a high level, and at the moment, the second-stage successive approximation analog-to-digital converter performs fine quantization processing on the voltage stored on the second top plate capacitor array.
9. The hybrid analog-to-digital converter for a power private communication network of claim 1, wherein the fully parallel analog-to-digital converter is connected to the analog input signal through a bootstrapped switch.
10. A signal transceiving apparatus for a power private communication network, comprising the hybrid analog-to-digital converter for a power private communication network according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011024305.8A CN112187265A (en) | 2020-09-25 | 2020-09-25 | Mixed type analog-digital converter and signal transceiver for electric power special communication network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011024305.8A CN112187265A (en) | 2020-09-25 | 2020-09-25 | Mixed type analog-digital converter and signal transceiver for electric power special communication network |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112187265A true CN112187265A (en) | 2021-01-05 |
Family
ID=73943605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011024305.8A Pending CN112187265A (en) | 2020-09-25 | 2020-09-25 | Mixed type analog-digital converter and signal transceiver for electric power special communication network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112187265A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929028A (en) * | 2021-01-25 | 2021-06-08 | 中国科学院半导体研究所 | Hybrid analog-to-digital converter system |
| CN114499529A (en) * | 2022-04-01 | 2022-05-13 | 浙江地芯引力科技有限公司 | Analog-digital converter circuit, analog-digital converter, and electronic apparatus |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684465A (en) * | 2013-12-20 | 2014-03-26 | 清华大学 | Multiphase clock generating circuit for asynchronous successive approximation analog/digital converter |
| CN103905049A (en) * | 2014-03-11 | 2014-07-02 | 中国科学院半导体研究所 | High speed quick flashing plus alternating comparison type successive approximation analog to digital converter |
| CN106209102A (en) * | 2016-06-27 | 2016-12-07 | 合肥工业大学 | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter |
| CN107425852A (en) * | 2017-06-22 | 2017-12-01 | 西安电子科技大学 | Gradual approaching A/D converter based on binary weights Charge scaling |
| CN110311677A (en) * | 2019-07-10 | 2019-10-08 | 湖北汽车工业学院 | A kind of SAR ADC based on novel capacitor switching algorithm |
| CN111446964A (en) * | 2020-04-10 | 2020-07-24 | 上海交通大学 | Novel fourteen-bit assembly line-successive approximation type analog-digital converter |
-
2020
- 2020-09-25 CN CN202011024305.8A patent/CN112187265A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684465A (en) * | 2013-12-20 | 2014-03-26 | 清华大学 | Multiphase clock generating circuit for asynchronous successive approximation analog/digital converter |
| CN103905049A (en) * | 2014-03-11 | 2014-07-02 | 中国科学院半导体研究所 | High speed quick flashing plus alternating comparison type successive approximation analog to digital converter |
| CN106209102A (en) * | 2016-06-27 | 2016-12-07 | 合肥工业大学 | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter |
| CN107425852A (en) * | 2017-06-22 | 2017-12-01 | 西安电子科技大学 | Gradual approaching A/D converter based on binary weights Charge scaling |
| CN110311677A (en) * | 2019-07-10 | 2019-10-08 | 湖北汽车工业学院 | A kind of SAR ADC based on novel capacitor switching algorithm |
| CN111446964A (en) * | 2020-04-10 | 2020-07-24 | 上海交通大学 | Novel fourteen-bit assembly line-successive approximation type analog-digital converter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929028A (en) * | 2021-01-25 | 2021-06-08 | 中国科学院半导体研究所 | Hybrid analog-to-digital converter system |
| CN114499529A (en) * | 2022-04-01 | 2022-05-13 | 浙江地芯引力科技有限公司 | Analog-digital converter circuit, analog-digital converter, and electronic apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105391451A (en) | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof | |
| US7414562B2 (en) | Analog-to-digital conversion using asynchronous current-mode cyclic comparison | |
| TWI521887B (en) | Successive approximation register anolog-to-digital converter | |
| US6473021B1 (en) | Analog to digital conversion circuits, systems and methods with gain scaling switched-capacitor array | |
| KR101435978B1 (en) | Hybrid pipeline ADC using time-interleaved SAR and flash ADC | |
| US8823566B2 (en) | Analog to digital conversion architecture and method with input and reference voltage scaling | |
| CN112187265A (en) | Mixed type analog-digital converter and signal transceiver for electric power special communication network | |
| CN109644002B (en) | Scalable random successive approximation register analog-to-digital converter | |
| US10826520B1 (en) | Successive approximation register analog-to-digital converter | |
| CN110690901A (en) | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit | |
| CN112564709B (en) | Noise shaping successive approximation analog-to-digital converter based on error feedback | |
| CN113676183B (en) | High-precision low-power-consumption SAR ADC based on two steps | |
| CN112994699B (en) | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method | |
| Chen et al. | A 1-V 8-bit 100kS/s-to-4MS/s asynchronous SAR ADC with 46fJ/conv.-step | |
| CN112564704B (en) | Successive approximation analog-to-digital converter with sampling time expansion function and electronic device | |
| CN110198167B (en) | Asymmetric SAR ADC capacitance switch sequential circuit and method | |
| Gu et al. | An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation | |
| WO2021137686A1 (en) | Interfacing circuit and analog to digital converter for battery monitoring applications and a method thereof | |
| Yang et al. | A 0.5 V 16nW 8.08-ENOB SAR ADC for ultra-low power sensor applications | |
| Ishizuka et al. | Design of resource sharing reconfigurable ΔΣ SAR-ADC | |
| Jiangl et al. | A 13-bit 70MS/s SAR-Assisted 2-bit/cycle Cyclic ADC with Offset Cancellation and Slack-Borrowing Logic | |
| Dhage et al. | Design of power efficient hybrid flash-successive approximation register analog to digital converter | |
| Gu et al. | Power efficient SAR ADC with optimized settling technique | |
| CN107517059B (en) | Circuit and method for improving conversion speed of analog-to-digital converter | |
| CN114448439B (en) | TDC-based two-step successive approximation type analog-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |