CN114095029B - Successive approximation type analog-to-digital converter capable of reducing number of capacitors and switches - Google Patents

Abstract

The invention discloses a successive approximation type analog-to-digital converter capable of reducing the number of capacitors and switches, which comprises a DAC module, a voltage comparator and an SAR logic control circuit which are electrically connected in sequence, wherein the SAR logic control circuit outputs a switch control signal to control the output of the DAC module, and the comparison is completed in the voltage comparator. The capacitor array adopts a segmented capacitor structure, a segmentation calculation method of the minimum capacitance quantity is provided, the required capacitance quantity is effectively reduced, the capacitance quantity of the capacitor array can be saved by about 96% compared with the traditional capacitor array, and the capacitance quantity of the capacitor array can be saved by 37% -90% compared with other types of segmented capacitor structures; the simpler CMOS complementary switch is used as a switch, and a unit capacitor is further added to the high potential section, so that the low potential section capacitor does not need to be sampled, and the switching cost is further saved; the highest weighted capacitor of the high potential segment of the capacitor array is split, so that the common mode level Vcm is not required to be connected into a switch in a charge transfer stage, and the switching overhead can be saved by about 20%.

Description

Successive approximation type analog-to-digital converter capable of reducing number of capacitors and switches

Technical Field

The present invention relates to a successive approximation type analog-to-digital converter, and more particularly, to a successive approximation type analog-to-digital converter with reduced capacitance and switching.

Background

The successive approximation analog-to-digital converter (SAR ADC) is a medium-high precision and medium-speed analog-to-digital converter, and is commonly used in occasions such as mobile equipment, biological signal processing, medical equipment and the like due to the advantages of low power consumption, small area and the like.

The SARADC analog-to-digital converter adopts binary search algorithm (Binary Search Algorithm), and the system structure utilizes a DAC to produce a series of analog voltage values and input signal voltage, and makes comparison by means of voltage comparator to progressively define final digital code D0]，D[1]，……，D[n]. In an ideal converter, the input voltage signal Vin is equal to the redundancy voltage V in the capacitor _residual And converted DAC voltage V _DAC And (3) summing. When the last conversion is completed, the redundant voltage V _residual Should be as follows0V, when the input voltage Vin is equal to the DAC voltage V _DAC The system has been described as converting the input signal entirely into a digital signal.

However, in practice, due to the excessive number of capacitors and the huge number of switches, the problems of capacitor mismatch, excessive energy consumption and the like are caused, and finally, the input signals cannot be completely converted, so that linear and nonlinear errors are caused. In the conventional analog-to-digital converter circuit, in order to reduce the number of capacitors, a capacitor segmented array is generally adopted, that is, an original capacitor array is divided into two sections by adopting bridge capacitors, and each section is assigned to a capacitor according to a binary weight. The number of the used switches is determined by connecting the capacitor with different reference levels, and when energy is calculated, the capacitor does not consume energy, and the consumed energy is energy consumption generated when the switch is switched, so that the system energy consumption can be reduced by reducing the number of the switches. The current designs generally suffer from several problems: 1. the traditional capacitor array has a large number of capacitors, a segmented capacitor technology can be introduced to segment the capacitor array, but how to segment optimally is not solved yet, and most of the capacitors are determined empirically in practice; 2. the grid voltage bootstrap switch is adopted, when sampling is carried out, the on-resistance is related to an input signal due to the influence of a substrate bias effect, linearity is influenced, and 2N grid voltage bootstrap switches are needed to be used in half of the traditional structure, so that great power consumption and area cost are brought; 3. while ensuring the accuracy of the capacitor array, consider how to reduce the number of switches.

Disclosure of Invention

The invention aims to: aiming at the problems, the invention provides a successive approximation type analog-to-digital converter which reduces the capacitance and the number of switches, effectively reduces the required capacitance number and saves the switching cost.

The technical scheme is as follows: the technical scheme adopted by the invention is a successive approximation type analog-to-digital converter for reducing the number of capacitors and switches, which comprises a DAC module, a voltage comparator and an SAR logic control circuit which are electrically connected in sequence, wherein the SAR logic control circuit outputs a switch control signal to control the output of the DAC module, the voltage comparator finishes comparison, and the DA logic control circuit outputs a switch control signal to control the output of the DAC moduleThe C module comprises an in-phase end processing module and an anti-phase end processing module, wherein the in-phase end processing module comprises an in-phase end capacitor array, an in-phase end switch control circuit and an in-phase end sampling circuit, the in-phase end capacitor array is divided into a low-potential section capacitor array and a high-potential section capacitor array by coupling capacitors connected in series, each section of capacitor array is a capacitor connected in parallel in a binary weight sequence, the highest weight bit of the high-potential section capacitor array is composed of split capacitor groups C9 and C9s, and the number of parallel capacitors in the two split capacitor groups is equal; the free point of the high-potential capacitor array at the same phase end except the split capacitor group is selectively connected with a common mode level Vcm, a same phase reference level VRP, a reverse phase reference level VRN or a same phase input signal V through a switch control circuit at the same phase end _ip The free point of the split capacitor group is selectively connected into an in-phase reference level VRP, an anti-phase reference level VRN or an in-phase input signal V through an in-phase end switch control circuit _ip The method comprises the steps of carrying out a first treatment on the surface of the The common point of the capacitor array at the same phase end is used as the output of the processing module at the same phase end and is connected with the same phase input end of the voltage comparator; the circuit structure of the inverting terminal processing module is symmetrical with the non-inverting terminal processing module, and the output of the inverting terminal processing module is connected with the inverting input terminal of the voltage comparator.

The high-potential section capacitor array also comprises a unit capacitor Cc, and the sampling signal is input to the unit capacitor Cc to replace the sampling of the low-potential section capacitor, thereby saving 2 ^L -1 switch.

Further, the calculation formula of the total capacitance number of the capacitor array is as follows:

wherein C is _tot Is the total capacitance of the capacitor array, C _u The unit capacitance is represented, L represents the low potential segment bit number, M represents the high potential segment bit number, m+l=n, N being the bit number of the successive approximation type analog-to-digital converter, and the equal sign holds if and only if m=l.

The relation among the common mode level Vcm, the in-phase reference level VRP and the anti-phase reference level VRN is: vcm=1/2 (vrp+vrn).

The successive approximation type analog-to-digital converter is 10 bits, the capacitor array of the low potential section of the same phase end consists of 4 unit capacitor groups of C1, C2, C3 and C4, and the capacitor array of the high potential section of the same phase end consists of 6 unit capacitor Cc and 6 capacitor groups of C5, C6, C7, C8, C9 and C9 s; the capacitor group C1 is provided with 1 unit capacitor, the capacitor group C2 is connected in parallel by 2 unit capacitors, the capacitor group C3 is connected in parallel by 4 unit capacitors, and the capacitor group C4 is connected in parallel by 8 unit capacitors; the capacitor group C5 is provided with 1 unit capacitor, the capacitor group C6 is connected in parallel by 2 unit capacitors, the capacitor group C7 is connected in parallel by 4 unit capacitors, the capacitor group C8 is connected in parallel by 8 unit capacitors, the capacitor group C9 is connected in parallel by 8 unit capacitors, and the capacitor group C9s is connected in parallel by 8 unit capacitors.

The in-phase end switch control array comprises 10 PMOS tubes M1-M10 and 18 NMOS tubes M11-M28; the source electrodes of the PMOS tubes M1-M10 are connected with the level VRP, and the grid electrodes are respectively connected with feedback signals P <1> -P <9> and P <9s >; the source electrodes of the NMOS tubes M11-M18 are connected with a common mode level Vcm, and the grid electrodes are respectively connected with feedback signals M <1> to M <8>; the sources of NMOS transistors M19-M28 are connected with the reverse reference level VRN, and the gates are respectively connected with feedback signals N <1> -N <9> and N <9s >.

The drain electrode of the PMOS tube M1, the drain electrode of the NMOS tube M11 and the drain electrode of the NMOS tube M19 are connected to form a node S _p1 The drain electrode of the PMOS tube M2, the drain electrode of the NMOS tube M12 and the drain electrode of the NMOS tube M20 are connected to form a node S _p2 The drain electrode of the PMOS tube M3, the drain electrode of the NMOS tube M13 and the drain electrode of the NMOS tube M21 are connected to form a node S _p3 The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the PMOS tube M4, the drain electrode of the NMOS tube M14 and the drain electrode of the NMOS tube M22 are connected to form a node S _p4 The drain electrode of the PMOS tube M5, the drain electrode of the NMOS tube M15 and the drain electrode of the NMOS tube M23 are connected to form a node S _p5 The drain electrode of the PMOS tube M6, the drain electrode of the NMOS tube M16 and the drain electrode of the NMOS tube M24 are connected to form a node S _p6 The drain electrode of the PMOS tube M7, the drain electrode of the NMOS tube M17 and the drain electrode of the NMOS tube M25 are connected to form a node S _p7 The drain electrode of the PMOS tube M8, the drain electrode of the NMOS tube M18 and the drain electrode of the NMOS tube M26 are connected to form a node S _p8 The drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M27 to form a node S _p9 The method comprises the steps of carrying out a first treatment on the surface of the PMOS tubeThe drain electrode of M10 is connected with the drain electrode of NMOS tube M28 to form a node S _p9s 。

The in-phase end sampling circuit comprises 7 PMOS (P-channel metal oxide semiconductor) transistors M1, M5, M6, M9, M10, M13 and M14, and 8 NMOS transistors M2, M3, M4, M7, M8, M11, M12 and M15. Wherein the source electrode of the PMOS tube M1 is connected with the positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M2, the grid electrode of the NMOS tube M2 is connected with the clock signal NC_2, the source electrode is connected with the common mode level VCM, and the source electrode of the NMOS tube M3 is connected with the normal phase input signal V _ip The grid is connected with a clock signal C_2, the drain is connected with the drain of M1 and the drain of M2, and the node is also connected with the lower electrode plate of a coupling capacitor Cs in the capacitor array; the drain electrode of the NMOS tube M4 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M5 and is simultaneously connected with the switch control array node S _p5 The drain electrode of the PMOS tube M5 is connected with the normal phase input signal V _ip The grid electrode is connected with a clock signal NC_2; the source electrode of the PMOS tube M6 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M7, and is simultaneously connected with the node S in the switch control array _p6 The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the NMOS tube M7 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2; the drain electrode of the NMOS tube M8 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M9 and is simultaneously connected with the node S of the switch control array _p7 The drain electrode of the PMOS tube M9 is connected with the normal phase input signal V _ip The grid is connected with a clock signal NC_2; the source electrode of the PMOS tube M10 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M11, and is simultaneously connected with the switch control array node S _p8 The source electrode of the NMOS tube M11 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2; the drain electrode of the NMOS tube M12 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M13, and is simultaneously connected with the node S of the switch control array _p9s The drain electrode of the PMOS tube M13 is connected with the normal phase input signal V _ip The grid electrode is connected with a clock signal NC_2; the source electrode of the PMOS tube M14 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the NMOS tube M15, and is simultaneously connected withNode S _p9 The source electrode of the NMOS tube M15 is connected with a normal phase input signal V _ip The gate is connected to the clock signal C_2.

The beneficial effects are that: compared with the prior art, the invention has the following advantages: 1. the capacitor array adopts a segmented capacitor structure, and charge transfer is utilized, so that the process of reference establishment is not needed in the first comparison, and the cost of a one-bit capacitor group can be saved; the segmentation calculation method of the minimum capacitance quantity is provided, the minimum capacitance quantity which can be used by the segmentation capacitance is calculated, so that the capacitance quantity of the capacitance array is not increased in an exponential form any more, the required capacitance quantity is effectively reduced, the capacitance quantity of the segmentation capacitor array can be saved by about 96% compared with the traditional capacitance array, and the capacitance quantity of the segmentation capacitor array can be saved by 37% -90% compared with other types of segmentation capacitor structures; meanwhile, common mode level Vcm is introduced as reference voltage, so that dynamic energy consumption of the switch in the conversion process is greatly reduced; 2. the grid voltage bootstrap switch with large energy consumption and large area is not adopted, a simpler complementary CMOS switch is used as a switch, a unit capacitor is further added in a high potential section, and a sampling signal is input into the unit capacitor, so that the capacitor in a low potential section does not need to be sampled, and the switching cost is further saved; 3. the highest weighted capacitor of the high potential segment is split, so that the common mode level Vcm is not required to be connected into a switch in a charge transfer stage, and the switching overhead can be saved by about 20%.

Drawings

FIG. 1 is a circuit diagram of a 10-bit SAR ADC according to the present subject matter;

FIG. 2 is a diagram showing the connection of a capacitor array, a switch control circuit and a sampling switch circuit of a 10-bit SAR ADC positive-phase processing module (the reverse-phase processing module is symmetrical to the positive-phase processing module);

FIG. 3 is a segmented capacitive structural analysis diagram of an N-bit SAR ADC according to the present subject matter;

fig. 4 is an equivalent circuit diagram of a segmented capacitor structure of the N-bit SAR ADC according to the present invention, wherein (a) is an equivalent circuit diagram of a high-potential segment capacitor array, and (b) is an equivalent circuit diagram of a low-potential segment capacitor array.

Detailed Description

The technical scheme of the invention is further described below with reference to the accompanying drawings and examples.

Taking a 10-bit successive approximation type analog-to-digital converter as an example, a circuit diagram of a successive approximation type analog-to-digital converter with reduced capacitance and switch number according to the present invention is shown in fig. 1. The structure includes a capacitor array 10, a switch control circuit, a sampling circuit, a Vcm sampling circuit 40, a voltage comparator 50, and a SAR logic control circuit 60. The capacitor array 10 is further divided into a positive-phase capacitor array 101 and a negative-phase capacitor array 102; the switch control circuit comprises a positive phase end switch control circuit 201 and a negative phase end switch control circuit 202; the sampling circuit includes a positive-side sampling circuit 301 and a negative-side sampling circuit 302.

The positive-phase capacitor array 101 can be connected to a positive-phase input signal V through a positive-phase switch control circuit 201 and a positive-phase sampling circuit 301 _ip The inverting input signal V is accessible to the inverting capacitive array 102 through the inverting switch control circuit 202 and the inverting sampling circuit 302 _in The positive-phase end capacitor array 101 is connected with the positive-phase input end of the voltage comparator 50, and the negative-phase end capacitor array 102 is connected with the negative-phase input end of the voltage comparator 50; an output terminal of the voltage comparator 50 is connected to an input terminal of the SAR logic control circuit 60; the output terminal of the SAR logic control circuit 60 outputs a normal phase switch control signal SLP and an inverse phase switch control signal SLN, the normal phase switch control signal SLP is connected to the normal phase switch control circuit 201, and the inverse phase switch control signal SLN is connected to the inverse phase switch control circuit 202. The switch control circuit forms a double-end signal input and a double-end input and output of the capacitor array 10, and the used signals are differential input signals. Wherein the common mode level Vcm takes on the following values: vcm=1/2 (vrp+vrn), VRP is a positive reference level, VRN is an inverted reference level. The Vcm sampling circuit 40 is connected to the free point of the capacitor array 10 through a sampling switch, and the switch is opened after the sampling is finished.

The positive phase end capacitor array 101 comprises a positive phase end low potential section capacitor array, a coupling capacitor Cs and a positive phase end high potential section capacitor array; the positive-phase end low-potential section consists of 4 unit capacitor groups of C1, C2, C3 and C4, and the positive-phase end high-potential section consists of 7 unit capacitor groups of Cc, C5, C6, C7, C8, C9 and C9 s. Wherein, the highest weight bit of the high potential section of the normal phase end is composed of split capacitor groups C9 and C9 s. The coupling capacitor Cs connects the low potential section and the high potential section in series, and the capacitors in each section are connected in parallel. Each section of capacitor array is arranged in a binary weight sequence, C1 in the positive-phase end low-potential section capacitor array has 1 unit capacitor, C2 is connected in parallel by 2 unit capacitors, C3 is connected in parallel by 4 unit capacitors, C4 is connected in parallel by 8 unit capacitors, and 15 unit capacitors are needed; cc in the positive-phase end high-potential section capacitor array has 1 unit capacitor, C5 has 1 unit capacitor, C6 is connected in parallel by 2 unit capacitors, C7 is connected in parallel by 4 unit capacitors, C8 is connected in parallel by 8 unit capacitors, C9s is connected in parallel by 8 unit capacitors, and the total number of the unit capacitors is 32; the value of the coupling capacitance Cs is equal to the unit capacitance value, so the total capacitance number of the positive-phase-side capacitor array is 48 unit capacitances.

The top plates of 4 unit capacitor groups in the positive-phase end low-potential capacitor array and the top plates of 7 unit capacitor groups in the high-potential capacitor array are connected in series through coupling capacitors Cs to form a common point, and are connected with the positive-phase input end of the voltage comparator 50, and are connected with a common mode level Vcm through the Vcm sampling circuit 40; the bottom plates (free points) of the positive-side high-potential section capacitor array (except the highest weight capacitor group C9 and capacitor group C9 s) can be connected with the common-mode level Vcm, the positive-side reference level VRP, the reverse-phase reference level VRN or connected with the positive-side input signal V through the positive-side switch control circuit 201 _ip The bottom plates of the highest weight capacitor groups C9 and C9s can be connected into a normal phase reference level VRP, an inverse phase reference level VRN or a normal phase input signal V through a normal phase end switch control circuit 201 _ip The method comprises the steps of carrying out a first treatment on the surface of the The bottom plates (free points) of the four unit capacitor groups of the positive-phase end low-potential capacitor array can be connected with a common mode level Vcm, a positive-phase reference level VRP and an inverted reference level VRN through a positive-phase end switch control circuit 201.

Referring to fig. 2, the non-inverting terminal switch control array 201 includes 10 PMOS transistors M1 to M10 and 18 NMOS transistors M11 to M28.

Wherein the source electrodes of the PMOS tubes M1-M10 are connected with the level VRP, and the grid electrodes are respectively connected with the feedback signal P<i>～P<9>And P <9s>The method comprises the steps of carrying out a first treatment on the surface of the Source electrodes of NMOS transistors M11-M18Connected with common mode level Vcm, and the grid electrodes are respectively connected with feedback signals M<1>～M<8>The method comprises the steps of carrying out a first treatment on the surface of the The sources of NMOS tubes M19-M28 are connected with the reverse reference level VRN, and the grids are respectively connected with the feedback signal N<1>～N<9>And N <9s>The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the PMOS tube M1, the drain electrode of the NMOS tube M11 and the drain electrode of the NMOS tube M19 are connected to form a node S _p1 The drain electrode of the PMOS tube M2, the drain electrode of the NMOS tube M12 and the drain electrode of the NMOS tube M20 are connected to form a node S _p2 The drain electrode of the PMOS tube M3, the drain electrode of the NMOS tube M13 and the drain electrode of the NMOS tube M21 are connected to form a node S _p3 The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the PMOS tube M4, the drain electrode of the NMOS tube M14 and the drain electrode of the NMOS tube M22 are connected to form a node S _p4 The drain electrode of the PMOS tube M5, the drain electrode of the NMOS tube M15 and the drain electrode of the NMOS tube M23 are connected to form a node S _p5 The drain electrode of the PMOS tube M6, the drain electrode of the NMOS tube M16 and the drain electrode of the NMOS tube M24 are connected to form a node S _p6 The drain electrode of the PMOS tube M7, the drain electrode of the NMOS tube M17 and the drain electrode of the NMOS tube M25 are connected to form a node S _p7 The drain electrode of the PMOS tube M8, the drain electrode of the NMOS tube M18 and the drain electrode of the NMOS tube M26 are connected to form a node S _p8 The drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M27 to form a node S _p9 The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the PMOS tube M10 is connected with the drain electrode of the NMOS tube M28 to form a node S _p9s 。

The width and length of the PMOS tube M1 are 3.7um/550nm, the width and length of the PMOS tube M2 are 4.6um/550nm, the width and length of the PMOS tube M3 are 9.2um/550nm, the width and length of the PMOS tube M4 are 13.4um/550nm, the width and length of the PMOS tube M5 are 3.7um/550nm, the width and length of the PMOS tube M6 are 4.6um/550nm, the width and length of the PMOS tube M7 are 9.2um/550nm, and the width and length of the PMOS tubes M8, M9 and M10 are 18.4um/nm; NMOS tube M11 is 1.7um/500nm, NMOS tube M12 is 2.2um/500nm, NMOS tube M13 is 4.2um/500nm, NMOS tube M14 is 8.4um/500nm, NMOS tube M15 is 1.7um/500nm, NMOS tube M16 is 2.2um/500nm, NMOS tube M17 is 4.2um/500nm, NMOS tube M18 is 8.4um/500nm; NMOS transistors M19 and M23 are 1.1um/500nm, NMOS transistors M20 and M24 are 1.4um/50nm, NMOS transistors M21 and M25 are 2.8um/500nm, and NMOS transistors M22, M26, M27 and M28 are 5.6um/500nm.

The positive phase sampling circuit 301 includes 7 PMOS transistors M1, M5, M6, M9, M10, M13, and M14, and 8 NMOS transistors M2, M3, M4, M7, M8, M11, M12, and M15.

Wherein the source electrode of the PMOS tube M1 is connected with the positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M2, the grid electrode of the NMOS tube M2 is connected with the clock signal NC_2, the source electrode is connected with the common mode level VCM, and the source electrode of the NMOS tube M3 is connected with the normal phase input signal V _ip The grid is connected with a clock signal C_2, the drain is connected with the drain of M1 and the drain of M2, and the node is also connected with the lower electrode plate of a coupling capacitor Cs in the capacitor array; the drain electrode of the NMOS tube M4 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M5 and is simultaneously connected with the switch control array node S _p5 The drain electrode of the PMOS tube M5 is connected with the normal phase input signal V _ip The grid electrode is connected with a clock signal NC_2; the source electrode of the PMOS tube M6 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M7, and is simultaneously connected with the node S in the switch control array _p6 The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the NMOS tube M7 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2; the drain electrode of the NMOS tube M8 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M9 and is simultaneously connected with the node S of the switch control array _p7 The drain electrode of the PMOS tube M9 is connected with the normal phase input signal V _ip The grid is connected with a clock signal NC_2; the source electrode of the PMOS tube M10 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M11, and is simultaneously connected with the switch control array node S _p8 The source electrode of the NMOS tube M11 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2; the drain electrode of the NMOS tube M12 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M13, and is simultaneously connected with the node S of the switch control array _p9s The drain electrode of the PMOS tube M13 is connected with the normal phase input signal V _ip The grid electrode is connected with a clock signal NC_2; the source electrode of the PMOS tube M14 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the NMOS tube M15 and is simultaneously connected with the node S _p9 The source electrode of the NMOS tube M15 is connected with a normal phase input signal V _ip The gate is connected to the clock signal C_2.

The width-to-length ratio of the PMOS tube M1 is 3.7um/550nm, the NMOS tube M2 is 1.7um/500nm, the NMOS tubes M3 and M4 are 1.1um/500nm, the PMOS tube M5 is 3.7um/500nm, the PMOS tube M6 is 5.5 um/550nm, the NMOS tube M7 is 1.7um/500nm, the NMOS tube M8 is 2.8um/500nm, the PMOS tube M9 is 9.2um/550nm, the PMOS tubes M10, M13 and M14 are 18.4um/550nm, and the NMOS tubes M11, M12 and M15 are 5.6um/500nm.

Referring to fig. 2, a specific connection diagram of the capacitor array and the switch used in the present embodiment is shown. Wherein, according to the conventional structure, SARADC for Nbit requires 2 ^N The total unit capacitors are 1024 according to 10 bits designed in the embodiment, and the number of the capacitors is too large, so that the implementation is not easy. A segmented capacitive structure is introduced, dividing the capacitive array into two small arrays by the coupling capacitance Cs. The segmentation structure calculation method with the least capacitance is provided as follows, the SAR ADC structure with the least unit capacitance can be obtained, and the capacitance can be further reduced by combining other methods on the basis.

Referring to fig. 3, a classical capacitor array with a segmented structure is shown, if a step signal with an amplitude V is input at point (1) and point (2), respectively, point V is calculated ₀ The output signal change amounts at this point are shown in fig. 4 (a) and 4 (b) by simplifying the circuit, and include:

V ₀₁ ＝kC _u (Cs+C _L )V/X (1)

V ₀₂ ＝(2 ^L-1 CsC _u )V/X (2)

wherein C is _u Represents a unit capacitance, k represents k C _u Cs is the coupling capacitance, C _L Representing the total capacitance number of the low potential section, C _M For the total capacitance number of the high potential section, L represents the bit number of the low potential section, M represents the bit number of the high potential section, cd is the grounding capacitance, and the node V ₀ Point (1) and point (2); specific: c (C) _L ＝(2 ^L -1)C _u +C _d2 ，C _M ＝(2 ^M -1)kC _u +C _d1 ，X＝C _M (Cs+C _L )+CsC _L M+l=n. To maintain the correct weight of the array, ensure ADC linearity, should V ₀₁ ＝2V ₀₂ The method can obtain:

k(Cs+C _u )＝2 ^L Cs (3)

the method comprises the following steps of:

from C _L The total capacitance can be seen as:

C _L ≥(2 ^L -1)C _u (5)

combining formula (4) and formula (5), let k=1, yields:

C _L ＝(2 ^L -1)C _u (6)

Cs＝C _u ，C _d2 ＝0，C _d1 ＝C _u (7)

thus, in combination with (7) and (8), the total capacitance number of the segment structure capacitance is:

in equation (8), the equal sign holds if and only if m=l. That is, for an N-bit SAR ADC, when the high-potential number and the low-potential number are equal, the minimum capacitance number can be obtained, and the linearity requirement of the ADC can be maintained. When combining with the charge transfer stage in the bottom plate sampling to transfer the charge to the capacitor term plate (common point), the charge can be directly input to two input ends of the comparator for the first comparison, thus saving one capacitor group, so M or L can be one less on the original basis, i.e. the total capacitance number becomes C _tot ＝2 ^M-1 +2 ^L Or C _tot ＝2 ^M +2 ^L-1 . The embodiment needs 96 unit capacitors, which can save approximately 96% of capacitance compared with the traditional capacitor array and 37% -90% of capacitance compared with other segmented capacitor structures.

In this embodiment, by adding a capacitor Cc whose value is equal to the unit capacitor to the high-potential segment and inputting the sampling signal thereto, the low-potential segment capacitor does not need to be sampled, thereby saving 2 ^L -1 switch; in addition, the highest weight group of the high potential segment can obtain the common mode voltage Vcm by splitting the capacitor group instead of directly accessing Vcm level, so the highest weight group bit can save 2 ^M A Vcm switch; therefore in this practiceIn the embodiment, a total of 154 switches are needed, and the number of the switches is saved by nearly 20% compared with the original structure.

Claims (8)

1. The successive approximation type analog-to-digital converter comprises a DAC module, a voltage comparator and an SAR logic control circuit which are electrically connected in sequence, wherein the SAR logic control circuit outputs a switch control signal to control the DAC module to output, and the voltage comparator finishes comparison, and the successive approximation type analog-to-digital converter is characterized in that: the DAC module comprises an in-phase end processing module and an anti-phase end processing module, the in-phase end processing module comprises an in-phase end capacitor array, an in-phase end switch control array and an in-phase end sampling circuit, the in-phase end capacitor array is divided into a low potential section capacitor array and a high potential section capacitor array by coupling capacitors connected in series, each section of capacitor array is a capacitor connected in parallel in a binary weight sequence, the highest weight bit of the high potential section capacitor array is composed of split capacitor groups C9 and C9s, and the number of parallel capacitors in the two split capacitor groups is equal; the free point of the high-potential capacitor array at the same phase end except the split capacitor group is selectively connected with a common mode level Vcm, a same phase reference level VRP, a reverse phase reference level VRN or a same phase input signal V through a switch control circuit at the same phase end _ip The free point of the split capacitor group is selectively connected into an in-phase reference level VRP, an anti-phase reference level VRN or an in-phase input signal V through an in-phase end switch control circuit _ip The method comprises the steps of carrying out a first treatment on the surface of the The common point of the capacitor array at the same phase end is used as the output of the processing module at the same phase end and is connected with the same phase input end of the voltage comparator; the circuit structure of the inverting terminal processing module is symmetrical with the non-inverting terminal processing module, and the output of the inverting terminal processing module is connected with the inverting input terminal of the voltage comparator; the high-potential section capacitor array further comprises a unit capacitor Cc, and sampling signals are input to the unit capacitor Cc.

2. The reduced capacitance and switch count successive approximation analog-to-digital converter of claim 1 wherein: the successive approximation type analog-to-digital converter is 10 bits, the capacitor array of the low potential section of the same phase end consists of 4 unit capacitor groups of C1, C2, C3 and C4, and the capacitor array of the high potential section of the same phase end consists of 6 capacitor groups of unit capacitor Cc and C5, C6, C7, C8, C9 and C9 s; the capacitor group C1 is provided with 1 unit capacitor, the capacitor group C2 is connected in parallel by 2 unit capacitors, the capacitor group C3 is connected in parallel by 4 unit capacitors, and the capacitor group C4 is connected in parallel by 8 unit capacitors; the capacitor group C5 is provided with 1 unit capacitor, the capacitor group C6 is connected in parallel by 2 unit capacitors, the capacitor group C7 is connected in parallel by 4 unit capacitors, the capacitor group C8 is connected in parallel by 8 unit capacitors, the capacitor group C9 is connected in parallel by 8 unit capacitors, and the capacitor group C9s is connected in parallel by 8 unit capacitors.

3. The reduced capacitance and switch count successive approximation analog-to-digital converter of claim 2 wherein: the in-phase end switch control array comprises 10 PMOS tubes M1-M10 and 18 NMOS tubes M11-M28; the source electrodes of the PMOS tubes M1-M10 are connected with the level VRP, and the grid electrodes are respectively connected with feedback signals P <1> -P <9> and P <9s >; the source electrodes of the NMOS tubes M11-M18 are connected with a common mode level Vcm, and the grid electrodes are respectively connected with feedback signals M <1> to M <8>; the sources of NMOS transistors M19-M28 are connected with the reverse reference level VRN, and the gates are respectively connected with feedback signals N <1> -N <9> and N <9s >.

4. A successive approximation analog-to-digital converter with reduced number of capacitors and switches as claimed in claim 3, wherein: the drain electrode of the PMOS tube M1, the drain electrode of the NMOS tube M11 and the drain electrode of the NMOS tube M19 are connected to form a node S _p1 The drain electrode of the PMOS tube M2, the drain electrode of the NMOS tube M12 and the drain electrode of the NMOS tube M20 are connected to form a node S _p2 The drain electrode of the PMOS tube M3, the drain electrode of the NMOS tube M13 and the drain electrode of the NMOS tube M21 are connected to form a node S _p3 The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the PMOS tube M4, the drain electrode of the NMOS tube M14 and the drain electrode of the NMOS tube M22 are connected to form a node S _p4 The drain electrode of the PMOS tube M5, the drain electrode of the NMOS tube M15 and the drain electrode of the NMOS tube M23 are connected to form a node S _p5 The drain electrode of the PMOS tube M6, the drain electrode of the NMOS tube M16 and the drain electrode of the NMOS tube M24 are connected to form a node S _p6 The drain electrode of the PMOS tube M7, the drain electrode of the NMOS tube M17 and the drain electrode of the NMOS tube M25 are connected to form a node S _p7 The drain electrode of the PMOS tube M8, the drain electrode of the NMOS tube M18 and the drain electrode of the NMOS tube M26 are connected to form a node S _p8 The drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M27 to form a node S _p9 The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the PMOS tube M10 is connected with the drain electrode of the NMOS tube M28 to form a node S _p9s 。

5. The reduced capacitance and switch count successive approximation analog-to-digital converter of claim 2 wherein: the in-phase end sampling circuit comprises 7 PMOS (P-channel metal oxide semiconductor) transistors M1, M5, M6, M9, M10, M13 and M14, and 8 NMOS transistors M2, M3, M4, M7, M8, M11, M12 and M15.

6. The reduced capacitance and switch count successive approximation analog-to-digital converter of claim 5 wherein: the source electrode of the PMOS tube M1 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M2, the grid electrode of the NMOS tube M2 is connected with the clock signal NC_2, the source electrode is connected with the common mode level VCM, and the source electrode of the NMOS tube M3 is connected with the normal phase input signal V _ip The grid is connected with a clock signal C_2, the drain is connected with the drain of M1 and the drain of M2, and the node is also connected with the lower electrode plate of a coupling capacitor Cs in the capacitor array; the drain electrode of the NMOS tube M4 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M5 and is simultaneously connected with the switch control array node S _p5 The drain electrode of the PMOS tube M5 is connected with the normal phase input signal V _ip The grid electrode is connected with a clock signal NC_2; the source electrode of the PMOS tube M6 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M7, and is simultaneously connected with the node S in the switch control array _p6 The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the NMOS tube M7 is connected with a normal phase input signal V _ip The grid electrode is connected with a clock signal C_2; the drain electrode of the NMOS tube M8 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M9 and is simultaneously connected with the node S of the switch control array _p7 The drain electrode of the PMOS tube M9 is connected with the normal phase input signal V _ip The grid is connected with a clock signal NC_2; the source electrode of the PMOS tube M10 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the drain electrode of the NMOS tube M11, and is simultaneously connected with the switch control array node S _p8 Source of NMOS tube M11Polar connected with positive phase input signal V _ip The grid electrode is connected with a clock signal C_2; the drain electrode of the NMOS tube M12 is connected with a normal phase input signal V _ip The grid electrode is connected with the clock signal C_2, the source electrode is connected with the source electrode of the PMOS tube M13, and is simultaneously connected with the node S of the switch control array _p9s The drain electrode of the PMOS tube M13 is connected with the normal phase input signal V _ip The grid electrode is connected with a clock signal NC_2; the source electrode of the PMOS tube M14 is connected with a positive phase input signal V _ip The grid electrode is connected with the clock signal NC_2, the drain electrode is connected with the NMOS tube M15 and is simultaneously connected with the node S _p9 The source electrode of the NMOS tube M15 is connected with a normal phase input signal V _ip The gate is connected to the clock signal C_2.

7. The successive approximation analog-to-digital converter of claim 1, wherein the total capacitance of the capacitor array is calculated by the formula:

wherein C is _tot Is the total capacitance of the capacitor array, C _u The unit capacitance is represented, L represents the low potential segment bit number, M represents the high potential segment bit number, m+l=n, N being the bit number of the successive approximation type analog-to-digital converter, and the equal sign holds if and only if m=l.

8. The reduced capacitance and switching successive approximation analog-to-digital converter of claim 1, wherein the common mode level Vcm, the in-phase reference level VRP and the anti-phase reference level VRN are related by: vcm=1/2 (vrp+vrn).