CN114095029A - Successive approximation type analog-to-digital converter capable of reducing capacitance and switch number - Google Patents

Successive approximation type analog-to-digital converter capable of reducing capacitance and switch number Download PDF

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CN114095029A
CN114095029A CN202111428497.3A CN202111428497A CN114095029A CN 114095029 A CN114095029 A CN 114095029A CN 202111428497 A CN202111428497 A CN 202111428497A CN 114095029 A CN114095029 A CN 114095029A
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CN114095029B (en
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李效龙
杨双竹
曾睿
高亮
杨正文
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Jiangsu University of Science and Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed

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Abstract

The invention discloses a successive approximation type analog-digital converter for reducing the number of capacitors and switches, which comprises a DAC module, a voltage comparator and an SAR logic control circuit which are electrically connected in sequence, wherein the SAR logic control circuit outputs a switch control signal to control the output of the DAC module, and the comparison is completed in the voltage comparator. The capacitor array adopts a segmented capacitor structure, provides a segmented calculation method of the minimum capacitor quantity, and effectively reduces the required capacitor quantity, compared with the traditional capacitor array, the capacitor array can save the capacitor quantity by nearly 96 percent, and compared with segmented capacitor structures in other forms, the capacitor array can save the capacitor quantity by 37 to 90 percent; a simpler CMOS complementary switch is used as a switch, and a unit capacitor is further added in the high potential section, so that the low potential section capacitor does not need to be sampled, and the switch overhead is saved; by splitting the highest weight recombination capacitor of the high potential section of the capacitor array, the common-mode level Vcm is not required to be switched in through a switch in the charge transfer stage, and therefore the switching overhead can be saved by about 20%.

Description

Successive approximation type analog-to-digital converter capable of reducing capacitance and switch number
Technical Field
The present invention relates to successive approximation analog-to-digital converters, and more particularly, to a successive approximation analog-to-digital converter with reduced capacitance and switch count.
Background
A successive approximation analog-to-digital converter (SAR ADC) is an analog-to-digital converter with medium and high precision and medium speed, and is often used in mobile devices, bio-signal processing, medical devices and other occasions due to its advantages of low power consumption, small area and the like.
The principle of the SARADC analog-to-digital converter is that a Binary Search Algorithm (Binary Search Algorithm) is adopted, a system structure utilizes a DAC to generate a series of analog voltage values to be compared with input signal voltage through a voltage comparator, and the final digital code D [0 ] is determined step by step]，D[1]，……，D[n]. In an ideal converter, the input voltage signal Vin is equal to the redundancy voltage V in the capacitorresidualWith converted DAC voltage VDACAnd (4) summing. When the last conversion is completed, the redundant voltage VresidualShould be 0V, when the input voltage Vin equals the DAC voltage VDACThe system is described as having converted the input signal entirely to a digital signal.
However, in practice, due to the fact that the number of capacitors is too large and the number of switches is huge, the problems of capacitor mismatch, excessive energy consumption overhead and the like can be caused, and finally, input signals cannot be completely converted, so that linear and nonlinear errors are caused. In a conventional analog-to-digital converter circuit, a capacitor segmented array is generally adopted to reduce the number of capacitors, that is, a bridging capacitor is adopted to divide an original capacitor array into two segments, and each segment is assigned to a capacitor according to a binary weight value. The number of the used switches is also determined by the access of the capacitor to different reference levels, when the energy is calculated, the capacitor does not consume energy, and the consumed energy is energy consumption generated when the switches are switched, so that the energy consumption of the system can be reduced by reducing the number of the switches. The current designs generally have several problems as follows: 1. the traditional capacitor array needs more capacitors, a segmented capacitor technology can be introduced to segment the capacitor array, but how to segment the capacitor array is optimal is not solved, and the actual situation is mostly determined according to experience; 2. the gate voltage bootstrap switch is influenced by the substrate bias effect during sampling, so that the on-resistance is related to an input signal, the linearity is influenced, and in the traditional structure, 2N gate voltage bootstrap switches are needed to be used for one half, so that great power consumption and area overhead are brought; 3. the reduction of the number of switches is considered while ensuring the accuracy of the capacitor array.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the problems, the invention provides a successive approximation type analog-to-digital converter which reduces the number of capacitors and switches, effectively reduces the number of required capacitors and saves the switching overhead.
The technical scheme is as follows: the invention adopts the technical scheme that the successive approximation type analog-digital converter for reducing the number of capacitors and switches comprises a DAC module, a voltage comparator and an SAR logic control circuit which are sequentially and electrically connected, wherein the SAR logic control circuit outputs a switch control signal to control the output of the DAC module, the comparison is completed by the voltage comparator, the DAC module comprises a same-phase end processing module and an opposite-phase end processing module, the same-phase end processing module comprises a same-phase end capacitor array, a same-phase end switch control circuit and a same-phase end sampling circuit, the same-phase end capacitor array is divided into a low-potential section capacitor array and a high-potential section capacitor array by serially connected coupling capacitors, each section of capacitor array is a capacitor which is connected in parallel in a binary weight sequence, and the highest weight bit of the high-potential section capacitor array is formed by split capacitor groups C9 and C9s, the number of the parallel capacitors in the two split capacitor groups is equal; the free points of the high-potential capacitor array at the same phase end except the split capacitor group are selectively connected with a common-mode level Vcm, an in-phase reference level VRP, an inverted reference level VRN or an in-phase input signal V through an in-phase switch control circuitipThe free point of the split capacitor bank is selectively connected with an in-phase reference level VRP, an inverted reference level VRN or an in-phase input signal V through an in-phase end switch control circuitip(ii) a The common point of the in-phase end capacitor array is used as the output of the in-phase end processing module and is connected with the non-inverting input end of the voltage comparator; the circuit structure of the inverting terminal processing module is symmetrical to that of the non-inverting terminal processing module, and the output of the inverting terminal processing module is connected to the inverting input terminal of the voltage comparator.
The high-potential section capacitor array also comprises a unit capacitor Cc, a sampling signal is input into the unit capacitor Cc, and the sampling signal can replace the sampling of the low-potential section capacitor, so that 2 is savedL-1 switch.
Further, the calculation formula of the total capacitance number of the capacitor array is as follows:
Figure BDA0003376529380000021
wherein, CtotIs the total capacitance of the capacitor array, CuThe unit capacitance is represented, L represents the number of low-potential stage bits, M represents the number of high-potential stage bits, M + L is equal to N, N is the number of bits of the successive approximation analog-to-digital converter, and an equal sign is established if and only if M is equal to L.
The relation among the common mode level Vcm, the in-phase reference level VRP and the reversed phase reference level VRN is as follows: vcm 1/2(VRP + VRN).
The successive approximation type analog-to-digital converter is 10bit, the same-phase end low-potential section capacitor array consists of 4 unit capacitor groups including C1, C2, C3 and C4, and the same-phase end high-potential section capacitor array consists of 6 capacitor groups including unit capacitor Cc, C5, C6, C7, C8, C9 and C9 s; the capacitor bank C1 has 1 unit capacitor, the capacitor bank C2 has 2 unit capacitors connected in parallel, the capacitor bank C3 has 4 unit capacitors connected in parallel, and the capacitor bank C4 has 8 unit capacitors connected in parallel; the capacitor bank C5 has 1 unit capacitor, the capacitor bank C6 is formed by connecting 2 unit capacitors in parallel, the capacitor bank C7 is formed by connecting 4 unit capacitors in parallel, the capacitor bank C8 is formed by connecting 8 unit capacitors in parallel, the capacitor bank C9 is formed by connecting 8 unit capacitors in parallel, and the capacitor bank C9s is formed by connecting 8 unit capacitors in parallel.
The in-phase end switch control array comprises 10 PMOS tubes M1-M10 and 18 NMOS tubes M11-M28; wherein, the source of PMOS tube M1-M10 is connected with level VRP, the grid is connected with feedback signal P <1> -P <9> and P <9s > respectively; the source electrodes of the NMOS tubes M11-M18 are connected with a common mode level Vcm, and the grid electrodes are respectively connected with feedback signals M <1> to M <8 >; the source electrodes of the NMOS tubes M19-M28 are connected with the inverted reference level VRN, and the grid electrodes are respectively connected with feedback signals N <1> -N <9> and N <9s >.
The drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M11 and the drain electrode of the NMOS transistor M19 are connected to form a node Sp1The drain of the PMOS transistor M2, the drain of the NMOS transistor M12 and the drain of the NMOS transistor M20 are connected to form a node Sp2The drain of the PMOS transistor M3, the drain of the NMOS transistor M13 and the drain of the NMOS transistor M21 are connected to form a node Sp3(ii) a The drain electrode of the PMOS transistor M4, the drain electrode of the NMOS transistor M14 and the drain electrode of the NMOS transistor M22 are connected to form a node Sp4The drain of the PMOS transistor M5, the drain of the NMOS transistor M15 and the drain of the NMOS transistor M23 are connected to form a node Sp5The drain of the PMOS transistor M6, the drain of the NMOS transistor M16 and the drain of the NMOS transistor M24 are connected to form a node Sp6The drain of the PMOS transistor M7, the drain of the NMOS transistor M17 and the drain of the NMOS transistor M25 are connected to form a node Sp7The drain of the PMOS transistor M8, the drain of the NMOS transistor M18 and the drain of the NMOS transistor M26 are connected to form a node Sp8The drain electrode of the PMOS tube M9 and the drain electrode of the NMOS tube M27 are connected to form a node Sp9(ii) a The drain electrode of the PMOS transistor M10 is connected with the drain electrode of the NMOS transistor M28 to form a node Sp9s。
The in-phase end sampling circuit comprises 7 PMOS tubes M1, M5, M6, M9, M10, M13 and M14, and 8 NMOS tubes M2, M3, M4, M7, M8, M11, M12 and M15. Wherein, the source of the PMOS transistor M1 is connected to the non-inverting input signal VipThe gate of the NMOS transistor M2 is connected to the clock signal NC _2, the drain of the NMOS transistor M2 is connected to the clock signal NC _2, the source of the NMOS transistor M2 is connected to the common mode level VCM, and the source of the NMOS transistor M3 is connected to the non-inverting input signal VipThe grid is connected with a clock signal C _2, the drain is connected with the drain of M1 and the drain of M2, and the node is also connected with the lower plate of a coupling capacitor Cs in the capacitor array; the drain of the NMOS transistor M4 is connected to the positive input signal VipThe grid is connected with a clock signal C _2, the source electrode of the grid is connected with the source electrode of the PMOS pipe M5 and is simultaneously connected with the switch control array node Sp5The drain of the PMOS transistor M5 is connected with the positive phase input signal VipThe grid is connected with a clock signal NC _ 2; the source of the PMOS transistor M6 is connected with the positive phase input signal VipThe grid is connected with a clock signal NC-2, the drain is connected with the drain of an NMOS tube M7 and is also connected with a node S in a switch control arrayp6(ii) a The source of the NMOS transistor M7 is connected with the positive phase input signal VipGrid is connected to timeA clock signal C _ 2; the drain of the NMOS transistor M8 is connected to the positive input signal VipThe grid is connected with the clock signal C _2, the source is connected with the source of the PMOS pipe M9 and is also connected with the node S of the switch control arrayp7The drain of the PMOS transistor M9 is connected with the non-inverting input signal VipThe grid is connected with a clock signal NC _ 2; the source electrode of the PMOS tube M10 is connected with a positive phase input signal VipThe grid is connected with a clock signal NC-2, the drain is connected with the drain of an NMOS tube M11 and is also connected with a switch control array node Sp8The source of the NMOS transistor M11 is connected to the positive input signal VipThe grid is connected with a clock signal C _ 2; the drain of the NMOS transistor M12 is connected to the positive input signal VipThe grid is connected with the clock signal C _2, the source is connected with the source of the PMOS pipe M13, and the grid is connected with the node S of the switch control arrayp9sThe drain of the PMOS transistor M13 is connected to the positive input signal VipThe grid is connected with a clock signal NC _ 2; the source of the PMOS transistor M14 is connected with the positive phase input signal VipThe grid is connected with the clock signal NC _2, the drain is connected with the NMOS tube M15 and is connected with the node Sp9The source of the NMOS transistor M15 is connected to the positive phase input signal VipAnd the grid is connected with a clock signal C _ 2.
Has the advantages that: compared with the prior art, the invention has the following advantages: 1. the capacitor array adopts a segmented capacitor structure, and utilizes charge transfer to ensure that the process of reference establishment is not needed in the first comparison, thereby saving the expense of a one-bit capacitor bank; the invention provides a sectional calculation method of the minimum capacitance quantity, and the minimum capacitance quantity which can be used by sectional capacitance is obtained through calculation, so that the capacitance quantity of a capacitance array is not increased in an exponential form any more, and the required capacitance quantity is effectively reduced; meanwhile, a common mode level Vcm is introduced as a reference voltage, so that the dynamic energy consumption of the switch in the conversion process is greatly reduced; 2. a grid voltage bootstrap switch with large energy consumption and large area is not adopted, a simpler CMOS complementary switch is used as a switch, a unit capacitor is further added in a high potential section, and a sampling signal is input into the unit capacitor, so that the low potential section capacitor does not need to be sampled, and the switch expense is saved; 3. by splitting the highest weight recombination capacitor in the high potential section, the common mode level Vcm is not required to be switched in through a switch in the charge transfer stage, and therefore the switching overhead can be saved by nearly 20%.
Drawings
FIG. 1 is a circuit diagram of a 10-bit SAR ADC according to the present invention;
fig. 2 is a connection diagram of the capacitor array, the switch control circuit and the sampling switch circuit of the 10-bit SAR ADC normal phase processing module according to the present invention (the normal phase processing module is symmetrical to the inverse phase processing module);
FIG. 3 is a graph of a segmented capacitance structure analysis of an N-bit SAR ADC according to the present invention;
fig. 4 is an equivalent circuit diagram of a segmented capacitor structure of an N-bit SAR ADC according to the present invention, wherein (a) is an equivalent circuit diagram of a high-potential segment capacitor array, and (b) is an equivalent circuit diagram of a low-potential segment capacitor array.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Taking a 10-bit successive approximation type analog-to-digital converter as an example, a circuit diagram of a successive approximation type analog-to-digital converter with reduced capacitance and switch number according to the present invention is shown in fig. 1. The structure includes a capacitor array 10, a switch control circuit, a sampling circuit, a Vcm sampling circuit 40, a voltage comparator 50, and a SAR logic control circuit 60. The capacitor array 10 is further divided into a positive phase capacitor array 101 and a negative phase capacitor array 102; the switch control circuit comprises a positive-phase end switch control circuit 201 and a negative-phase end switch control circuit 202; the sampling circuit includes a non-inverting terminal sampling circuit 301 and an inverting terminal sampling circuit 302.
The positive side capacitor array 101 can receive the positive side input signal V through the positive side switch control circuit 201 and the positive side sampling circuit 301ipThe inverting terminal capacitor array 102 can access the inverting input signal V through the inverting terminal switch control circuit 202 and the inverting terminal sampling circuit 302inThe positive phase end capacitor array 101 is connected with the positive phase input end of the voltage comparator 50, and the negative phase end capacitor array 102 is connected with the negative phase input end of the voltage comparator 50; output of voltage comparator 50 and SAR logicThe input terminals of the edit control circuit 60 are connected; the output end of the SAR logic control circuit 60 outputs a positive phase switch control signal SLP and a negative phase switch control signal SLN, the positive phase switch control signal SLP is connected to the positive phase switch control circuit 201, and the negative phase switch control signal SLN is connected to the negative phase switch control circuit 202. The switch control circuit forms a double-end signal input, the capacitor array 10 is double-end input and output, and the used signal is a differential input signal. Wherein the common mode level Vcm takes the values: vcm is 1/2(VRP + VRN), VRP is the positive phase reference level, VRN is the negative phase reference level. The Vcm sampling circuit 40 switches in the common mode level Vcm to the free point of the capacitor array 10 through the sampling switch, and the switch is turned off after the sampling is finished.
The positive-phase-end capacitor array 101 includes a positive-phase-end low-potential-section capacitor array, a coupling capacitor Cs, and a positive-phase-end high-potential-section capacitor array; the positive phase end low potential section consists of 4 unit capacitor groups including C1, C2, C3 and C4, and the positive phase end high potential section consists of 7 unit capacitor groups including Cc, C5, C6, C7, C8, C9 and C9 s. The highest weight bit of the high-potential segment at the positive phase end is composed of split capacitor groups C9 and C9 s. The coupling capacitor Cs connects the capacitor arrays of the low potential section and the high potential section in series, and the capacitors in each capacitor array are connected in parallel. Each capacitor array is arranged in a binary weight sequence, C1 in the low-potential capacitor array at the positive-phase end has 1 unit capacitor, C2 is formed by connecting 2 unit capacitors in parallel, C3 is formed by connecting 4 unit capacitors in parallel, C4 is formed by connecting 8 unit capacitors in parallel, and 15 unit capacitors are needed in total; cc in the positive-phase-end high-potential-section capacitor array is provided with 1 unit capacitor, C5 is provided with 1 unit capacitor, C6 is formed by connecting 2 unit capacitors in parallel, C7 is formed by connecting 4 unit capacitors in parallel, C8 is formed by connecting 8 unit capacitors in parallel, C9 is formed by connecting 8 unit capacitors in parallel, and C9s is formed by connecting 8 unit capacitors in parallel, so that 32 unit capacitors are required; the value of the coupling capacitor Cs is equal to the unit capacitance value, so the total capacitance of the positive phase end capacitor array is 48 unit capacitors.
The top plates of 4 unit capacitor groups in the positive-phase-end low-potential capacitor array and the top plates of 7 unit capacitor groups in the high-potential capacitor array are connected in series through coupling capacitors Cs to form a common point, and are connected with the positive-phase input end of a voltage comparator 50 and a common-mode level Vcm through a Vcm sampling circuit 40; is justThe bottom plate (free point) of the phase end high potential section capacitor array (except the highest weight capacitor bank C9 and the capacitor bank C9s) can be connected with a common mode level Vcm, a positive phase reference level VRP, a reverse phase reference level VRN or connected with a positive phase input signal V through the positive phase end switch control circuit 201ipThe bottom plates of the highest weighted capacitor banks C9 and C9s can be connected to the positive phase reference level VRP, the negative phase reference level VRN or the positive phase input signal V through the positive phase switch control circuit 201ip(ii) a The bottom plates (free points) of the four unit capacitor groups of the positive-phase-end low-potential capacitor array can be connected with a common-mode level Vcm, a positive-phase reference level VRP and a reverse-phase reference level VRN through a positive-phase-end switch control circuit 201.
Referring to fig. 2, the positive side switch control array 201 includes 10 PMOS transistors M1-M10, and 18 NMOS transistors M11-M28.
Wherein, the sources of the PMOS transistors M1-M10 are connected with the level VRP, and the gates are respectively connected with the feedback signal P<i>～P<9>And P <9s>(ii) a The source electrodes of the NMOS transistors M11-M18 are connected with a common mode level Vcm, and the grid electrodes are respectively connected with a feedback signal M<1>～M<8>(ii) a The source electrodes of the NMOS transistors M19-M28 are connected with the inverted reference level VRN, and the grid electrodes are respectively connected with the feedback signal N<1>～N<9>And N <9s>(ii) a The drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M11 and the drain electrode of the NMOS transistor M19 are connected to form a node Sp1The drain of the PMOS transistor M2, the drain of the NMOS transistor M12 and the drain of the NMOS transistor M20 are connected to form a node Sp2The drain of the PMOS transistor M3, the drain of the NMOS transistor M13 and the drain of the NMOS transistor M21 are connected to form a node Sp3(ii) a The drain electrode of the PMOS transistor M4, the drain electrode of the NMOS transistor M14 and the drain electrode of the NMOS transistor M22 are connected to form a node Sp4The drain of the PMOS transistor M5, the drain of the NMOS transistor M15 and the drain of the NMOS transistor M23 are connected to form a node Sp5The drain of the PMOS transistor M6, the drain of the NMOS transistor M16 and the drain of the NMOS transistor M24 are connected to form a node Sp6The drain of the PMOS transistor M7, the drain of the NMOS transistor M17 and the drain of the NMOS transistor M25 are connected to form a node Sp7The drain of the PMOS transistor M8, the drain of the NMOS transistor M18 and the drain of the NMOS transistor M26 are connected to form a node Sp8The drain electrode of the PMOS tube M9 and the drain electrode of the NMOS tube M27 are connected to form a node Sp9(ii) a The drain electrode of the PMOS transistor M10 is connected with the drain electrode of the NMOS transistor M28 to form a node Sp9s。
The width and length of the PMOS tube M1 are 3.7um/550nm, the width and length of the PMOS tube M2 are 4.6um/550nm, the width and length of the PMOS tube M3 are 9.2um/550nm, the width and length of the PMOS tube M4 are 13.4um/550nm, the width and length of the PMOS tube M5 are 3.7um/550nm, the width and length of the PMOS tube M6 are 4.6um/550nm, the width and length of the PMOS tube M7 are 9.2um/550nm, the width and length of the PMOS tube M8, the width and length of the PMOS tube M9 are 18.4um/550nm, the width and length of the PMOS tube M6 are 4um/550nm, the width and length of the PMOS tube M7 are 4um/550nm, the width and length of the PMOS tube M8, the M9 and the M10 are all 18.4um/550 nm; NMOS tube M11 is 1.7um/500nm, NMOS tube M12 is 2.2um/500nm, NMOS tube M13 is 4.2um/500nm, NMOS tube M14 is 8.4um/500nm, NMOS tube M15 is 1.7um/500nm, NMOS tube M16 is 2.2um/500nm, NMOS tube M17 is 4.2um/500nm, and NMOS tube M18 is 8.4um/500 nm; NMOS tubes M19 and M23 are both 1.1um/500nm, NMOS tubes M20 and M24 are both 1.4um/50nm, NMOS tubes M21 and M25 are both 2.8um/500nm, and NMOS tubes M22, M26, M27 and M28 are all 5.6um/500 nm.
The positive-phase-end sampling circuit 301 includes 7 PMOS transistors M1, M5, M6, M9, M10, M13, and M14, and 8 NMOS transistors M2, M3, M4, M7, M8, M11, M12, and M15.
Wherein, the source of the PMOS transistor M1 is connected to the non-inverting input signal VipThe gate of the NMOS transistor M2 is connected to the clock signal NC _2, the drain of the NMOS transistor M2 is connected to the clock signal NC _2, the source of the NMOS transistor M2 is connected to the common mode level VCM, and the source of the NMOS transistor M3 is connected to the non-inverting input signal VipThe grid is connected with a clock signal C _2, the drain is connected with the drain of M1 and the drain of M2, and the node is also connected with the lower plate of a coupling capacitor Cs in the capacitor array; the drain of the NMOS transistor M4 is connected to the positive input signal VipThe grid is connected with a clock signal C _2, the source electrode of the grid is connected with the source electrode of the PMOS pipe M5 and is simultaneously connected with the switch control array node Sp5The drain of the PMOS transistor M5 is connected with the positive phase input signal VipThe grid is connected with a clock signal NC _ 2; the source of the PMOS transistor M6 is connected with the positive phase input signal VipThe grid is connected with a clock signal NC-2, the drain is connected with the drain of an NMOS tube M7 and is also connected with a node S in a switch control arrayp6(ii) a The source of the NMOS transistor M7 is connected with the positive phase input signal VipThe grid is connected with a clock signal C _ 2; the drain of the NMOS transistor M8 is connected to the positive input signal VipThe grid is connected with the clock signal C _2, the source is connected with the source of the PMOS pipe M9 and is also connected with the node S of the switch control arrayp7The drain of the PMOS transistor M9 is connected with the non-inverting input signal VipThe grid is connected with a clock signal NC _ 2; PMOS transistor M10 source electrode accessPositive phase input signal VipThe grid is connected with a clock signal NC-2, the drain is connected with the drain of an NMOS tube M11 and is also connected with a switch control array node Sp8The source of the NMOS transistor M11 is connected to the positive input signal VipThe grid is connected with a clock signal C _ 2; the drain of the NMOS transistor M12 is connected to the positive input signal VipThe grid is connected with the clock signal C _2, the source is connected with the source of the PMOS pipe M13, and the grid is connected with the node S of the switch control arrayp9sThe drain of the PMOS transistor M13 is connected to the positive input signal VipThe grid is connected with a clock signal NC _ 2; the source of the PMOS transistor M14 is connected with the positive phase input signal VipThe grid is connected with the clock signal NC _2, the drain is connected with the NMOS tube M15 and is connected with the node Sp9The source of the NMOS transistor M15 is connected to the positive phase input signal VipAnd the grid is connected with a clock signal C _ 2.
The width-length ratio of the PMOS tube M1 is 3.7um/550nm, the NMOS tube M2 is 1.7um/500nm, the NMOS tubes M3 and M4 are both 1.1um/500nm, the PMOS tube M5 is 3.7um/500nm, the PMOS tube M6 is 5.5 um/550nm, the NMOS tube M7 is 1.7um/500nm, the NMOS tube M8 is 2.8um/500nm, the PMOS tube M9 is 9.2um/550nm, the PMOS tubes M10, M13 and M14 are both 18.4um/550nm, and the NMOS tubes M11, M12 and M15 are all 5.6um/500 nm.
Referring to fig. 2, a specific connection diagram of the capacitor array and the switch used in the present embodiment is shown. Wherein, according to the conventional structure, 2 is required for SARADC of NbitNThe unit capacitors, 10 bits designed according to this embodiment, require 1024 unit capacitors in total, and the number of capacitors is too large, so that the implementation is not easy. So a segmented capacitor structure is introduced, and the capacitor array is divided into two small arrays by the coupling capacitor Cs. The calculation method of the segmented structure with the minimum capacitance quantity is provided as follows, the SAR ADC structure with the minimum unit capacitance quantity can be obtained, and the capacitance quantity can be further reduced by combining other methods on the basis.
Referring to fig. 3, a classic capacitor array with a segmented structure is provided, if a step signal with an amplitude of V is respectively input at a point (i) and a point (ii), a point V is calculated0The output signal change amount of (A) and (B) of FIG. 4 is obtained by simplifying the circuit, which has:
V01＝kCu(Cs+CL)V/X (1)
V02＝(2L-1CsCu)V/X (2)
wherein, CuDenotes a unit capacitance, k denotes k CuCs is coupling capacitance, CLRepresents the total capacitance of the low potential section, CMIs the total capacitance number of the high potential section, L represents the bit number of the low potential section, M represents the bit number of the high potential section, Cd is the grounding capacitance, and the node V0A first point and a second point; specifically, the method comprises the following steps: cL＝(2L-1)Cu+Cd2，CM＝(2M-1)kCu+Cd1，X＝CM(Cs+CL)+CsCLAnd M + L ═ N. To maintain the correct weighting of the array, ensure ADC linearity, should have V01＝2V02The following can be obtained:
k(Cs+Cu)＝2LCs (3)
further finishing to obtain:
Figure BDA0003376529380000071
from CLThe total capacitance is known as:
CL≥(2L-1)Cu (5)
combining formula (4) and formula (5), making k equal to 1, yields:
CL＝(2L-1)Cu (6)
Cs＝Cu，Cd2＝0，Cd1＝Cu (7)
thus, in combination of equations (7) and (8), the total capacitance number of the segmented structure capacitor is:
Figure BDA0003376529380000072
in the formula (8), an equal sign is established if and only if M ═ L. That is, for an N-bit SAR ADC, when the number of high and low bits is equal, the minimum number of capacitors is obtained and the linearity requirement of the ADC is maintained. In combination with the charge transfer stage in bottom plate sampling, charge is transferred to the capacitor top plate(common point) when the charge is inputted to two input ends of the comparator directly, the first comparison can be made, so that one-bit capacitor group is saved, so that M or L can be reduced by one on the original basis, i.e. the total capacitance is changed into Ctot＝2M-1+2LOr Ctot＝2M+2L-1. The embodiment needs 96 unit capacitors, and can save about 96% of the capacitor number compared with the traditional capacitor array, and can save 37% -90% of the capacitor number compared with other forms of segmented capacitor structures.
In this embodiment, by adding a capacitor Cc in the high-voltage segment, the value of which is equal to the unit capacitor, and inputting the sampling signal to the capacitor Cc, the low-voltage segment does not need to be sampled, and 2 can be savedL-1 switch; in addition, the highest weight group of the high potential section obtains the common mode voltage Vcm by splitting the capacitor group, but not directly accessing the Vcm level, so 2 can be saved by the highest weight group bitsMA Vcm switch; therefore, in the present embodiment, a total of 154 switches are required, which saves nearly 20% of the number of switches compared to the original structure.

Claims (9)

1. A successive approximation type analog-to-digital converter for reducing the number of capacitors and switches comprises a DAC module, a voltage comparator and an SAR logic control circuit which are electrically connected in sequence, wherein the SAR logic control circuit outputs a switch control signal to control the output of the DAC module, and the voltage comparator is used for finishing comparison, and the successive approximation type analog-to-digital converter is characterized in that: the DAC module comprises a same-phase end processing module and an opposite-phase end processing module, the same-phase end processing module comprises a same-phase end capacitor array, a same-phase end switch control circuit and a same-phase end sampling circuit, the same-phase end capacitor array is divided into a low-potential section capacitor array and a high-potential section capacitor array by serially connected coupling capacitors, each section of capacitor array is a capacitor which is connected in parallel in a binary weight sequence, the highest weight bit of the high-potential section capacitor array is composed of split capacitor groups C9 and C9s, and the number of the parallel capacitors in the two split capacitor groups is equal; the free points of the high-potential capacitor array at the same phase end except the split capacitor group are selectively connected with a common-mode level Vcm, a same-phase reference level VRP and an opposite-phase reference level through a same-phase end switch control circuitVRN or inphase input signal VipThe free point of the split capacitor bank is selectively connected with an in-phase reference level VRP, an inverted reference level VRN or an in-phase input signal V through an in-phase end switch control circuitip(ii) a The common point of the in-phase end capacitor array is used as the output of the in-phase end processing module and is connected with the non-inverting input end of the voltage comparator; the circuit structure of the inverting terminal processing module is symmetrical to that of the non-inverting terminal processing module, and the output of the inverting terminal processing module is connected to the inverting input terminal of the voltage comparator.
2. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 1, wherein: the high-potential section capacitor array also comprises a unit capacitor Cc, a sampling signal is input into the unit capacitor Cc, and the sampling signal can replace the sampling of the low-potential section capacitor, so that 2 is savedL-1 switch.
3. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 2, wherein: the successive approximation type analog-to-digital converter is 10bit, the same-phase end low-potential section capacitor array consists of 4 unit capacitor groups including C1, C2, C3 and C4, and the same-phase end high-potential section capacitor array consists of 6 capacitor groups including unit capacitor Cc, C5, C6, C7, C8, C9 and C9 s; the capacitor bank C1 has 1 unit capacitor, the capacitor bank C2 is formed by connecting 2 unit capacitors in parallel, the capacitor bank C3 is formed by connecting 4 unit capacitors in parallel, and the capacitor bank C4 is formed by connecting 8 unit capacitors in parallel; the capacitor bank C5 has 1 unit capacitor, the capacitor bank C6 is formed by connecting 2 unit capacitors in parallel, the capacitor bank C7 is formed by connecting 4 unit capacitors in parallel, the capacitor bank C8 is formed by connecting 8 unit capacitors in parallel, the capacitor bank C9 is formed by connecting 8 unit capacitors in parallel, and the capacitor bank C9s is formed by connecting 8 unit capacitors in parallel.
4. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 3, wherein: the in-phase end switch control array comprises 10 PMOS tubes M1-M10 and 18 NMOS tubes M11-M28; wherein, the sources of PMOS tubes M1-M10 are connected with level VRP, and the gates are respectively connected with feedback signals P <1> -P <9> and P <9s >; the source electrodes of the NMOS tubes M11-M18 are connected with a common mode level Vcm, and the grid electrodes are respectively connected with feedback signals M <1> -M <8 >; the sources of the NMOS transistors M19-M28 are connected with the inverted reference level VRN, and the gates are respectively connected with feedback signals N <1> -N <9> and N <9s >.
5. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 4, wherein: the drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M11 and the drain electrode of the NMOS transistor M19 are connected to form a node Sp1The drain of the PMOS transistor M2, the drain of the NMOS transistor M12 and the drain of the NMOS transistor M20 are connected to form a node Sp2The drain of the PMOS transistor M3, the drain of the NMOS transistor M13 and the drain of the NMOS transistor M21 are connected to form a node Sp3(ii) a The drain electrode of the PMOS transistor M4, the drain electrode of the NMOS transistor M14 and the drain electrode of the NMOS transistor M22 are connected to form a node Sp4The drain of the PMOS transistor M5, the drain of the NMOS transistor M15 and the drain of the NMOS transistor M23 are connected to form a node Sp5The drain of the PMOS transistor M6, the drain of the NMOS transistor M16 and the drain of the NMOS transistor M24 are connected to form a node Sp6The drain of the PMOS transistor M7, the drain of the NMOS transistor M17 and the drain of the NMOS transistor M25 are connected to form a node Sp7The drain of the PMOS transistor M8, the drain of the NMOS transistor M18 and the drain of the NMOS transistor M26 are connected to form a node Sp8The drain electrode of the PMOS tube M9 and the drain electrode of the NMOS tube M27 are connected to form a node Sp9(ii) a The drain electrode of the PMOS transistor M10 is connected with the drain electrode of the NMOS transistor M28 to form a node Sp9s。
6. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 3, wherein: the in-phase end sampling circuit comprises 7 PMOS tubes M1, M5, M6, M9, M10, M13 and M14, and 8 NMOS tubes M2, M3, M4, M7, M8, M11, M12 and M15.
7. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 6, wherein: the source of the PMOS transistor M1 is connected with the positive phase input signal VipThe gate is connected with the clock signal NC _2, the drain is connected with the drain of the NMOS tube M2, the gate of the NMOS tube M2 is connected with the clock signal NC _2 and the sourceThe pole is connected to the common mode level VCM, and the source of the NMOS tube M3 is connected to the non-inverting input signal VipThe grid is connected with a clock signal C _2, the drain is connected with the drain of M1 and the drain of M2, and the node is also connected with the lower plate of a coupling capacitor Cs in the capacitor array; the drain of the NMOS transistor M4 is connected to the positive input signal VipThe grid is connected with a clock signal C _2, the source electrode of the grid is connected with the source electrode of the PMOS pipe M5 and is simultaneously connected with the switch control array node Sp5The drain of the PMOS transistor M5 is connected with the positive phase input signal VipThe grid is connected with a clock signal NC _ 2; the source of the PMOS transistor M6 is connected with the positive phase input signal VipThe grid is connected with a clock signal NC-2, the drain is connected with the drain of an NMOS tube M7 and is also connected with a node S in a switch control arrayp6(ii) a The source of the NMOS transistor M7 is connected with the positive phase input signal VipThe grid is connected with a clock signal C _ 2; the drain of the NMOS transistor M8 is connected to the positive input signal VipThe grid is connected with the clock signal C _2, the source is connected with the source of the PMOS pipe M9 and is also connected with the node S of the switch control arrayp7The drain of the PMOS transistor M9 is connected with the non-inverting input signal VipThe grid is connected with a clock signal NC _ 2; the source electrode of the PMOS tube M10 is connected with a positive phase input signal VipThe grid is connected with a clock signal NC-2, the drain is connected with the drain of an NMOS tube M11 and is also connected with a switch control array node Sp8The source of the NMOS transistor M11 is connected to the positive input signal VipThe grid is connected with a clock signal C _ 2; the drain of the NMOS transistor M12 is connected to the positive input signal VipThe grid is connected with the clock signal C _2, the source is connected with the source of the PMOS pipe M13, and the grid is connected with the node S of the switch control arrayp9sThe drain of the PMOS transistor M13 is connected to the positive input signal VipThe grid is connected with a clock signal NC _ 2; the source of the PMOS transistor M14 is connected with the positive phase input signal VipThe grid is connected with the clock signal NC _2, the drain is connected with the NMOS tube M15 and is connected with the node Sp9The source of the NMOS transistor M15 is connected to the positive phase input signal VipAnd the grid is connected with a clock signal C _ 2.
8. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 1 wherein the total capacitance of the capacitor array is calculated by the formula:
Figure FDA0003376529370000021
wherein, CtotIs the total capacitance of the capacitor array, CuThe unit capacitance is represented, L represents the number of low-potential stage bits, M represents the number of high-potential stage bits, M + L is equal to N, N is the number of bits of the successive approximation analog-to-digital converter, and an equal sign is established if and only if M is equal to L.
9. The reduced capacitance and switching count successive approximation analog-to-digital converter of claim 1 wherein the common mode level Vcm, the in-phase reference level VRP and the reverse phase reference level VRN have the relationship: vcm 1/2(VRP + VRN).
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